61 Commits (master)

Author	SHA1	Message	Date
Andrei Vlad LUTAS	f32c0373ac	Incremented revision to 2.1.4.	3 weeks ago
Andrei Vlad LUTAS	4bc4636765	https://github.com/bitdefender/bddisasm/issues/88 - removed (no longer needed) assert.	3 weeks ago
Andrei Vlad LUTAS	37a8c94bc7	Applied some of the syntax recomandations from https://cdrdv2.intel.com/v1/dl/getContent/817241.	2 months ago
Andrei Vlad LUTAS	02cbe6a298	https://github.com/bitdefender/bddisasm/issues/87 - added missing `R` access for the `rIP` operand for `SYSCALL` instructions; added missing `SCS`, `rCX` and `rDX` operands for `SYSEXIT` instruction.	2 months ago
Andrei Vlad LUTAS	3df189f093	https://github.com/bitdefender/bddisasm/issues/87 - Fixed `CALL` instruction access for `rIP` operand - it must include read access, as the instruction pointer is saved on the stack.	2 months ago
Andrei Vlad LUTAS	fad9c7e35c	BDDISASM v2.1.0 release - please consult the CHANGELOG for details about the modifications.	2 months ago
Andrei Vlad LUTAS	f53cbc51e2	Added support for new Intel ISA, per Intel® Architecture Instruction Set Extensions and Future Features document #319433-049 (June 2023): AVX-NNI-INT16, SHA512, SM3, SM4, TSE.	9 months ago
BITDEFENDER\vlutas	124521beb5	Added support for Intel AMX-COMPLEX instructions.	1 year ago
BITDEFENDER\vlutas	7a254037b0	Added support for AMD RMPQUERY instruction.	2 years ago
BITDEFENDER\vlutas	9ba1e6a2f9	Added support for new Intel instructions, per Intel ISA extensions document #319433-046 (September 2022): PREFETCHITI, RAO-INT, CMPCCXADD, WRMSRNS, MSRLIST, AMX-FP16, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8. ... Multiple minor fixes to existing instructions. Moved x86 decoding tests in a separate directory & improved the test script.	2 years ago
BITDEFENDER\vlutas	4596dbda51	Add copyright info when auto-generating files.	2 years ago
BITDEFENDER\vlutas	47da322ea5	Improved upper bits handling for SSE/AVX operations. ... Improved POPF handling when 16 bit operand size is used. Fixed typo in PUNPCKLBW emulation.	2 years ago
BITDEFENDER\vlutas	2fc491d51d	Handle reserved bits in RFLAGS when setting the entire register value.	2 years ago
BITDEFENDER\vlutas	f62c8a2238	https://github.com/bitdefender/bddisasm/issues/70 - fixed OF setting on ROR.	2 years ago
BITDEFENDER\vlutas	d3fd900903	Fixed OF on SHL and SHR with one bit shifts.	2 years ago
BITDEFENDER\vlutas	bf81c647e3	Make sure all flags are set for CMPXCHG (this was left intentionally incomplete). ... Make sure we clear upper bits of the 256/512 bit SSE register.	2 years ago
BITDEFENDER\vlutas	6dda2c122c	Make sure upper 32 bit of a CMOV destination register is cleared to 0 even if the condition is not satisfied	2 years ago
BITDEFENDER\vlutas	1805a9edec	Fixed flag setting for ADC, SBB, SAR and IMUL instructions.	2 years ago
BITDEFENDER\vlutas	fe6a937f51	Switched to internally defined types. ... WRUSSD and WRUSSQ cannot be executed when CPL != 0.	2 years ago
BITDEFENDER\vlutas	63e3ee22a9	Fixed High8 handling in NdGetFullAccessMap.	2 years ago
BITDEFENDER\vlutas	2f50ce9b4e	Improved REG_ID macros - make sure we include block addressing and High8 designator in the reg ID. Alsom, make sure the register size fits in, since the new tile register can be 1K in size, which previously overflowed...	2 years ago
BITDEFENDER\vlutas	433e723e07	Implemented a reverse oprand lookup table. It holds pointers to relevant operands inside INSTRUX, for quick lookup. ... Moved helper functions in bdhelpers.c. Added a dedicated BranchInfo field inside INSTRUX, containing the most relevant branch information.	3 years ago
BITDEFENDER\vlutas	412f065965	Moved the formatting function in a dedicated source file. ... Added support for SIDT and RDTSC in bdshemu.	3 years ago
Andrei Vlad LUTAS	08096172cc	Multiple improvements ... - New shemu flag - SHEMU_FLAG_SIDT, set when sheu encounters a SIDT in ring0. - Added the CET Tracked flag to SYSCLAL, SYSENTER and INT n instructions. - Fixed Do Not Track prefix recognition for CALL and JMP in long-mode. - Fixed MONITOR and MONITORX implicit operands - the rAX register encodes a virtual address that will be used as the monitored range. That address is subject to a 1 byte load. - Fixed RMPADJUST and RMPUPDATE implicit operands - the rAX register encodes a virtual address, and the rCX register encodes a virtual address of the RMP updated entry.	3 years ago
Andrei Vlad LUTAS	5a617986b7	Added new shemu flag: SHEMU_FLAG_SUD_ACCESS is raised whenever the code accesses the SharedUserData page.	3 years ago
Andrei Vlad LUTAS	c8735b437a	Fixed NEG emulation - make sure flags are set.	3 years ago
Andrei Vlad LUTAS	f6050661d5	Multiple improvements in bdshemu ... Fixed an emulation bug for MOVZX and MOVSX instructions (https://github.com/bitdefender/bddisasm/issues/48) New shellcode flag - call tot Wow32 reserved. New shellcode flag - heaven's gate. New shellcode flag - stack-pivot. Moved bdshemu tests in a password protected zip file, so it doesn't trigger AV detections.	3 years ago
Andrei Vlad LUTAS	76d92e73c2	Multiple changes ... - Add support for AVX512-FP16 instructions, as per https://software.intel.com/content/www/us/en/develop/download/intel-avx512-fp16-architecture-specification.html - Bug fix: zeroing with no masking is not supported, so return an error if we encounter such encodings - Bug fix: ignore VEX/EVEX.W field outside 64 bit mode for some instructions - Several other minor fixes and improvements	3 years ago
Andrei Vlad LUTAS	c3a6ea1c25	Updated SEAMCALL specs according to Intel® Trust Domain CPU Architectural Extensions 343754-002US May 2021.	3 years ago
Andrei Vlad LUTAS	d053de409f	Although not stated in the SDM, VMCALL, VMLAUNCH, VMRESUME and VMXOFF refuse any prefix (66, F3, F2).	3 years ago
Andrei Vlad LUTAS	072f6e059b	Build improvements ... Exclude string constants from build if BDDISASM_NO_FORMAT is defined. Use extern "C" when declaring the public bddisasm/bdshemu functions. Include wmmintrin.h for AES intrinisics when building using LLVM/clang.	3 years ago
Andrei Vlad LUTAS	f7bf814bbc	Flag the rIP operand of conditional branches as being conditionally read/write instead of plain read/write. ... Bypass self-writes option in bdshemu - if set, bdshemu will not proceed to commit modifications made by the shellcode to itself.	3 years ago
Anichitei Ionel-Cristinel	a0e5d8f905	Increment revision	3 years ago
Andrei Vlad LUTAS	fccf11915d	Added support for Intel FRED and LKGS instructions.	3 years ago
Andrei Vlad LUTAS	f7be5a7bbd	Incremented version.	3 years ago
Andrei Vlad LUTAS	1eb1c9d0d2	Fixed https://github.com/bitdefender/bddisasm/issues/38.	3 years ago
Andrei Vlad LUTAS	98ea9e1d9a	Fixed https://github.com/bitdefender/bddisasm/issues/34, https://github.com/bitdefender/bddisasm/issues/35, https://github.com/bitdefender/bddisasm/issues/36 and https://github.com/bitdefender/bddisasm/issues/37.	3 years ago
Andrei Vlad LUTAS	f8a3011a49	Added support for AESDEC, AESDECLAST and AESIMC emulation, using compiler intrinsics - they will be used only if the SHEMU_OPT_SUPPORT_AES is set (so the integrator can properly check for AES-NI support in hardware). ... Fixed shemu option on Linux - make sure proper RIP is provided.	3 years ago
Ionel-Cristinel ANICHITEI	c1c3770cc6	Move bdhsemu.h to inc/	3 years ago
Ionel-Cristinel ANICHITEI	0af56019c2	Initial CMake support	3 years ago
Andrei Vlad LUTAS	e89f56289d	As per Intel SDM version 73 released in November 2020, make sure we don't decode 32-bit EVEX instructions that have EVEX.V' cleared, and 64-bit EVEX instructions that don't use EVEX.V' field, but have it cleared.	3 years ago
Andrei Vlad LUTAS	58197cc518	Removed support for PCOMMIT and CL1INVMB (not implemented by any x86/x64 CPUs), and marked MOV to/from test registers as being invalid in long mode. ... Fixed https://github.com/bitdefender/bddisasm/issues/24 Fixed https://github.com/bitdefender/bddisasm/issues/25 Fixed https://github.com/bitdefender/bddisasm/issues/26	3 years ago
Andrei Vlad LUTAS	bcf9a89d69	Fixed https://github.com/bitdefender/bddisasm/issues/22 and https://github.com/bitdefender/bddisasm/issues/23.	3 years ago
Andrei Vlad LUTAS	e26971b4f0	Added missing Default 64 flag for the ENTER instruction. ... On AMD, operand size is never forced to 64 bit - instead, it only defaults to 64 bit, which means that 0x66 can be used to encode 16 bit version of the instructions.	4 years ago
Andrei Vlad LUTAS	9652450125	Added support for UINTR, HRESET and AVX-VNNI instructions, as per Intel® Architecture Instruction Set Extensions Programming Reference 41 (October 2020).	4 years ago
Andrei Vlad LUTAS	4f8b030ddd	Added support for Intel Key Locker instructions, as per https://software.intel.com/content/www/us/en/develop/download/intel-key-locker-specification.html.	4 years ago
Andrei Vlad LUTAS	33078e4670	Added support for TDX instructions, per https://software.intel.com/content/dam/develop/external/us/en/documents/intel-tdx-cpu-architectural-specification.pdf.	4 years ago
Andrei Vlad LUTAS	ea28907359	Fix potential division error in bdshemu, when the destination operand is not large enough to hold the result.	4 years ago
Andrei Vlad LUTAS	1d43b7b1ba	Improved stack string detection heuristic: only consider registers which have been modified during emulation; registers which were provided as "input" can be ignored, as they most likely contain addresses or other data relevant to the emulated code. We are only interested in string dynamically built during our emulation.	4 years ago
Andrei Vlad LUTAS	356ed63916	Clarifying comments to the decode API arguments.	4 years ago