arno/bddisasm
1
0
Fork 0
mirror of https://github.com/bitdefender/bddisasm.git synced 2025-05-03 17:59:01 +00:00
Code Issues Releases Wiki Activity

Multiple changes

Browse Source 
- Add support for AVX512-FP16 instructions, as per https://software.intel.com/content/www/us/en/develop/download/intel-avx512-fp16-architecture-specification.html
- Bug fix: zeroing with no masking is not supported, so return an error if we encounter such encodings
- Bug fix: ignore VEX/EVEX.W field outside 64 bit mode for some instructions
- Several other minor fixes and improvements
This commit is contained in:
Andrei Vlad LUTAS 2021-07-08 12:40:39 +03:00
parent 5b8b67c596
commit 76d92e73c2
86 changed files with 501341 additions and 131800 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

343
bddisasm/bddisasm.c
View File

@ -619,7 +619,7 @@ NdFetchEvex(
return ND_STATUS_EVEX_WITH_PREFIX;
}
// Do the opcode independent checks. Opcode dependent checks are done when decoding each
// Do the opcode independent checks. Opcode dependent checks are done when decoding each instruction.
if (Instrux->Evex.zero != 0 || Instrux->Evex.one != 1 || Instrux->Evex.m == 0)
{
return ND_STATUS_INVALID_ENCODING;
@ -1242,25 +1242,32 @@ NdGetCompDispSize(
uint32_t MemSize
)
{
static const uint8_t fvszLut[2][2][4] =
{
{ { 16, 32, 64, 0 }, { 4, 4, 4, 0 }, },
{ { 16, 32, 64, 0 }, { 8, 8, 8, 0 }, },
};
static const uint8_t hvszLut[2][4] = { { 8, 16, 32, 0 }, { 4, 4, 4, 0 }, };
static const uint8_t fvszLut[4] = { 16, 32, 64, 0 };
static const uint8_t hvszLut[4] = { 8, 16, 32, 0 };
static const uint8_t qvszLut[4] = { 4, 8, 16, 0 };
static const uint8_t dupszLut[4] = { 8, 32, 64, 0 };
static const uint8_t fvmszLut[4] = { 16, 32, 64, 0 };
static const uint8_t hvmszLut[4] = { 8, 16, 32, 0 };
static const uint8_t qvmszLut[4] = { 4, 8, 16, 0 };
static const uint8_t ovmszLut[4] = { 2, 4, 8, 0 };
if (Instrux->HasBroadcast)
{
// If the instruction uses broadcast, then compressed displacement will use the size of the element as scale:
// - 2 when broadcasting 16 bit
// - 4 when broadcasting 32 bit
// - 8 when broadcasting 64 bit
return (uint8_t)MemSize;
}
switch (Instrux->TupleType)
{
case ND_TUPLE_FV:
return fvszLut[Instrux->Exs.w][Instrux->Exs.bm][Instrux->Exs.l];
return fvszLut[Instrux->Exs.l];
case ND_TUPLE_HV:
return hvszLut[Instrux->Exs.bm][Instrux->Exs.l];
return hvszLut[Instrux->Exs.l];
case ND_TUPLE_QV:
return qvszLut[Instrux->Exs.l];
case ND_TUPLE_DUP:
return dupszLut[Instrux->Exs.l];
case ND_TUPLE_FVM:
@ -1601,7 +1608,8 @@ NdParseOperand(
case ND_OPS_pd:
case ND_OPS_ps:
// packed double or packed single precision values.
case ND_OPS_ph:
// packed double or packed single or packed FP16 values.
{
static const uint8_t szLut[3] = { ND_SIZE_128BIT, ND_SIZE_256BIT, ND_SIZE_512BIT };
@ -1609,14 +1617,19 @@ NdParseOperand(
}
break;
case ND_OPS_sd:
// Scalar double.
size = ND_SIZE_64BIT;
break;
case ND_OPS_ss:
// Scalar single.
size = ND_SIZE_32BIT;
break;
case ND_OPS_sd:
// Scalar double.
size = ND_SIZE_64BIT;
case ND_OPS_sh:
// Scalar FP16.
size = ND_SIZE_16BIT;
break;
case ND_OPS_mib:
@ -2315,11 +2328,6 @@ NdParseOperand(
case ND_OPT_G:
// General purpose register encoded in modrm.reg.
if (Instrux->Exs.rp == 1)
{
return ND_STATUS_INVALID_ENCODING;
}
operand->Type = ND_OP_REG;
operand->Info.Register.Type = ND_REG_GPR;
operand->Info.Register.Size = (ND_REG_SIZE)size;
@ -2712,48 +2720,47 @@ memory:
// sibmem requires SIB to be present.
if (!Instrux->HasSib)
{
return ND_STATUS_INVALID_ENCODING;
return ND_STATUS_SIBMEM_WITHOUT_SIB;
}
operand->Info.Memory.IsSibMem = true;
}
if (Instrux->HasEvex)
// If we have broadcast, the operand size is fixed to either 16, 32 or 64 bit, depending on bcast size.
// Therefore, we will override the rawSize with either 16, 32 or 64 bits. Note that bcstSize will save the
// total size of the access, and it will be used to compute the number of broadcasted elements:
// bcstSize / rawSize.
if (Instrux->HasBroadcast)
{
// Handle compressed displacement, if any. Note that most EVEX instructions with 8 bit displacement
// use compressed displacement addressing.
if ((Instrux->HasDisp) && (ND_SIZE_8BIT == Instrux->DispLength))
{
Instrux->HasCompDisp = true;
operand->Info.Memory.HasBroadcast = true;
operand->Info.Memory.HasCompDisp = true;
operand->Info.Memory.CompDispSize = NdGetCompDispSize(Instrux, operand->Size);
if (opd & ND_OPD_B32)
{
size = ND_SIZE_32BIT;
}
else if (opd & ND_OPD_B64)
{
size = ND_SIZE_64BIT;
}
else if (opd & ND_OPD_B16)
{
size = ND_SIZE_16BIT;
}
else
{
size = width ? ND_SIZE_64BIT : ND_SIZE_32BIT;
}
// If we have broadcast, the operand size is fixed to either 32 bit, either 64 bit, depending on bcast size.
// Therefore, we will override the rawSize with either 32 or 64 bits. Note that bcstSize will save the total
// size of the access, and it will be used to compute the number of broadcasted elements: bcstSize / rawSize.
if ((Instrux->Exs.bm) && (opd & (ND_OPD_B32 | ND_OPD_B64)))
{
Instrux->HasBroadcast = true;
operand->Info.Memory.HasBroadcast = true;
// Override operand size.
operand->Size = operand->RawSize = size;
}
if (opd & ND_OPD_B32)
{
size = ND_SIZE_32BIT;
}
else if (opd & ND_OPD_B64)
{
size = ND_SIZE_64BIT;
}
else
{
size = width ? ND_SIZE_64BIT : ND_SIZE_32BIT;
}
// Override operand size.
operand->Size = operand->RawSize = size;
}
// Handle compressed displacement, if any. Note that most EVEX instructions with 8 bit displacement
// use compressed displacement addressing.
if (Instrux->HasCompDisp)
{
operand->Info.Memory.HasCompDisp = true;
operand->Info.Memory.CompDispSize = NdGetCompDispSize(Instrux, operand->Size);
}
// MIB, if any. Used by some MPX instructions.
@ -3122,23 +3129,26 @@ memory:
{
// Check for mask register. Mask if present only if the operand supports masking and if the
// mask register is not k0 (which implies "no masking").
if ((opd & ND_OPD_MASK) && (Instrux->Exs.k != 0))
if ((opd & ND_OPD_MASK) && (Instrux->HasMask))
{
operand->Decorator.HasMask = true;
operand->Decorator.Mask.Msk = (uint8_t)Instrux->Exs.k;
Instrux->HasMask = true;
}
// Check for zeroing. The operand must support zeroing and the z bit inside vex3 must be set. Note that
// Check for zeroing. The operand must support zeroing and the z bit inside evex3 must be set. Note that
// zeroing is allowed only for register destinations, and NOT for memory.
if ((opd & ND_OPD_Z) && (Instrux->Exs.z) && (operand->Type != ND_OP_MEM))
if ((opd & ND_OPD_Z) && (Instrux->HasZero))
{
if (operand->Type == ND_OP_MEM)
{
return ND_STATUS_ZEROING_ON_MEMORY;
}
operand->Decorator.HasZero = true;
Instrux->HasZero = true;
}
// Check for broadcast again. We've already filled the broadcast size before parsing the op size.
if (((opd & ND_OPD_B32) || (opd & ND_OPD_B64)) && (Instrux->Exs.bm) && (Instrux->ModRm.mod != 3))
if ((opd & ND_OPD_BCAST) && (Instrux->HasBroadcast))
{
operand->Decorator.HasBroadcast = true;
operand->Decorator.Broadcast.Size = (uint8_t)operand->Size;
@ -3554,6 +3564,10 @@ NdFindInstruction(
pTable = (const ND_TABLE *)pTable->Table[Instrux->Exs.w];
break;
case ND_ILUT_VEX_WI:
pTable = (const ND_TABLE *)pTable->Table[Instrux->DefCode == ND_CODE_64 ? Instrux->Exs.w : 0];
break;
default:
status = ND_STATUS_INTERNAL_ERROR;
stop = true;
@ -3637,11 +3651,13 @@ NdGetVectorLength(
INSTRUX *Instrux
)
{
if (Instrux->HasEvex && Instrux->Exs.bm && (Instrux->ModRm.mod == 3) &&
(ND_ER_SUPPORT(Instrux) || ND_SAE_SUPPORT(Instrux) || !!(Instrux->Attributes & ND_FLAG_IER)))
if (Instrux->HasEr || Instrux->HasSae || Instrux->HasIgnEr)
{
// Embedded rounding present, force the vector length to 512.
if ((Instrux->TupleType == ND_TUPLE_T1S) || (Instrux->TupleType == ND_TUPLE_T1F))
// Embedded rounding or SAE present, force the vector length to 512 or scalar.
if ((Instrux->TupleType == ND_TUPLE_T1S) ||
(Instrux->TupleType == ND_TUPLE_T1S8) ||
(Instrux->TupleType == ND_TUPLE_T1S16) ||
(Instrux->TupleType == ND_TUPLE_T1F))
{
Instrux->VecMode = Instrux->EfVecMode = ND_VECM_128;
}
@ -3653,7 +3669,7 @@ NdGetVectorLength(
return ND_STATUS_SUCCESS;
}
// Decode VEX vector length. Also take into consideration the "ignore L" flag.
// Decode EVEX vector length. Also take into consideration the "ignore L" flag.
switch (Instrux->Exs.l)
{
case 0:
@ -3669,7 +3685,13 @@ NdGetVectorLength(
Instrux->EfVecMode = (Instrux->Attributes & ND_FLAG_LIG) ? ND_VECM_128 : ND_VECM_512;
break;
default:
return ND_STATUS_INVALID_INSTRUX;
return ND_STATUS_BAD_EVEX_LL;
}
// Some instructions don't support 128 bit vectors.
if ((ND_VECM_128 == Instrux->EfVecMode) && (0 != (Instrux->Attributes & ND_FLAG_NOL0)))
{
return ND_STATUS_INVALID_ENCODING;
}
return ND_STATUS_SUCCESS;
@ -3718,6 +3740,12 @@ NdGetEffectiveOpMode(
static const uint8_t szLut[3] = { ND_SIZE_16BIT, ND_SIZE_32BIT, ND_SIZE_64BIT };
bool width, f64, d64, has66;
if ((ND_CODE_64 != Instrux->DefCode) && !!(Instrux->Attributes & ND_FLAG_IWO64))
{
// Some instructions ignore VEX/EVEX.W field outside 64 bit mode, and treat it as 0.
Instrux->Exs.w = 0;
}
// Extract the flags.
width = (0 != Instrux->Exs.w) && !(Instrux->Attributes & ND_FLAG_WIG);
// In 64 bit mode, the operand is forced to 64 bit. Size-changing prefixes are ignored.
@ -3755,6 +3783,108 @@ NdGetEffectiveOpMode(
}
//
// NdPostProcessEvex
//
static NDSTATUS
NdPostProcessEvex(
INSTRUX *Instrux
)
{
// Handle embedded broadcast/rounding-control.
if (Instrux->Exs.bm == 1)
{
if (Instrux->ModRm.mod == 3)
{
// reg form for the instruction, check for ER or SAE support.
if (Instrux->ValidDecorators.Er)
{
Instrux->HasEr = 1;
Instrux->HasSae = 1;
Instrux->RoundingMode = (uint8_t)Instrux->Exs.l;
}
else if (Instrux->ValidDecorators.Sae)
{
Instrux->HasSae = 1;
}
else if (!!(Instrux->Attributes & ND_FLAG_IER))
{
// The encoding behaves as if embedded rounding is enabled, but it is in fact ignored.
Instrux->HasIgnEr = 1;
}
else
{
return ND_STATUS_ER_SAE_NOT_SUPPORTED;
}
}
else
{
// mem form for the instruction, check for broadcast.
if (Instrux->ValidDecorators.Broadcast)
{
Instrux->HasBroadcast = 1;
}
else
{
return ND_STATUS_BROADCAST_NOT_SUPPORTED;
}
}
}
// Handle masking.
if (Instrux->Exs.k != 0)
{
if (Instrux->ValidDecorators.Mask)
{
Instrux->HasMask = 1;
}
else
{
return ND_STATUS_MASK_NOT_SUPPORTED;
}
}
else
{
if (!!(Instrux->Attributes & ND_FLAG_MMASK))
{
return ND_STATUS_MASK_REQUIRED;
}
}
// Handle zeroing.
if (Instrux->Exs.z != 0)
{
if (Instrux->ValidDecorators.Zero)
{
// Zeroing restrictions:
// - valid with register only;
// - valid only if masking is also used;
if (Instrux->HasMask)
{
Instrux->HasZero = 1;
}
else
{
return ND_STATUS_ZEROING_NO_MASK;
}
}
else
{
return ND_STATUS_ZEROING_NOT_SUPPORTED;
}
}
// EVEX instructions with 8 bit displacement use compressed displacement addressing, where the displacement
// is scaled according to the data type accessed by the instruction.
if (Instrux->HasDisp && Instrux->DispLength == 1)
{
Instrux->HasCompDisp = true;
}
return ND_STATUS_SUCCESS;
}
//
// NdValidateInstruction
//
@ -3797,12 +3927,6 @@ NdValidateInstruction(
return ND_STATUS_BAD_EVEX_V_PRIME;
}
// Some instructions don't support 128 bit vectors.
if ((ND_VECM_128 == Instrux->EfVecMode) && (0 != (Instrux->Attributes & ND_FLAG_NOL0)))
{
return ND_STATUS_INVALID_ENCODING;
}
// VSIB instructions have a restriction: the same vector register can't be used by more than one operand.
// The exception is SCATTER*, which can use the VSIB reg as two sources.
if (ND_HAS_VSIB(Instrux) && Instrux->Category != ND_CAT_SCATTER)
@ -3839,7 +3963,7 @@ NdValidateInstruction(
Instrux->Operands[0].Info.Register.Reg == Instrux->Operands[2].Info.Register.Reg ||
Instrux->Operands[1].Info.Register.Reg == Instrux->Operands[2].Info.Register.Reg)
{
return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION;
return ND_STATUS_INVALID_TILE_REGS;
}
}
else
@ -3852,50 +3976,29 @@ NdValidateInstruction(
}
}
if (Instrux->HasEvex)
// Handle EVEX exception class.
if (Instrux->ExceptionClass == ND_EXC_EVEX)
{
// Instructions that don't support masking must have EVEX.aaa = 0.
if (!ND_MASK_SUPPORT(Instrux) && (0 != Instrux->Exs.k))
// If E4* or E10* exception class is used (check out AVX512-FP16 instructions), an additional #UD case
// exists: if the destination register is equal to either of the source registers.
if (Instrux->ExceptionType == ND_EXT_E4S || Instrux->ExceptionType == ND_EXT_E10S)
{
return ND_STATUS_MASK_NOT_SUPPORTED;
}
// Note that operand 0 is the destination, operand 1 is the mask, operand 2 is first source, operand
// 3 is the second source.
// Some instructions have mandatory masking, and using k0 as a mask triggers #UD.
if ((Instrux->Attributes & ND_FLAG_MMASK) && (0 == Instrux->Exs.k))
{
return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION;
}
// EVEX.z must be 0 if:
// - zeroing is not supported by the instruction.
// - zeroing is supported, but the destination is memory.
// If zeroing is supported and the mask is 0, then zeroing is ignored.
if (0 != Instrux->Exs.z)
{
if (!ND_ZERO_SUPPORT(Instrux))
if (Instrux->Operands[0].Type == ND_OP_REG && Instrux->Operands[2].Type == ND_OP_REG &&
Instrux->Operands[0].Info.Register.Reg == Instrux->Operands[2].Info.Register.Reg)
{
return ND_STATUS_ZEROING_NOT_SUPPORTED;
return ND_STATUS_INVALID_DEST_REGS;
}
if (Instrux->Operands[0].Type == ND_OP_MEM)
if (Instrux->Operands[0].Type == ND_OP_REG && Instrux->Operands[3].Type == ND_OP_REG &&
Instrux->Operands[0].Info.Register.Reg == Instrux->Operands[3].Info.Register.Reg)
{
return ND_STATUS_ZEROING_ON_MEMORY;
return ND_STATUS_INVALID_DEST_REGS;
}
}
// EVEX.b must be 0 if SAE/ER is not used, but can be ignored if the ignore embedded rounding flag is set.
if (Instrux->Exs.bm && (Instrux->ModRm.mod == 3) &&
!ND_SAE_SUPPORT(Instrux) && !ND_ER_SUPPORT(Instrux) &&
!(Instrux->Attributes & ND_FLAG_IER))
{
return ND_STATUS_ER_SAE_NOT_SUPPORTED;
}
// EVEX.b must be 0 if broadcast is not supported.
if (Instrux->Exs.bm && (Instrux->ModRm.mod != 3) && !ND_BROADCAST_SUPPORT(Instrux))
{
return ND_STATUS_BROADCAST_NOT_SUPPORTED;
}
}
}
@ -4062,6 +4165,18 @@ NdDecodeWithContext(
return status;
}
if (Instrux->HasEvex)
{
// Post-process EVEX encoded instructions. This does two thing:
// - check and fill in decorator info;
// - generate error for invalid broadcast/rounding, mask or zeroing bits.
status = NdPostProcessEvex(Instrux);
if (!ND_SUCCESS(status))
{
return status;
}
}
if (ND_HAS_VECTOR(Instrux))
{
// Get vector length.
@ -4084,24 +4199,6 @@ NdDecodeWithContext(
Instrux->Condition = Instrux->Predicate = Instrux->PrimaryOpCode & 0xF;
}
if (0 != pIns->ValidDecorators)
{
// Check for suppress all exceptions.
if ((Instrux->ValidDecorators.Sae) && (Instrux->Exs.bm) && (Instrux->ModRm.mod == 3))
{
Instrux->HasSae = true;
}
// Check for embedded rounding. This is available only in reg-reg encodings. Also, if embedded
// rounding is used, the vector length is forced to 512 bit, as the
if ((Instrux->ValidDecorators.Er) && (Instrux->Exs.bm) && (Instrux->ModRm.mod == 3))
{
Instrux->HasEr = true;
Instrux->HasSae = true;
Instrux->RoundingMode = (uint8_t)Instrux->Exs.l;
}
}
Instrux->ExpOperandsCount = ND_EXP_OPS_CNT(pIns->OpsCount);
Instrux->OperandsCount = Instrux->ExpOperandsCount + ND_IMP_OPS_CNT(pIns->OpsCount);

7091
bddisasm/include/instructions.h
View File

File diff suppressed because it is too large Load Diff

219
bddisasm/include/mnemonics.h
View File

@ -1,7 +1,7 @@
#ifndef MNEMONICS_H
#define MNEMONICS_H
const char *gMnemonics[1589] =
const char *gMnemonics[1695] =
{
"AAA", "AAD", "AAM", "AAS", "ADC", "ADCX", "ADD", "ADDPD", "ADDPS",
"ADDSD", "ADDSS", "ADDSUBPD", "ADDSUBPS", "ADOX", "AESDEC", "AESDEC128KL",
@ -126,87 +126,105 @@ const char *gMnemonics[1589] =
"TILEZERO", "TLBSYNC", "TPAUSE", "TZCNT", "TZMSK", "UCOMISD",
"UCOMISS", "UD0", "UD1", "UD2", "UIRET", "UMONITOR", "UMWAIT",
"UNPCKHPD", "UNPCKHPS", "UNPCKLPD", "UNPCKLPS", "V4FMADDPS",
"V4FMADDSS", "V4FNMADDPS", "V4FNMADDSS", "VADDPD", "VADDPS",
"VADDSD", "VADDSS", "VADDSUBPD", "VADDSUBPS", "VAESDEC", "VAESDECLAST",
"VAESENC", "VAESENCLAST", "VAESIMC", "VAESKEYGENASSIST", "VALIGND",
"VALIGNQ", "VANDNPD", "VANDNPS", "VANDPD", "VANDPS", "VBLENDMPD",
"VBLENDMPS", "VBLENDPD", "VBLENDPS", "VBLENDVPD", "VBLENDVPS",
"VBROADCASTF128", "VBROADCASTF32X2", "VBROADCASTF32X4", "VBROADCASTF32X8",
"VBROADCASTF64X2", "VBROADCASTF64X4", "VBROADCASTI128", "VBROADCASTI32X2",
"VBROADCASTI32X4", "VBROADCASTI32X8", "VBROADCASTI64X2", "VBROADCASTI64X4",
"VBROADCASTSD", "VBROADCASTSS", "VCMPPD", "VCMPPS", "VCMPSD",
"VCMPSS", "VCOMISD", "VCOMISS", "VCOMPRESSPD", "VCOMPRESSPS",
"VCVTDQ2PD", "VCVTDQ2PS", "VCVTNE2PS2BF16", "VCVTNEPS2BF16",
"VCVTPD2DQ", "VCVTPD2PS", "VCVTPD2QQ", "VCVTPD2UDQ", "VCVTPD2UQQ",
"VCVTPH2PS", "VCVTPS2DQ", "VCVTPS2PD", "VCVTPS2PH", "VCVTPS2QQ",
"VCVTPS2UDQ", "VCVTPS2UQQ", "VCVTQQ2PD", "VCVTQQ2PS", "VCVTSD2SI",
"VCVTSD2SS", "VCVTSD2USI", "VCVTSI2SD", "VCVTSI2SS", "VCVTSS2SD",
"VCVTSS2SI", "VCVTSS2USI", "VCVTTPD2DQ", "VCVTTPD2QQ", "VCVTTPD2UDQ",
"VCVTTPD2UQQ", "VCVTTPS2DQ", "VCVTTPS2QQ", "VCVTTPS2UDQ", "VCVTTPS2UQQ",
"VCVTTSD2SI", "VCVTTSD2USI", "VCVTTSS2SI", "VCVTTSS2USI", "VCVTUDQ2PD",
"VCVTUDQ2PS", "VCVTUQQ2PD", "VCVTUQQ2PS", "VCVTUSI2SD", "VCVTUSI2SS",
"VDBPSADBW", "VDIVPD", "VDIVPS", "VDIVSD", "VDIVSS", "VDPBF16PS",
"VDPPD", "VDPPS", "VERR", "VERW", "VEXP2PD", "VEXP2PS", "VEXPANDPD",
"VEXPANDPS", "VEXTRACTF128", "VEXTRACTF32X4", "VEXTRACTF32X8",
"VEXTRACTF64X2", "VEXTRACTF64X4", "VEXTRACTI128", "VEXTRACTI32X4",
"VEXTRACTI32X8", "VEXTRACTI64X2", "VEXTRACTI64X4", "VEXTRACTPS",
"VFIXUPIMMPD", "VFIXUPIMMPS", "VFIXUPIMMSD", "VFIXUPIMMSS", "VFMADD132PD",
"VFMADD132PS", "VFMADD132SD", "VFMADD132SS", "VFMADD213PD", "VFMADD213PS",
"VFMADD213SD", "VFMADD213SS", "VFMADD231PD", "VFMADD231PS", "VFMADD231SD",
"VFMADD231SS", "VFMADDPD", "VFMADDPS", "VFMADDSD", "VFMADDSS",
"VFMADDSUB132PD", "VFMADDSUB132PS", "VFMADDSUB213PD", "VFMADDSUB213PS",
"VFMADDSUB231PD", "VFMADDSUB231PS", "VFMADDSUBPD", "VFMADDSUBPS",
"VFMSUB132PD", "VFMSUB132PS", "VFMSUB132SD", "VFMSUB132SS", "VFMSUB213PD",
"VFMSUB213PS", "VFMSUB213SD", "VFMSUB213SS", "VFMSUB231PD", "VFMSUB231PS",
"VFMSUB231SD", "VFMSUB231SS", "VFMSUBADD132PD", "VFMSUBADD132PS",
"VFMSUBADD213PD", "VFMSUBADD213PS", "VFMSUBADD231PD", "VFMSUBADD231PS",
"VFMSUBADDPD", "VFMSUBADDPS", "VFMSUBPD", "VFMSUBPS", "VFMSUBSD",
"VFMSUBSS", "VFNMADD132PD", "VFNMADD132PS", "VFNMADD132SD", "VFNMADD132SS",
"VFNMADD213PD", "VFNMADD213PS", "VFNMADD213SD", "VFNMADD213SS",
"VFNMADD231PD", "VFNMADD231PS", "VFNMADD231SD", "VFNMADD231SS",
"VFNMADDPD", "VFNMADDPS", "VFNMADDSD", "VFNMADDSS", "VFNMSUB132PD",
"VFNMSUB132PS", "VFNMSUB132SD", "VFNMSUB132SS", "VFNMSUB213PD",
"VFNMSUB213PS", "VFNMSUB213SD", "VFNMSUB213SS", "VFNMSUB231PD",
"VFNMSUB231PS", "VFNMSUB231SD", "VFNMSUB231SS", "VFNMSUBPD",
"VFNMSUBPS", "VFNMSUBSD", "VFNMSUBSS", "VFPCLASSPD", "VFPCLASSPS",
"VFPCLASSSD", "VFPCLASSSS", "VFRCZPD", "VFRCZPS", "VFRCZSD",
"V4FMADDSS", "V4FNMADDPS", "V4FNMADDSS", "VADDPD", "VADDPH",
"VADDPS", "VADDSD", "VADDSH", "VADDSS", "VADDSUBPD", "VADDSUBPS",
"VAESDEC", "VAESDECLAST", "VAESENC", "VAESENCLAST", "VAESIMC",
"VAESKEYGENASSIST", "VALIGND", "VALIGNQ", "VANDNPD", "VANDNPS",
"VANDPD", "VANDPS", "VBLENDMPD", "VBLENDMPS", "VBLENDPD", "VBLENDPS",
"VBLENDVPD", "VBLENDVPS", "VBROADCASTF128", "VBROADCASTF32X2",
"VBROADCASTF32X4", "VBROADCASTF32X8", "VBROADCASTF64X2", "VBROADCASTF64X4",
"VBROADCASTI128", "VBROADCASTI32X2", "VBROADCASTI32X4", "VBROADCASTI32X8",
"VBROADCASTI64X2", "VBROADCASTI64X4", "VBROADCASTSD", "VBROADCASTSS",
"VCMPPD", "VCMPPH", "VCMPPS", "VCMPSD", "VCMPSH", "VCMPSS", "VCOMISD",
"VCOMISH", "VCOMISS", "VCOMPRESSPD", "VCOMPRESSPS", "VCVTDQ2PD",
"VCVTDQ2PH", "VCVTDQ2PS", "VCVTNE2PS2BF16", "VCVTNEPS2BF16",
"VCVTPD2DQ", "VCVTPD2PH", "VCVTPD2PS", "VCVTPD2QQ", "VCVTPD2UDQ",
"VCVTPD2UQQ", "VCVTPH2DQ", "VCVTPH2PD", "VCVTPH2PS", "VCVTPH2PSX",
"VCVTPH2QQ", "VCVTPH2UDQ", "VCVTPH2UQQ", "VCVTPH2UW", "VCVTPH2W",
"VCVTPS2DQ", "VCVTPS2PD", "VCVTPS2PH", "VCVTPS2PHX", "VCVTPS2QQ",
"VCVTPS2UDQ", "VCVTPS2UQQ", "VCVTQQ2PD", "VCVTQQ2PH", "VCVTQQ2PS",
"VCVTSD2SH", "VCVTSD2SI", "VCVTSD2SS", "VCVTSD2USI", "VCVTSH2SD",
"VCVTSH2SI", "VCVTSH2SS", "VCVTSH2USI", "VCVTSI2SD", "VCVTSI2SH",
"VCVTSI2SS", "VCVTSS2SD", "VCVTSS2SH", "VCVTSS2SI", "VCVTSS2USI",
"VCVTTPD2DQ", "VCVTTPD2QQ", "VCVTTPD2UDQ", "VCVTTPD2UQQ", "VCVTTPH2DQ",
"VCVTTPH2QQ", "VCVTTPH2UDQ", "VCVTTPH2UQQ", "VCVTTPH2UW", "VCVTTPH2W",
"VCVTTPS2DQ", "VCVTTPS2QQ", "VCVTTPS2UDQ", "VCVTTPS2UQQ", "VCVTTSD2SI",
"VCVTTSD2USI", "VCVTTSH2SI", "VCVTTSH2USI", "VCVTTSS2SI", "VCVTTSS2USI",
"VCVTUDQ2PD", "VCVTUDQ2PH", "VCVTUDQ2PS", "VCVTUQQ2PD", "VCVTUQQ2PH",
"VCVTUQQ2PS", "VCVTUSI2SD", "VCVTUSI2SH", "VCVTUSI2SS", "VCVTUW2PH",
"VCVTW2PH", "VDBPSADBW", "VDIVPD", "VDIVPH", "VDIVPS", "VDIVSD",
"VDIVSH", "VDIVSS", "VDPBF16PS", "VDPPD", "VDPPS", "VERR", "VERW",
"VEXP2PD", "VEXP2PS", "VEXPANDPD", "VEXPANDPS", "VEXTRACTF128",
"VEXTRACTF32X4", "VEXTRACTF32X8", "VEXTRACTF64X2", "VEXTRACTF64X4",
"VEXTRACTI128", "VEXTRACTI32X4", "VEXTRACTI32X8", "VEXTRACTI64X2",
"VEXTRACTI64X4", "VEXTRACTPS", "VFCMADDCPH", "VFCMADDCSH", "VFCMULCPH",
"VFCMULCSH", "VFIXUPIMMPD", "VFIXUPIMMPS", "VFIXUPIMMSD", "VFIXUPIMMSS",
"VFMADD132PD", "VFMADD132PH", "VFMADD132PS", "VFMADD132SD", "VFMADD132SH",
"VFMADD132SS", "VFMADD213PD", "VFMADD213PH", "VFMADD213PS", "VFMADD213SD",
"VFMADD213SH", "VFMADD213SS", "VFMADD231PD", "VFMADD231PH", "VFMADD231PS",
"VFMADD231SD", "VFMADD231SH", "VFMADD231SS", "VFMADDCPH", "VFMADDCSH",
"VFMADDPD", "VFMADDPS", "VFMADDSD", "VFMADDSS", "VFMADDSUB132PD",
"VFMADDSUB132PH", "VFMADDSUB132PS", "VFMADDSUB213PD", "VFMADDSUB213PH",
"VFMADDSUB213PS", "VFMADDSUB231PD", "VFMADDSUB231PH", "VFMADDSUB231PS",
"VFMADDSUBPD", "VFMADDSUBPS", "VFMSUB132PD", "VFMSUB132PH", "VFMSUB132PS",
"VFMSUB132SD", "VFMSUB132SH", "VFMSUB132SS", "VFMSUB213PD", "VFMSUB213PH",
"VFMSUB213PS", "VFMSUB213SD", "VFMSUB213SH", "VFMSUB213SS", "VFMSUB231PD",
"VFMSUB231PH", "VFMSUB231PS", "VFMSUB231SD", "VFMSUB231SH", "VFMSUB231SS",
"VFMSUBADD132PD", "VFMSUBADD132PH", "VFMSUBADD132PS", "VFMSUBADD213PD",
"VFMSUBADD213PH", "VFMSUBADD213PS", "VFMSUBADD231PD", "VFMSUBADD231PH",
"VFMSUBADD231PS", "VFMSUBADDPD", "VFMSUBADDPS", "VFMSUBPD", "VFMSUBPS",
"VFMSUBSD", "VFMSUBSS", "VFMULCPH", "VFMULCSH", "VFNMADD132PD",
"VFNMADD132PH", "VFNMADD132PS", "VFNMADD132SD", "VFNMADD132SH",
"VFNMADD132SS", "VFNMADD213PD", "VFNMADD213PH", "VFNMADD213PS",
"VFNMADD213SD", "VFNMADD213SH", "VFNMADD213SS", "VFNMADD231PD",
"VFNMADD231PH", "VFNMADD231PS", "VFNMADD231SD", "VFNMADD231SH",
"VFNMADD231SS", "VFNMADDPD", "VFNMADDPS", "VFNMADDSD", "VFNMADDSS",
"VFNMSUB132PD", "VFNMSUB132PH", "VFNMSUB132PS", "VFNMSUB132SD",
"VFNMSUB132SH", "VFNMSUB132SS", "VFNMSUB213PD", "VFNMSUB213PH",
"VFNMSUB213PS", "VFNMSUB213SD", "VFNMSUB213SH", "VFNMSUB213SS",
"VFNMSUB231PD", "VFNMSUB231PH", "VFNMSUB231PS", "VFNMSUB231SD",
"VFNMSUB231SH", "VFNMSUB231SS", "VFNMSUBPD", "VFNMSUBPS", "VFNMSUBSD",
"VFNMSUBSS", "VFPCLASSPD", "VFPCLASSPH", "VFPCLASSPS", "VFPCLASSSD",
"VFPCLASSSH", "VFPCLASSSS", "VFRCZPD", "VFRCZPS", "VFRCZSD",
"VFRCZSS", "VGATHERDPD", "VGATHERDPS", "VGATHERPF0DPD", "VGATHERPF0DPS",
"VGATHERPF0QPD", "VGATHERPF0QPS", "VGATHERPF1DPD", "VGATHERPF1DPS",
"VGATHERPF1QPD", "VGATHERPF1QPS", "VGATHERQPD", "VGATHERQPS",
"VGETEXPPD", "VGETEXPPS", "VGETEXPSD", "VGETEXPSS", "VGETMANTPD",
"VGETMANTPS", "VGETMANTSD", "VGETMANTSS", "VGF2P8AFFINEINVQB",
"VGF2P8AFFINEQB", "VGF2P8MULB", "VHADDPD", "VHADDPS", "VHSUBPD",
"VHSUBPS", "VINSERTF128", "VINSERTF32X4", "VINSERTF32X8", "VINSERTF64X2",
"VINSERTF64X4", "VINSERTI128", "VINSERTI32X4", "VINSERTI32X8",
"VINSERTI64X2", "VINSERTI64X4", "VINSERTPS", "VLDDQU", "VLDMXCSR",
"VMASKMOVDQU", "VMASKMOVPD", "VMASKMOVPS", "VMAXPD", "VMAXPS",
"VMAXSD", "VMAXSS", "VMCALL", "VMCLEAR", "VMFUNC", "VMGEXIT",
"VMINPD", "VMINPS", "VMINSD", "VMINSS", "VMLAUNCH", "VMLOAD",
"VMMCALL", "VMOVAPD", "VMOVAPS", "VMOVD", "VMOVDDUP", "VMOVDQA",
"VMOVDQA32", "VMOVDQA64", "VMOVDQU", "VMOVDQU16", "VMOVDQU32",
"VMOVDQU64", "VMOVDQU8", "VMOVHLPS", "VMOVHPD", "VMOVHPS", "VMOVLHPS",
"VMOVLPD", "VMOVLPS", "VMOVMSKPD", "VMOVMSKPS", "VMOVNTDQ", "VMOVNTDQA",
"VMOVNTPD", "VMOVNTPS", "VMOVQ", "VMOVSD", "VMOVSHDUP", "VMOVSLDUP",
"VMOVSS", "VMOVUPD", "VMOVUPS", "VMPSADBW", "VMPTRLD", "VMPTRST",
"VMREAD", "VMRESUME", "VMRUN", "VMSAVE", "VMULPD", "VMULPS",
"VMULSD", "VMULSS", "VMWRITE", "VMXOFF", "VMXON", "VORPD", "VORPS",
"VP2INTERSECTD", "VP2INTERSECTQ", "VP4DPWSSD", "VP4DPWSSDS",
"VPABSB", "VPABSD", "VPABSQ", "VPABSW", "VPACKSSDW", "VPACKSSWB",
"VPACKUSDW", "VPACKUSWB", "VPADDB", "VPADDD", "VPADDQ", "VPADDSB",
"VPADDSW", "VPADDUSB", "VPADDUSW", "VPADDW", "VPALIGNR", "VPAND",
"VPANDD", "VPANDN", "VPANDND", "VPANDNQ", "VPANDQ", "VPAVGB",
"VPAVGW", "VPBLENDD", "VPBLENDMB", "VPBLENDMD", "VPBLENDMQ",
"VPBLENDMW", "VPBLENDVB", "VPBLENDW", "VPBROADCASTB", "VPBROADCASTD",
"VPBROADCASTMB2Q", "VPBROADCASTMW2D", "VPBROADCASTQ", "VPBROADCASTW",
"VPCLMULQDQ", "VPCMOV", "VPCMPB", "VPCMPD", "VPCMPEQB", "VPCMPEQD",
"VPCMPEQQ", "VPCMPEQW", "VPCMPESTRI", "VPCMPESTRM", "VPCMPGTB",
"VPCMPGTD", "VPCMPGTQ", "VPCMPGTW", "VPCMPISTRI", "VPCMPISTRM",
"VPCMPQ", "VPCMPUB", "VPCMPUD", "VPCMPUQ", "VPCMPUW", "VPCMPW",
"VPCOMB", "VPCOMD", "VPCOMPRESSB", "VPCOMPRESSD", "VPCOMPRESSQ",
"VPCOMPRESSW", "VPCOMQ", "VPCOMUB", "VPCOMUD", "VPCOMUQ", "VPCOMUW",
"VPCOMW", "VPCONFLICTD", "VPCONFLICTQ", "VPDPBUSD", "VPDPBUSDS",
"VPDPWSSD", "VPDPWSSDS", "VPERM2F128", "VPERM2I128", "VPERMB",
"VPERMD", "VPERMI2B", "VPERMI2D", "VPERMI2PD", "VPERMI2PS", "VPERMI2Q",
"VGETEXPPD", "VGETEXPPH", "VGETEXPPS", "VGETEXPSD", "VGETEXPSH",
"VGETEXPSS", "VGETMANTPD", "VGETMANTPH", "VGETMANTPS", "VGETMANTSD",
"VGETMANTSH", "VGETMANTSS", "VGF2P8AFFINEINVQB", "VGF2P8AFFINEQB",
"VGF2P8MULB", "VHADDPD", "VHADDPS", "VHSUBPD", "VHSUBPS", "VINSERTF128",
"VINSERTF32X4", "VINSERTF32X8", "VINSERTF64X2", "VINSERTF64X4",
"VINSERTI128", "VINSERTI32X4", "VINSERTI32X8", "VINSERTI64X2",
"VINSERTI64X4", "VINSERTPS", "VLDDQU", "VLDMXCSR", "VMASKMOVDQU",
"VMASKMOVPD", "VMASKMOVPS", "VMAXPD", "VMAXPH", "VMAXPS", "VMAXSD",
"VMAXSH", "VMAXSS", "VMCALL", "VMCLEAR", "VMFUNC", "VMGEXIT",
"VMINPD", "VMINPH", "VMINPS", "VMINSD", "VMINSH", "VMINSS", "VMLAUNCH",
"VMLOAD", "VMMCALL", "VMOVAPD", "VMOVAPS", "VMOVD", "VMOVDDUP",
"VMOVDQA", "VMOVDQA32", "VMOVDQA64", "VMOVDQU", "VMOVDQU16",
"VMOVDQU32", "VMOVDQU64", "VMOVDQU8", "VMOVHLPS", "VMOVHPD",
"VMOVHPS", "VMOVLHPS", "VMOVLPD", "VMOVLPS", "VMOVMSKPD", "VMOVMSKPS",
"VMOVNTDQ", "VMOVNTDQA", "VMOVNTPD", "VMOVNTPS", "VMOVQ", "VMOVSD",
"VMOVSH", "VMOVSHDUP", "VMOVSLDUP", "VMOVSS", "VMOVUPD", "VMOVUPS",
"VMOVW", "VMPSADBW", "VMPTRLD", "VMPTRST", "VMREAD", "VMRESUME",
"VMRUN", "VMSAVE", "VMULPD", "VMULPH", "VMULPS", "VMULSD", "VMULSH",
"VMULSS", "VMWRITE", "VMXOFF", "VMXON", "VORPD", "VORPS", "VP2INTERSECTD",
"VP2INTERSECTQ", "VP4DPWSSD", "VP4DPWSSDS", "VPABSB", "VPABSD",
"VPABSQ", "VPABSW", "VPACKSSDW", "VPACKSSWB", "VPACKUSDW", "VPACKUSWB",
"VPADDB", "VPADDD", "VPADDQ", "VPADDSB", "VPADDSW", "VPADDUSB",
"VPADDUSW", "VPADDW", "VPALIGNR", "VPAND", "VPANDD", "VPANDN",
"VPANDND", "VPANDNQ", "VPANDQ", "VPAVGB", "VPAVGW", "VPBLENDD",
"VPBLENDMB", "VPBLENDMD", "VPBLENDMQ", "VPBLENDMW", "VPBLENDVB",
"VPBLENDW", "VPBROADCASTB", "VPBROADCASTD", "VPBROADCASTMB2Q",
"VPBROADCASTMW2D", "VPBROADCASTQ", "VPBROADCASTW", "VPCLMULQDQ",
"VPCMOV", "VPCMPB", "VPCMPD", "VPCMPEQB", "VPCMPEQD", "VPCMPEQQ",
"VPCMPEQW", "VPCMPESTRI", "VPCMPESTRM", "VPCMPGTB", "VPCMPGTD",
"VPCMPGTQ", "VPCMPGTW", "VPCMPISTRI", "VPCMPISTRM", "VPCMPQ",
"VPCMPUB", "VPCMPUD", "VPCMPUQ", "VPCMPUW", "VPCMPW", "VPCOMB",
"VPCOMD", "VPCOMPRESSB", "VPCOMPRESSD", "VPCOMPRESSQ", "VPCOMPRESSW",
"VPCOMQ", "VPCOMUB", "VPCOMUD", "VPCOMUQ", "VPCOMUW", "VPCOMW",
"VPCONFLICTD", "VPCONFLICTQ", "VPDPBUSD", "VPDPBUSDS", "VPDPWSSD",
"VPDPWSSDS", "VPERM2F128", "VPERM2I128", "VPERMB", "VPERMD",
"VPERMI2B", "VPERMI2D", "VPERMI2PD", "VPERMI2PS", "VPERMI2Q",
"VPERMI2W", "VPERMIL2PD", "VPERMIL2PS", "VPERMILPD", "VPERMILPS",
"VPERMPD", "VPERMPS", "VPERMQ", "VPERMT2B", "VPERMT2D", "VPERMT2PD",
"VPERMT2PS", "VPERMT2Q", "VPERMT2W", "VPERMW", "VPEXPANDB", "VPEXPANDD",
@ -251,28 +269,31 @@ const char *gMnemonics[1589] =
"VPUNPCKHQDQ", "VPUNPCKHWD", "VPUNPCKLBW", "VPUNPCKLDQ", "VPUNPCKLQDQ",
"VPUNPCKLWD", "VPXOR", "VPXORD", "VPXORQ", "VRANGEPD", "VRANGEPS",
"VRANGESD", "VRANGESS", "VRCP14PD", "VRCP14PS", "VRCP14SD", "VRCP14SS",
"VRCP28PD", "VRCP28PS", "VRCP28SD", "VRCP28SS", "VRCPPS", "VRCPSS",
"VREDUCEPD", "VREDUCEPS", "VREDUCESD", "VREDUCESS", "VRNDSCALEPD",
"VRNDSCALEPS", "VRNDSCALESD", "VRNDSCALESS", "VROUNDPD", "VROUNDPS",
"VRCP28PD", "VRCP28PS", "VRCP28SD", "VRCP28SS", "VRCPPH", "VRCPPS",
"VRCPSH", "VRCPSS", "VREDUCEPD", "VREDUCEPH", "VREDUCEPS", "VREDUCESD",
"VREDUCESH", "VREDUCESS", "VRNDSCALEPD", "VRNDSCALEPH", "VRNDSCALEPS",
"VRNDSCALESD", "VRNDSCALESH", "VRNDSCALESS", "VROUNDPD", "VROUNDPS",
"VROUNDSD", "VROUNDSS", "VRSQRT14PD", "VRSQRT14PS", "VRSQRT14SD",
"VRSQRT14SS", "VRSQRT28PD", "VRSQRT28PS", "VRSQRT28SD", "VRSQRT28SS",
"VRSQRTPS", "VRSQRTSS", "VSCALEFPD", "VSCALEFPS", "VSCALEFSD",
"VSCALEFSS", "VSCATTERDPD", "VSCATTERDPS", "VSCATTERPF0DPD",
"VSCATTERPF0DPS", "VSCATTERPF0QPD", "VSCATTERPF0QPS", "VSCATTERPF1DPD",
"VSCATTERPF1DPS", "VSCATTERPF1QPD", "VSCATTERPF1QPS", "VSCATTERQPD",
"VSCATTERQPS", "VSHUFF32X4", "VSHUFF64X2", "VSHUFI32X4", "VSHUFI64X2",
"VSHUFPD", "VSHUFPS", "VSQRTPD", "VSQRTPS", "VSQRTSD", "VSQRTSS",
"VSTMXCSR", "VSUBPD", "VSUBPS", "VSUBSD", "VSUBSS", "VTESTPD",
"VTESTPS", "VUCOMISD", "VUCOMISS", "VUNPCKHPD", "VUNPCKHPS",
"VUNPCKLPD", "VUNPCKLPS", "VXORPD", "VXORPS", "VZEROALL", "VZEROUPPER",
"WAIT", "WBINVD", "WBNOINVD", "WRFSBASE", "WRGSBASE", "WRMSR",
"WRPKRU", "WRSHR", "WRSSD", "WRSSQ", "WRUSSD", "WRUSSQ", "XABORT",
"XADD", "XBEGIN", "XCHG", "XCRYPTCBC", "XCRYPTCFB", "XCRYPTCTR",
"XCRYPTECB", "XCRYPTOFB", "XEND", "XGETBV", "XLATB", "XOR", "XORPD",
"XORPS", "XRESLDTRK", "XRSTOR", "XRSTOR64", "XRSTORS", "XRSTORS64",
"XSAVE", "XSAVE64", "XSAVEC", "XSAVEC64", "XSAVEOPT", "XSAVEOPT64",
"XSAVES", "XSAVES64", "XSETBV", "XSHA1", "XSHA256", "XSTORE",
"XSUSLDTRK", "XTEST",
"VRSQRTPH", "VRSQRTPS", "VRSQRTSH", "VRSQRTSS", "VSCALEFPD",
"VSCALEFPH", "VSCALEFPS", "VSCALEFSD", "VSCALEFSH", "VSCALEFSS",
"VSCATTERDPD", "VSCATTERDPS", "VSCATTERPF0DPD", "VSCATTERPF0DPS",
"VSCATTERPF0QPD", "VSCATTERPF0QPS", "VSCATTERPF1DPD", "VSCATTERPF1DPS",
"VSCATTERPF1QPD", "VSCATTERPF1QPS", "VSCATTERQPD", "VSCATTERQPS",
"VSHUFF32X4", "VSHUFF64X2", "VSHUFI32X4", "VSHUFI64X2", "VSHUFPD",
"VSHUFPS", "VSQRTPD", "VSQRTPH", "VSQRTPS", "VSQRTSD", "VSQRTSH",
"VSQRTSS", "VSTMXCSR", "VSUBPD", "VSUBPH", "VSUBPS", "VSUBSD",
"VSUBSH", "VSUBSS", "VTESTPD", "VTESTPS", "VUCOMISD", "VUCOMISH",
"VUCOMISS", "VUNPCKHPD", "VUNPCKHPS", "VUNPCKLPD", "VUNPCKLPS",
"VXORPD", "VXORPS", "VZEROALL", "VZEROUPPER", "WAIT", "WBINVD",
"WBNOINVD", "WRFSBASE", "WRGSBASE", "WRMSR", "WRPKRU", "WRSHR",
"WRSSD", "WRSSQ", "WRUSSD", "WRUSSQ", "XABORT", "XADD", "XBEGIN",
"XCHG", "XCRYPTCBC", "XCRYPTCFB", "XCRYPTCTR", "XCRYPTECB", "XCRYPTOFB",
"XEND", "XGETBV", "XLATB", "XOR", "XORPD", "XORPS", "XRESLDTRK",
"XRSTOR", "XRSTOR64", "XRSTORS", "XRSTORS64", "XSAVE", "XSAVE64",
"XSAVEC", "XSAVEC64", "XSAVEOPT", "XSAVEOPT64", "XSAVES", "XSAVES64",
"XSETBV", "XSHA1", "XSHA256", "XSTORE", "XSUSLDTRK", "XTEST",
};

5
bddisasm/include/nd_crt.h
View File

@ -12,8 +12,7 @@
#endif
#if defined(_MSC_VER)
typedef char * va_list;
#include <vadefs.h>
# ifndef _ADDRESSOF
# ifdef __cplusplus
@ -27,8 +26,6 @@ typedef char * va_list;
# if defined(AMD64) || defined(WIN64)
extern void __cdecl __va_start(__out va_list *, ...); // is this exported by VC compiler?
# define _crt_va_start(ap, x) ( __va_start(&ap, x) )
# define _crt_va_arg(ap, t) ( ( sizeof(t) > sizeof(QWORD) || ( sizeof(t) & (sizeof(t) - 1) ) != 0 ) \
? **(t **)( ( ap += sizeof(QWORD) ) - sizeof(QWORD) ) \

4234
bddisasm/include/table_evex.h
View File

File diff suppressed because it is too large Load Diff

178
bddisasm/include/table_root.h
View File

@ -106,7 +106,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_80_05_leaf =
const ND_TABLE_INSTRUCTION gRootTable_root_80_06_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2563]
(const void *)&gInstructions[2675]
};
const ND_TABLE_MODRM_REG gRootTable_root_80_modrmreg =
@ -169,7 +169,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_81_05_leaf =
const ND_TABLE_INSTRUCTION gRootTable_root_81_06_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2564]
(const void *)&gInstructions[2676]
};
const ND_TABLE_MODRM_REG gRootTable_root_81_modrmreg =
@ -232,7 +232,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_82_05_leaf =
const ND_TABLE_INSTRUCTION gRootTable_root_82_06_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2565]
(const void *)&gInstructions[2677]
};
const ND_TABLE_MODRM_REG gRootTable_root_82_modrmreg =
@ -295,7 +295,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_83_05_leaf =
const ND_TABLE_INSTRUCTION gRootTable_root_83_06_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2566]
(const void *)&gInstructions[2678]
};
const ND_TABLE_MODRM_REG gRootTable_root_83_modrmreg =
@ -328,13 +328,13 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f6_mem_F3_leaf =
const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f6_mem_NP_None_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2531]
(const void *)&gInstructions[2643]
};
const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f6_mem_NP_rexw_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2532]
(const void *)&gInstructions[2644]
};
const ND_TABLE_AUXILIARY gRootTable_root_0f_38_f6_mem_NP_auxiliary =
@ -2079,13 +2079,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_cb_mprefix =
const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f5_mem_66_None_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2533]
(const void *)&gInstructions[2645]
};
const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f5_mem_66_rexw_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2534]
(const void *)&gInstructions[2646]
};
const ND_TABLE_AUXILIARY gRootTable_root_0f_38_f5_mem_66_auxiliary =
@ -3969,25 +3969,25 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_04_leaf =
const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_01_F3_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[1765]
(const void *)&gInstructions[1850]
};
const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_01_F2_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[1766]
(const void *)&gInstructions[1851]
};
const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_01_None_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[1777]
(const void *)&gInstructions[1864]
};
const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_01_66_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[1778]
(const void *)&gInstructions[1865]
};
const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_03_01_mprefix =
@ -4004,19 +4004,19 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_03_01_mprefix =
const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_02_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[1776]
(const void *)&gInstructions[1863]
};
const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_00_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[1883]
(const void *)&gInstructions[1978]
};
const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_03_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[1884]
(const void *)&gInstructions[1979]
};
const ND_TABLE_MODRM_RM gRootTable_root_0f_01_reg_03_modrmrm =
@ -4089,7 +4089,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_00_F3_leaf =
const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_00_F2_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2587]
(const void *)&gInstructions[2699]
};
const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_00_mprefix =
@ -4112,7 +4112,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_07_F3_leaf =
const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_07_NP_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2529]
(const void *)&gInstructions[2641]
};
const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_07_mprefix =
@ -4163,7 +4163,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_04_mprefix =
const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_01_F2_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2569]
(const void *)&gInstructions[2681]
};
const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_01_mprefix =
@ -4349,7 +4349,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_07_mprefix =
const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_02_04_NP_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[1764]
(const void *)&gInstructions[1849]
};
const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_04_mprefix =
@ -4366,7 +4366,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_04_mprefix =
const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_02_05_NP_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2554]
(const void *)&gInstructions[2666]
};
const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_05_mprefix =
@ -4383,7 +4383,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_05_mprefix =
const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_02_00_NP_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2555]
(const void *)&gInstructions[2667]
};
const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_00_mprefix =
@ -4400,7 +4400,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_00_mprefix =
const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_02_01_NP_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2582]
(const void *)&gInstructions[2694]
};
const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_01_mprefix =
@ -4417,7 +4417,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_01_mprefix =
const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_02_06_NP_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2588]
(const void *)&gInstructions[2700]
};
const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_06_mprefix =
@ -4483,7 +4483,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_05_mprefix =
const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_01_NP_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[1762]
(const void *)&gInstructions[1847]
};
const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_01_mprefix =
@ -4500,7 +4500,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_01_mprefix =
const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_02_NP_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[1775]
(const void *)&gInstructions[1862]
};
const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_02_mprefix =
@ -4517,7 +4517,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_02_mprefix =
const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_03_NP_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[1882]
(const void *)&gInstructions[1977]
};
const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_03_mprefix =
@ -4534,7 +4534,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_03_mprefix =
const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_04_NP_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[1894]
(const void *)&gInstructions[1991]
};
const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_04_mprefix =
@ -4892,13 +4892,13 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_06_66_leaf =
const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_06_NP_None_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2578]
(const void *)&gInstructions[2690]
};
const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_06_NP_rexw_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2579]
(const void *)&gInstructions[2691]
};
const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_mem_06_NP_auxiliary =
@ -5023,13 +5023,13 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_04_F3_leaf =
const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_04_NP_None_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2574]
(const void *)&gInstructions[2686]
};
const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_04_NP_rexw_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2575]
(const void *)&gInstructions[2687]
};
const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_mem_04_NP_auxiliary =
@ -5076,13 +5076,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_03_mprefix =
const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_05_NP_None_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2570]
(const void *)&gInstructions[2682]
};
const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_05_NP_rexw_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2571]
(const void *)&gInstructions[2683]
};
const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_mem_05_NP_auxiliary =
@ -5298,7 +5298,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_07_mprefix =
const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_02_F3_64_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2526]
(const void *)&gInstructions[2638]
};
const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_reg_02_F3_auxiliary =
@ -5328,7 +5328,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_02_mprefix =
const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_03_F3_64_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2527]
(const void *)&gInstructions[2639]
};
const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_reg_03_F3_auxiliary =
@ -5556,19 +5556,19 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_c7_mem_01_auxiliary =
const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_06_66_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[1763]
(const void *)&gInstructions[1848]
};
const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_06_NP_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[1879]
(const void *)&gInstructions[1974]
};
const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_06_F3_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[1895]
(const void *)&gInstructions[1992]
};
const ND_TABLE_MPREFIX gRootTable_root_0f_c7_mem_06_mprefix =
@ -5585,7 +5585,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_c7_mem_06_mprefix =
const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_07_NP_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[1880]
(const void *)&gInstructions[1975]
};
const ND_TABLE_MPREFIX gRootTable_root_0f_c7_mem_07_mprefix =
@ -5602,13 +5602,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_c7_mem_07_mprefix =
const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_03_NP_None_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2572]
(const void *)&gInstructions[2684]
};
const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_03_NP_rexw_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2573]
(const void *)&gInstructions[2685]
};
const ND_TABLE_AUXILIARY gRootTable_root_0f_c7_mem_03_NP_auxiliary =
@ -5638,13 +5638,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_c7_mem_03_mprefix =
const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_04_NP_None_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2576]
(const void *)&gInstructions[2688]
};
const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_04_NP_rexw_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2577]
(const void *)&gInstructions[2689]
};
const ND_TABLE_AUXILIARY gRootTable_root_0f_c7_mem_04_NP_auxiliary =
@ -5674,13 +5674,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_c7_mem_04_mprefix =
const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_05_NP_None_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2580]
(const void *)&gInstructions[2692]
};
const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_05_NP_rexw_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2581]
(const void *)&gInstructions[2693]
};
const ND_TABLE_AUXILIARY gRootTable_root_0f_c7_mem_05_NP_auxiliary =
@ -6365,7 +6365,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_78_None_F2_leaf =
const ND_TABLE_INSTRUCTION gRootTable_root_0f_78_None_NP_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[1881]
(const void *)&gInstructions[1976]
};
const ND_TABLE_MPREFIX gRootTable_root_0f_78_None_mprefix =
@ -6422,7 +6422,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_79_None_reg_F2_leaf =
const ND_TABLE_INSTRUCTION gRootTable_root_0f_79_None_reg_NP_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[1893]
(const void *)&gInstructions[1990]
};
const ND_TABLE_MPREFIX gRootTable_root_0f_79_None_reg_mprefix =
@ -6439,7 +6439,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_79_None_reg_mprefix =
const ND_TABLE_INSTRUCTION gRootTable_root_0f_79_None_mem_NP_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[1893]
(const void *)&gInstructions[1990]
};
const ND_TABLE_MPREFIX gRootTable_root_0f_79_None_mem_mprefix =
@ -6516,7 +6516,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_37_None_mprefix =
const ND_TABLE_INSTRUCTION gRootTable_root_0f_37_cyrix_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2530]
(const void *)&gInstructions[2642]
};
const ND_TABLE_VENDOR gRootTable_root_0f_37_vendor =
@ -6720,13 +6720,13 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_mem_01_leaf =
const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_mem_04_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[1507]
(const void *)&gInstructions[1546]
};
const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_mem_05_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[1508]
(const void *)&gInstructions[1547]
};
const ND_TABLE_MODRM_REG gRootTable_root_0f_00_mem_modrmreg =
@ -6794,13 +6794,13 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_reg_01_leaf =
const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_reg_04_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[1507]
(const void *)&gInstructions[1546]
};
const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_reg_05_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[1508]
(const void *)&gInstructions[1547]
};
const ND_TABLE_MODRM_REG gRootTable_root_0f_00_reg_modrmreg =
@ -7174,7 +7174,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_a6_reg_00_modrmrm =
const ND_TABLE_INSTRUCTION gRootTable_root_0f_a6_reg_01_00_F3_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2583]
(const void *)&gInstructions[2695]
};
const ND_TABLE_MPREFIX gRootTable_root_0f_a6_reg_01_00_mprefix =
@ -7206,7 +7206,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_a6_reg_01_modrmrm =
const ND_TABLE_INSTRUCTION gRootTable_root_0f_a6_reg_02_00_F3_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2584]
(const void *)&gInstructions[2696]
};
const ND_TABLE_MPREFIX gRootTable_root_0f_a6_reg_02_00_mprefix =
@ -11031,13 +11031,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_14_mprefix =
const ND_TABLE_INSTRUCTION gRootTable_root_0f_09_None_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2524]
(const void *)&gInstructions[2636]
};
const ND_TABLE_INSTRUCTION gRootTable_root_0f_09_aF3_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2525]
(const void *)&gInstructions[2637]
};
const ND_TABLE_AUXILIARY gRootTable_root_0f_09_auxiliary =
@ -11056,25 +11056,25 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_09_auxiliary =
const ND_TABLE_INSTRUCTION gRootTable_root_0f_30_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2528]
(const void *)&gInstructions[2640]
};
const ND_TABLE_INSTRUCTION gRootTable_root_0f_c0_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2536]
(const void *)&gInstructions[2648]
};
const ND_TABLE_INSTRUCTION gRootTable_root_0f_c1_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2537]
(const void *)&gInstructions[2649]
};
const ND_TABLE_INSTRUCTION gRootTable_root_0f_a7_reg_02_00_F3_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2549]
(const void *)&gInstructions[2661]
};
const ND_TABLE_MPREFIX gRootTable_root_0f_a7_reg_02_00_mprefix =
@ -11106,7 +11106,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_a7_reg_02_modrmrm =
const ND_TABLE_INSTRUCTION gRootTable_root_0f_a7_reg_04_00_F3_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2550]
(const void *)&gInstructions[2662]
};
const ND_TABLE_MPREFIX gRootTable_root_0f_a7_reg_04_00_mprefix =
@ -11138,7 +11138,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_a7_reg_04_modrmrm =
const ND_TABLE_INSTRUCTION gRootTable_root_0f_a7_reg_03_00_F3_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2551]
(const void *)&gInstructions[2663]
};
const ND_TABLE_MPREFIX gRootTable_root_0f_a7_reg_03_00_mprefix =
@ -11170,7 +11170,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_a7_reg_03_modrmrm =
const ND_TABLE_INSTRUCTION gRootTable_root_0f_a7_reg_01_00_F3_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2552]
(const void *)&gInstructions[2664]
};
const ND_TABLE_MPREFIX gRootTable_root_0f_a7_reg_01_00_mprefix =
@ -11202,7 +11202,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_a7_reg_01_modrmrm =
const ND_TABLE_INSTRUCTION gRootTable_root_0f_a7_reg_05_00_F3_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2553]
(const void *)&gInstructions[2665]
};
const ND_TABLE_MPREFIX gRootTable_root_0f_a7_reg_05_00_mprefix =
@ -11234,13 +11234,13 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_a7_reg_05_modrmrm =
const ND_TABLE_INSTRUCTION gRootTable_root_0f_a7_reg_00_00_None_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2585]
(const void *)&gInstructions[2697]
};
const ND_TABLE_INSTRUCTION gRootTable_root_0f_a7_reg_00_00_F3_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2586]
(const void *)&gInstructions[2698]
};
const ND_TABLE_MPREFIX gRootTable_root_0f_a7_reg_00_00_mprefix =
@ -11296,13 +11296,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_a7_modrmmod =
const ND_TABLE_INSTRUCTION gRootTable_root_0f_57_66_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2567]
(const void *)&gInstructions[2679]
};
const ND_TABLE_INSTRUCTION gRootTable_root_0f_57_NP_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2568]
(const void *)&gInstructions[2680]
};
const ND_TABLE_MPREFIX gRootTable_root_0f_57_mprefix =
@ -14392,7 +14392,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_c6_reg_00_leaf =
const ND_TABLE_INSTRUCTION gRootTable_root_c6_reg_07_00_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2535]
(const void *)&gInstructions[2647]
};
const ND_TABLE_MODRM_RM gRootTable_root_c6_reg_07_modrmrm =
@ -14464,7 +14464,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_c7_reg_00_leaf =
const ND_TABLE_INSTRUCTION gRootTable_root_c7_reg_07_00_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2538]
(const void *)&gInstructions[2650]
};
const ND_TABLE_MODRM_RM gRootTable_root_c7_reg_07_modrmrm =
@ -14634,7 +14634,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_90_aF3_leaf =
const ND_TABLE_INSTRUCTION gRootTable_root_90_rexb_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2541]
(const void *)&gInstructions[2653]
};
const ND_TABLE_AUXILIARY gRootTable_root_90_auxiliary =
@ -15838,103 +15838,103 @@ const ND_TABLE_INSTRUCTION gRootTable_root_a9_leaf =
const ND_TABLE_INSTRUCTION gRootTable_root_9b_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2523]
(const void *)&gInstructions[2635]
};
const ND_TABLE_INSTRUCTION gRootTable_root_86_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2539]
(const void *)&gInstructions[2651]
};
const ND_TABLE_INSTRUCTION gRootTable_root_87_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2540]
(const void *)&gInstructions[2652]
};
const ND_TABLE_INSTRUCTION gRootTable_root_91_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2542]
(const void *)&gInstructions[2654]
};
const ND_TABLE_INSTRUCTION gRootTable_root_92_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2543]
(const void *)&gInstructions[2655]
};
const ND_TABLE_INSTRUCTION gRootTable_root_93_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2544]
(const void *)&gInstructions[2656]
};
const ND_TABLE_INSTRUCTION gRootTable_root_94_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2545]
(const void *)&gInstructions[2657]
};
const ND_TABLE_INSTRUCTION gRootTable_root_95_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2546]
(const void *)&gInstructions[2658]
};
const ND_TABLE_INSTRUCTION gRootTable_root_96_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2547]
(const void *)&gInstructions[2659]
};
const ND_TABLE_INSTRUCTION gRootTable_root_97_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2548]
(const void *)&gInstructions[2660]
};
const ND_TABLE_INSTRUCTION gRootTable_root_d7_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2556]
(const void *)&gInstructions[2668]
};
const ND_TABLE_INSTRUCTION gRootTable_root_30_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2557]
(const void *)&gInstructions[2669]
};
const ND_TABLE_INSTRUCTION gRootTable_root_31_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2558]
(const void *)&gInstructions[2670]
};
const ND_TABLE_INSTRUCTION gRootTable_root_32_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2559]
(const void *)&gInstructions[2671]
};
const ND_TABLE_INSTRUCTION gRootTable_root_33_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2560]
(const void *)&gInstructions[2672]
};
const ND_TABLE_INSTRUCTION gRootTable_root_34_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2561]
(const void *)&gInstructions[2673]
};
const ND_TABLE_INSTRUCTION gRootTable_root_35_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2562]
(const void *)&gInstructions[2674]
};
const ND_TABLE_OPCODE gRootTable_root_opcode =

940
bddisasm/include/table_vex.h
View File

File diff suppressed because it is too large Load Diff

142
bddisasm/include/table_xop.h
View File

@ -420,127 +420,127 @@ const ND_TABLE_MODRM_MOD gXopTable_root_09_12_modrmmod =
const ND_TABLE_INSTRUCTION gXopTable_root_09_81_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[1695]
(const void *)&gInstructions[1774]
};
const ND_TABLE_INSTRUCTION gXopTable_root_09_80_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[1696]
(const void *)&gInstructions[1775]
};
const ND_TABLE_INSTRUCTION gXopTable_root_09_83_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[1697]
(const void *)&gInstructions[1776]
};
const ND_TABLE_INSTRUCTION gXopTable_root_09_82_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[1698]
(const void *)&gInstructions[1777]
};
const ND_TABLE_INSTRUCTION gXopTable_root_09_c2_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2088]
(const void *)&gInstructions[2185]
};
const ND_TABLE_INSTRUCTION gXopTable_root_09_c3_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2089]
(const void *)&gInstructions[2186]
};
const ND_TABLE_INSTRUCTION gXopTable_root_09_c1_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2090]
(const void *)&gInstructions[2187]
};
const ND_TABLE_INSTRUCTION gXopTable_root_09_cb_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2092]
(const void *)&gInstructions[2189]
};
const ND_TABLE_INSTRUCTION gXopTable_root_09_d2_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2094]
(const void *)&gInstructions[2191]
};
const ND_TABLE_INSTRUCTION gXopTable_root_09_d3_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2095]
(const void *)&gInstructions[2192]
};
const ND_TABLE_INSTRUCTION gXopTable_root_09_d1_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2096]
(const void *)&gInstructions[2193]
};
const ND_TABLE_INSTRUCTION gXopTable_root_09_db_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2097]
(const void *)&gInstructions[2194]
};
const ND_TABLE_INSTRUCTION gXopTable_root_09_d6_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2098]
(const void *)&gInstructions[2195]
};
const ND_TABLE_INSTRUCTION gXopTable_root_09_d7_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2099]
(const void *)&gInstructions[2196]
};
const ND_TABLE_INSTRUCTION gXopTable_root_09_c6_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2101]
(const void *)&gInstructions[2198]
};
const ND_TABLE_INSTRUCTION gXopTable_root_09_c7_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2102]
(const void *)&gInstructions[2199]
};
const ND_TABLE_INSTRUCTION gXopTable_root_09_e1_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2104]
(const void *)&gInstructions[2201]
};
const ND_TABLE_INSTRUCTION gXopTable_root_09_e3_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2106]
(const void *)&gInstructions[2203]
};
const ND_TABLE_INSTRUCTION gXopTable_root_09_e2_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2109]
(const void *)&gInstructions[2206]
};
const ND_TABLE_INSTRUCTION gXopTable_root_09_90_00_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2271]
(const void *)&gInstructions[2368]
};
const ND_TABLE_INSTRUCTION gXopTable_root_09_90_01_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2272]
(const void *)&gInstructions[2369]
};
const ND_TABLE_VEX_W gXopTable_root_09_90_w =
@ -555,13 +555,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_90_w =
const ND_TABLE_INSTRUCTION gXopTable_root_09_92_00_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2274]
(const void *)&gInstructions[2371]
};
const ND_TABLE_INSTRUCTION gXopTable_root_09_92_01_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2275]
(const void *)&gInstructions[2372]
};
const ND_TABLE_VEX_W gXopTable_root_09_92_w =
@ -576,13 +576,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_92_w =
const ND_TABLE_INSTRUCTION gXopTable_root_09_93_00_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2277]
(const void *)&gInstructions[2374]
};
const ND_TABLE_INSTRUCTION gXopTable_root_09_93_01_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2278]
(const void *)&gInstructions[2375]
};
const ND_TABLE_VEX_W gXopTable_root_09_93_w =
@ -597,13 +597,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_93_w =
const ND_TABLE_INSTRUCTION gXopTable_root_09_91_00_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2280]
(const void *)&gInstructions[2377]
};
const ND_TABLE_INSTRUCTION gXopTable_root_09_91_01_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2281]
(const void *)&gInstructions[2378]
};
const ND_TABLE_VEX_W gXopTable_root_09_91_w =
@ -618,13 +618,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_91_w =
const ND_TABLE_INSTRUCTION gXopTable_root_09_98_00_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2288]
(const void *)&gInstructions[2385]
};
const ND_TABLE_INSTRUCTION gXopTable_root_09_98_01_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2289]
(const void *)&gInstructions[2386]
};
const ND_TABLE_VEX_W gXopTable_root_09_98_w =
@ -639,13 +639,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_98_w =
const ND_TABLE_INSTRUCTION gXopTable_root_09_9a_00_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2290]
(const void *)&gInstructions[2387]
};
const ND_TABLE_INSTRUCTION gXopTable_root_09_9a_01_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2291]
(const void *)&gInstructions[2388]
};
const ND_TABLE_VEX_W gXopTable_root_09_9a_w =
@ -660,13 +660,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_9a_w =
const ND_TABLE_INSTRUCTION gXopTable_root_09_9b_00_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2292]
(const void *)&gInstructions[2389]
};
const ND_TABLE_INSTRUCTION gXopTable_root_09_9b_01_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2293]
(const void *)&gInstructions[2390]
};
const ND_TABLE_VEX_W gXopTable_root_09_9b_w =
@ -681,13 +681,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_9b_w =
const ND_TABLE_INSTRUCTION gXopTable_root_09_99_00_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2294]
(const void *)&gInstructions[2391]
};
const ND_TABLE_INSTRUCTION gXopTable_root_09_99_01_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2295]
(const void *)&gInstructions[2392]
};
const ND_TABLE_VEX_W gXopTable_root_09_99_w =
@ -702,13 +702,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_99_w =
const ND_TABLE_INSTRUCTION gXopTable_root_09_94_00_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2296]
(const void *)&gInstructions[2393]
};
const ND_TABLE_INSTRUCTION gXopTable_root_09_94_01_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2297]
(const void *)&gInstructions[2394]
};
const ND_TABLE_VEX_W gXopTable_root_09_94_w =
@ -723,13 +723,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_94_w =
const ND_TABLE_INSTRUCTION gXopTable_root_09_95_01_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2298]
(const void *)&gInstructions[2395]
};
const ND_TABLE_INSTRUCTION gXopTable_root_09_95_00_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2309]
(const void *)&gInstructions[2406]
};
const ND_TABLE_VEX_W gXopTable_root_09_95_w =
@ -744,13 +744,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_95_w =
const ND_TABLE_INSTRUCTION gXopTable_root_09_96_01_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2299]
(const void *)&gInstructions[2396]
};
const ND_TABLE_INSTRUCTION gXopTable_root_09_96_00_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2300]
(const void *)&gInstructions[2397]
};
const ND_TABLE_VEX_W gXopTable_root_09_96_w =
@ -765,13 +765,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_96_w =
const ND_TABLE_INSTRUCTION gXopTable_root_09_97_00_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2307]
(const void *)&gInstructions[2404]
};
const ND_TABLE_INSTRUCTION gXopTable_root_09_97_01_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2308]
(const void *)&gInstructions[2405]
};
const ND_TABLE_VEX_W gXopTable_root_09_97_w =
@ -1049,13 +1049,13 @@ const ND_TABLE_OPCODE gXopTable_root_09_opcode =
const ND_TABLE_INSTRUCTION gXopTable_root_08_a2_00_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[1970]
(const void *)&gInstructions[2067]
};
const ND_TABLE_INSTRUCTION gXopTable_root_08_a2_01_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[1971]
(const void *)&gInstructions[2068]
};
const ND_TABLE_VEX_W gXopTable_root_08_a2_w =
@ -1070,133 +1070,133 @@ const ND_TABLE_VEX_W gXopTable_root_08_a2_w =
const ND_TABLE_INSTRUCTION gXopTable_root_08_cc_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2000]
(const void *)&gInstructions[2097]
};
const ND_TABLE_INSTRUCTION gXopTable_root_08_ce_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2001]
(const void *)&gInstructions[2098]
};
const ND_TABLE_INSTRUCTION gXopTable_root_08_cf_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2006]
(const void *)&gInstructions[2103]
};
const ND_TABLE_INSTRUCTION gXopTable_root_08_ec_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2007]
(const void *)&gInstructions[2104]
};
const ND_TABLE_INSTRUCTION gXopTable_root_08_ee_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2008]
(const void *)&gInstructions[2105]
};
const ND_TABLE_INSTRUCTION gXopTable_root_08_ef_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2009]
(const void *)&gInstructions[2106]
};
const ND_TABLE_INSTRUCTION gXopTable_root_08_ed_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2010]
(const void *)&gInstructions[2107]
};
const ND_TABLE_INSTRUCTION gXopTable_root_08_cd_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2011]
(const void *)&gInstructions[2108]
};
const ND_TABLE_INSTRUCTION gXopTable_root_08_9e_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2124]
(const void *)&gInstructions[2221]
};
const ND_TABLE_INSTRUCTION gXopTable_root_08_9f_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2125]
(const void *)&gInstructions[2222]
};
const ND_TABLE_INSTRUCTION gXopTable_root_08_97_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2126]
(const void *)&gInstructions[2223]
};
const ND_TABLE_INSTRUCTION gXopTable_root_08_8e_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2127]
(const void *)&gInstructions[2224]
};
const ND_TABLE_INSTRUCTION gXopTable_root_08_8f_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2128]
(const void *)&gInstructions[2225]
};
const ND_TABLE_INSTRUCTION gXopTable_root_08_87_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2129]
(const void *)&gInstructions[2226]
};
const ND_TABLE_INSTRUCTION gXopTable_root_08_86_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2130]
(const void *)&gInstructions[2227]
};
const ND_TABLE_INSTRUCTION gXopTable_root_08_85_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2131]
(const void *)&gInstructions[2228]
};
const ND_TABLE_INSTRUCTION gXopTable_root_08_96_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2132]
(const void *)&gInstructions[2229]
};
const ND_TABLE_INSTRUCTION gXopTable_root_08_95_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2133]
(const void *)&gInstructions[2230]
};
const ND_TABLE_INSTRUCTION gXopTable_root_08_a6_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2134]
(const void *)&gInstructions[2231]
};
const ND_TABLE_INSTRUCTION gXopTable_root_08_b6_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2135]
(const void *)&gInstructions[2232]
};
const ND_TABLE_INSTRUCTION gXopTable_root_08_a3_00_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2260]
(const void *)&gInstructions[2357]
};
const ND_TABLE_INSTRUCTION gXopTable_root_08_a3_01_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2261]
(const void *)&gInstructions[2358]
};
const ND_TABLE_VEX_W gXopTable_root_08_a3_w =
@ -1211,25 +1211,25 @@ const ND_TABLE_VEX_W gXopTable_root_08_a3_w =
const ND_TABLE_INSTRUCTION gXopTable_root_08_c0_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2270]
(const void *)&gInstructions[2367]
};
const ND_TABLE_INSTRUCTION gXopTable_root_08_c2_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2273]
(const void *)&gInstructions[2370]
};
const ND_TABLE_INSTRUCTION gXopTable_root_08_c3_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2276]
(const void *)&gInstructions[2373]
};
const ND_TABLE_INSTRUCTION gXopTable_root_08_c1_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2279]
(const void *)&gInstructions[2376]
};
const ND_TABLE_OPCODE gXopTable_root_08_opcode =

6
bddisasm/include/tabledefs.h
View File

@ -32,6 +32,7 @@ typedef enum _ND_ILUT_TYPE
ND_ILUT_VEX_PP, // Table contains 4 entries. Next entry is vex/xop/evex.pp
ND_ILUT_VEX_L, // Table contains 4 entries. Next entry is vex/xop.l or evex.l'l
ND_ILUT_VEX_W, // Table contains 2 entries. Next entry is vex/xop/evex.w
ND_ILUT_VEX_WI, // Table contains 2 entries. Next entry is vex/xop/evex.w. If not in 64 bit, next entry is 0.
} ND_ILUT_TYPE;
@ -303,8 +304,10 @@ typedef enum _ND_OPERAND_SIZE_SPEC
ND_OPS_cl,
ND_OPS_sd,
ND_OPS_ss,
ND_OPS_sh,
ND_OPS_ps,
ND_OPS_pd,
ND_OPS_ph,
ND_OPS_e,
ND_OPS_f,
ND_OPS_h,
@ -507,6 +510,9 @@ typedef enum _ND_OPERAND_TYPE_SPEC
#define ND_OPD_B64 0x08 // 64 bit broadcast supported.
#define ND_OPD_SAE 0x10 // Suppress all exceptions supported.
#define ND_OPD_ER 0x20 // Embedded rounding supported.
#define ND_OPD_B16 0x40 // 16 bit broadcast supported.
#define ND_OPD_BCAST (ND_OPD_B16 | ND_OPD_B32 | ND_OPD_B64)
//

2
bddisasm_test/avx512/avx512bitalg_64
View File

@ -1 +1 @@
bò}TÐbò}Tb²}TTÛb²}TTÛðbò} TÐbò} Tb²} TTÛb²} TTÛðbò}ˆTÐbò}ˆTb²}ˆTTÛb²}ˆTTÛðbò}<EFBFBD>TÐbò}<7D>Tb²}<7D>TTÛb²}<7D>TTÛðbÂ}(TÇbâ}(Tb¢}(TDÛb¢}(TDÛøbÂ}-TÇbâ}-Tb¢}-TDÛb¢}-TDÛøbÂ}¨TÇbâ}¨Tb¢}¨TDÛb¢}¨TDÛøbÂ}­TÇbâ}­Tb¢}­TDÛb¢}­TDÛøb}HTÇbb}HTb"}HTDÛb"}HTDÛüb}MTÇbb}MTb"}MTDÛb"}MTDÛüb}ÈTÇbb}ÈTb"}ÈTDÛb"}ÈTDÛüb}ÍTÇbb}ÍTb"}ÍTDÛb"}ÍTDÛübòýTÐbòýTb²ýTTÛb²ýTTÛðbòý TÐbòý Tb²ý TTÛb²ý TTÛðbòýˆTÐbòýˆTb²ýˆTTÛb²ýˆTTÛðbòý<EFBFBD>TÐbòý<EFBFBD>Tb²ý<C2B2>TTÛb²ý<C2B2>TTÛðbÂý(TÇbâý(Tb¢ý(TDÛb¢ý(TDÛøbÂý-TÇbâý-Tb¢ý-TDÛb¢ý-TDÛøbÂý¨TÇbâý¨Tb¢ý¨TDÛb¢ý¨TDÛøbÂý­TÇbâý­Tb¢ý­TDÛb¢ý­TDÛøbýHTÇbbýHTb"ýHTDÛb"ýHTDÛübýMTÇbbýMTb"ýMTDÛb"ýMTDÛübýÈTÇbbýÈTb"ýÈTDÛb"ýÈTDÛübýÍTÇbbýÍTb"ýÍTDÛb"ýÍTDÛübòE<08>ØbòE<08>b²E<08>\Ûb²E<08>\ÛðbÒ(<28>ßbò(<28>b²(<28>\Ûb²(<28>\Ûøb’=@<40>ßbò=@<40>b²=@<40>\Ûb²=@<40>\ÛübòE <0A>ØbòE <0A>b²E <0A>\Ûb²E <0A>\ÛðbÒ-<2D>ßbò-<2D>b²-<2D>\Ûb²-<2D>\Ûøb’=E<>ßbò=E<>b²=E<>\Ûb²=E<>\Ûü
bò}TÐbò}Tb²}TTÛb²}TTÛðbò} TÐbò} Tb²} TTÛb²} TTÛðbò}<7D>TÐbò}<7D>Tb²}<7D>TTÛb²}<7D>TTÛðbÂ}(TÇbâ}(Tb¢}(TDÛb¢}(TDÛøbÂ}-TÇbâ}-Tb¢}-TDÛb¢}-TDÛøbÂ}­TÇbâ}­Tb¢}­TDÛb¢}­TDÛøb}HTÇbb}HTb"}HTDÛb"}HTDÛüb}MTÇbb}MTb"}MTDÛb"}MTDÛüb}ÍTÇbb}ÍTb"}ÍTDÛb"}ÍTDÛübòýTÐbòýTb²ýTTÛb²ýTTÛðbòý TÐbòý Tb²ý TTÛb²ý TTÛðbòý<C3B2>TÐbòý<C3B2>Tb²ý<C2B2>TTÛb²ý<C2B2>TTÛðbÂý(TÇbâý(Tb¢ý(TDÛb¢ý(TDÛøbÂý-TÇbâý-Tb¢ý-TDÛb¢ý-TDÛøbÂý­TÇbâý­Tb¢ý­TDÛb¢ý­TDÛøbýHTÇbbýHTb"ýHTDÛb"ýHTDÛübýMTÇbbýMTb"ýMTDÛb"ýMTDÛübýÍTÇbbýÍTb"ýÍTDÛb"ýÍTDÛübòE<08>ØbòE<08>b²E<08>\Ûb²E<08>\ÛðbÒ(<28>ßbò(<28>b²(<28>\Ûb²(<28>\Ûøb’=@<40>ßbò=@<40>b²=@<40>\Ûb²=@<40>\ÛübòE <0A>ØbòE <0A>b²E <0A>\Ûb²E <0A>\ÛðbÒ-<2D>ßbò-<2D>b²-<2D>\Ûb²-<2D>\Ûøb’=E<>ßbò=E<>b²=E<>\Ûb²=E<>\Ûü

24
bddisasm_test/avx512/avx512bitalg_64.asm
View File

@ -8,10 +8,6 @@
vpopcntb xmm2{k5}, [rbx]
vpopcntb xmm2{k5}, [rbx+r11*8+256]
vpopcntb xmm2{k5}, [rbx+r11*8-256]
vpopcntb xmm2{z}, xmm0
vpopcntb xmm2{z}, [rbx]
vpopcntb xmm2{z}, [rbx+r11*8+256]
vpopcntb xmm2{z}, [rbx+r11*8-256]
vpopcntb xmm2{k5}{z}, xmm0
vpopcntb xmm2{k5}{z}, [rbx]
vpopcntb xmm2{k5}{z}, [rbx+r11*8+256]
@ -24,10 +20,6 @@
vpopcntb ymm16{k5}, [rbx]
vpopcntb ymm16{k5}, [rbx+r11*8+256]
vpopcntb ymm16{k5}, [rbx+r11*8-256]
vpopcntb ymm16{z}, ymm15
vpopcntb ymm16{z}, [rbx]
vpopcntb ymm16{z}, [rbx+r11*8+256]
vpopcntb ymm16{z}, [rbx+r11*8-256]
vpopcntb ymm16{k5}{z}, ymm15
vpopcntb ymm16{k5}{z}, [rbx]
vpopcntb ymm16{k5}{z}, [rbx+r11*8+256]
@ -40,10 +32,6 @@
vpopcntb zmm24{k5}, [rbx]
vpopcntb zmm24{k5}, [rbx+r11*8+256]
vpopcntb zmm24{k5}, [rbx+r11*8-256]
vpopcntb zmm24{z}, zmm31
vpopcntb zmm24{z}, [rbx]
vpopcntb zmm24{z}, [rbx+r11*8+256]
vpopcntb zmm24{z}, [rbx+r11*8-256]
vpopcntb zmm24{k5}{z}, zmm31
vpopcntb zmm24{k5}{z}, [rbx]
vpopcntb zmm24{k5}{z}, [rbx+r11*8+256]
@ -56,10 +44,6 @@
vpopcntw xmm2{k5}, [rbx]
vpopcntw xmm2{k5}, [rbx+r11*8+256]
vpopcntw xmm2{k5}, [rbx+r11*8-256]
vpopcntw xmm2{z}, xmm0
vpopcntw xmm2{z}, [rbx]
vpopcntw xmm2{z}, [rbx+r11*8+256]
vpopcntw xmm2{z}, [rbx+r11*8-256]
vpopcntw xmm2{k5}{z}, xmm0
vpopcntw xmm2{k5}{z}, [rbx]
vpopcntw xmm2{k5}{z}, [rbx+r11*8+256]
@ -72,10 +56,6 @@
vpopcntw ymm16{k5}, [rbx]
vpopcntw ymm16{k5}, [rbx+r11*8+256]
vpopcntw ymm16{k5}, [rbx+r11*8-256]
vpopcntw ymm16{z}, ymm15
vpopcntw ymm16{z}, [rbx]
vpopcntw ymm16{z}, [rbx+r11*8+256]
vpopcntw ymm16{z}, [rbx+r11*8-256]
vpopcntw ymm16{k5}{z}, ymm15
vpopcntw ymm16{k5}{z}, [rbx]
vpopcntw ymm16{k5}{z}, [rbx+r11*8+256]
@ -88,10 +68,6 @@
vpopcntw zmm24{k5}, [rbx]
vpopcntw zmm24{k5}, [rbx+r11*8+256]
vpopcntw zmm24{k5}, [rbx+r11*8-256]
vpopcntw zmm24{z}, zmm31
vpopcntw zmm24{z}, [rbx]
vpopcntw zmm24{z}, [rbx+r11*8+256]
vpopcntw zmm24{z}, [rbx+r11*8-256]
vpopcntw zmm24{k5}{z}, zmm31
vpopcntw zmm24{k5}{z}, [rbx]
vpopcntw zmm24{k5}{z}, [rbx+r11*8+256]

674
bddisasm_test/avx512/avx512bitalg_64.result
View File

File diff suppressed because it is too large Load Diff

BIN
bddisasm_test/avx512/avx512bw_64
View File

Binary file not shown.

747
bddisasm_test/avx512/avx512bw_64.asm
View File

File diff suppressed because it is too large Load Diff

21528
bddisasm_test/avx512/avx512bw_64.result
View File

File diff suppressed because it is too large Load Diff

2
bddisasm_test/avx512/avx512cd_64
View File

@ -1 +1 @@
b<EFBFBD><EFBFBD>*<2A>b<EFBFBD><62>(*<2A>bb<62>H*<2A>b<EFBFBD>~:<3A>b<EFBFBD>~(:<3A>bb~H:<3A>b<EFBFBD>}<08><>b<EFBFBD>}<08>b<>}<18>b<>}<08>T<EFBFBD>b<>}<08>T<EFBFBD><54>b<EFBFBD>} <0A><>b<EFBFBD>} <0A>b<>}<1D>b<>} <0A>T<EFBFBD>b<>} <0A>T<EFBFBD><54>b<EFBFBD>}<7D><><EFBFBD>b<EFBFBD>}<7D><>b<>}<7D><>b<>}<7D><>T<EFBFBD>b<>}<7D><>T<EFBFBD><54>b<EFBFBD>}<7D><><EFBFBD>b<EFBFBD>}<7D><>b<>}<7D><>b<>}<7D><>T<EFBFBD>b<>}<7D><>T<EFBFBD><54>b<EFBFBD>}(<28><>b<EFBFBD>}(<28>b<>}8<>b<>}(<28>D<EFBFBD>b<>}(<28>D<EFBFBD><44>b<EFBFBD>}-<2D><>b<EFBFBD>}-<2D>b<>}=<3D>b<>}-<2D>D<EFBFBD>b<>}-<2D>D<EFBFBD><44>b<EFBFBD>}<7D><><EFBFBD>b<EFBFBD>}<7D><>b<>}<7D><>b<>}<7D><>D<EFBFBD>b<>}<7D><>D<EFBFBD><44>b<EFBFBD>}<7D><><EFBFBD>b<EFBFBD>}<7D><>b<>}<7D><>b<>}<7D><>D<EFBFBD>b<>}<7D><>D<EFBFBD><44>b}H<><48>bb}H<>bb}X<>b"}H<>D<EFBFBD>b"}H<>D<EFBFBD><44>b}M<><4D>bb}M<>bb}]<5D>b"}M<>D<EFBFBD>b"}M<>D<EFBFBD><44>b}<7D><><EFBFBD>bb}<7D><>bb}<7D><>b"}<7D><>D<EFBFBD>b"}<7D><>D<EFBFBD><44>b}<7D><><EFBFBD>bb}<7D><>bb}<7D><>b"}<7D><>D<EFBFBD>b"}<7D><>D<EFBFBD><44>b<EFBFBD><62><08><>b<EFBFBD><62><08>b<><62><18>b<><62><08>T<EFBFBD>b<><62><08>T<EFBFBD><54>b<EFBFBD><62> <0A><>b<EFBFBD><62> <0A>b<><62><1D>b<><62> <0A>T<EFBFBD>b<><62> <0A>T<EFBFBD><54>b<EFBFBD><62><EFBFBD><EFBFBD><EFBFBD>b<EFBFBD><62><EFBFBD><EFBFBD>b<><62><EFBFBD><EFBFBD>b<><62><EFBFBD><EFBFBD>T<EFBFBD>b<><62><EFBFBD><EFBFBD>T<EFBFBD><54>b<EFBFBD><62><EFBFBD><EFBFBD><EFBFBD>b<EFBFBD><62><EFBFBD><EFBFBD>b<><62><EFBFBD><EFBFBD>b<><62><EFBFBD><EFBFBD>T<EFBFBD>b<><62><EFBFBD><EFBFBD>T<EFBFBD><54>b<EFBFBD><62>(<28><>b<EFBFBD><62>(<28>b<><62>8<EFBFBD>b<><62>(<28>D<EFBFBD>b<><62>(<28>D<EFBFBD><44>b<EFBFBD><62>-<2D><>b<EFBFBD><62>-<2D>b<><62>=<3D>b<><62>-<2D>D<EFBFBD>b<><62>-<2D>D<EFBFBD><44>b<EFBFBD><62><EFBFBD><EFBFBD><EFBFBD>b<EFBFBD><62><EFBFBD><EFBFBD>b<><62><EFBFBD><EFBFBD>b<><62><EFBFBD><EFBFBD>D<EFBFBD>b<><62><EFBFBD><EFBFBD>D<EFBFBD><44>b<EFBFBD><62><EFBFBD><EFBFBD><EFBFBD>b<EFBFBD><62><EFBFBD><EFBFBD>b<><62><EFBFBD><EFBFBD>b<><62><EFBFBD><EFBFBD>D<EFBFBD>b<><62><EFBFBD><EFBFBD>D<EFBFBD><44>b<02>H<EFBFBD><48>bb<62>H<EFBFBD>bb<62>X<EFBFBD>b"<22>H<EFBFBD>D<EFBFBD>b"<22>H<EFBFBD>D<EFBFBD><44>b<02>M<EFBFBD><4D>bb<62>M<EFBFBD>bb<62>]<5D>b"<22>M<EFBFBD>D<EFBFBD>b"<22>M<EFBFBD>D<EFBFBD><44>b<02><><EFBFBD><EFBFBD>bb<62><62><EFBFBD>bb<62><62><EFBFBD>b"<22><><EFBFBD>D<EFBFBD>b"<22><><EFBFBD>D<EFBFBD><44>b<02><><EFBFBD><EFBFBD>bb<62><62><EFBFBD>bb<62><62><EFBFBD>b"<22><><EFBFBD>D<EFBFBD>b"<22><><EFBFBD>D<EFBFBD><44>b<EFBFBD>}D<>b<EFBFBD>}Db<>}Db<>}DT<44>b<>}DT<44><54>b<EFBFBD>} D<>b<EFBFBD>} Db<>}Db<>} DT<44>b<>} DT<44><54>b<EFBFBD>}<7D>D<EFBFBD>b<EFBFBD>}<7D>Db<>}<7D>Db<>}<7D>DT<44>b<>}<7D>DT<44><54>b<EFBFBD>}<EFBFBD>D<EFBFBD>b<EFBFBD>}<7D>Db<>}<7D>Db<>}<7D>DT<44>b<>}<7D>DT<44><54>b<EFBFBD>}(D<>b<EFBFBD>}(Db<>}8Db<>}(DD<44>b<>}(DD<44><44>b<EFBFBD>}-D<>b<EFBFBD>}-Db<>}=Db<>}-DD<44>b<>}-DD<44><44>b<EFBFBD>}<7D>D<EFBFBD>b<EFBFBD>}<7D>Db<>}<7D>Db<>}<7D>DD<44>b<>}<7D>DD<44><44>b<EFBFBD>}<7D>D<EFBFBD>b<EFBFBD>}<7D>Db<>}<7D>Db<>}<7D>DD<44>b<>}<7D>DD<44><44>b}HD<48>bb}HDbb}XDb"}HDD<44>b"}HDD<44><44>b}MD<4D>bb}MDbb}]Db"}MDD<44>b"}MDD<EFBFBD><EFBFBD>b}<7D>D<EFBFBD>bb}<7D>Dbb}<7D>Db"}<7D>DD<44>b"}<7D>DD<EFBFBD><EFBFBD>b}<7D>D<EFBFBD>bb}<7D>Dbb}<7D>Db"}<7D>DD<44>b"}<7D>DD<44><44>b<EFBFBD><62>D<>b<EFBFBD><62>Db<><62>Db<><62>DT<44>b<><62>DT<44><54>b<EFBFBD><62> D<>b<EFBFBD><62> Db<><62>Db<><62> DT<44>b<><62> <0A><><EFBFBD>b<EFBFBD>}<7D><>b<>}<7D><>b<>}<7D><>T<EFBFBD>b<>}<7D><>T<EFBFBD><54>b<EFBFBD>}(<28><>b<EFBFBD>}(<28>b<>}8<>b<>}(<28>D<EFBFBD>b<>}(<28>D<EFBFBD><44>b<EFBFBD>}-<2D><>b<EFBFBD>}-<2D>b<>}=<3D>b<>}-<2D>D<EFBFBD>b<>}-<2D>D<EFBFBD><44>b<EFBFBD>}<7D><><EFBFBD>b<EFBFBD>}<7D><>b<>}<7D><>b<>}<7D><>D<EFBFBD>b<>}<7D><>D<EFBFBD><44>b<EFBFBD>}<7D><><EFBFBD>b<EFBFBD>}<7D><>b<>}<7D><>b<>}<7D><>D<EFBFBD>b<>}<7D><>D<EFBFBD><44>b}H<><48>bb}H<>bb}X<>b"}H<>D<EFBFBD>b"}H<>D<EFBFBD><44>b}M<><4D>bb}M<>bb}]<5D>b"}M<>D<EFBFBD>b"}M<>D<EFBFBD><44>b}<7D><><EFBFBD>bb}<7D><>bb}<7D><>b"}<7D><>D<EFBFBD>b"}<7D><>D<EFBFBD><44>b}<7D><><EFBFBD>bb}<7D><>bb}<7D><>b"}<7D><>D<EFBFBD>b"}<7D><>D<EFBFBD><44>b<EFBFBD><62><08><>b<EFBFBD><62><08>b<><62><18>b<><62><08>T<EFBFBD>b<><62><08>T<EFBFBD><54>b<EFBFBD><62> <EFBFBD>b<><62><1D>b<><62> DD<44><44>b<02><>D<EFBFBD>bb<62><62>Dbb<62><62>Db"<22><>DD<44>b"<22><>DD<44><44>
b<EFBFBD><EFBFBD>*<2A>b<EFBFBD><62>(*<2A>bb<62>H*<2A>b<EFBFBD>~:<3A>b<EFBFBD>~(:<3A>bb~H:<3A>b<EFBFBD>}<08><>b<EFBFBD>}<08>b<>}<18>b<>}<08>T<EFBFBD>b<>}<08>T<EFBFBD><54>b<EFBFBD>} <0A><>b<EFBFBD>} <0A>b<>}<1D>b<>} <0A>T<EFBFBD>b<>} <0A>T<EFBFBD><54>b<EFBFBD>}<7D><><EFBFBD>b<EFBFBD>}<7D><>b<>}<7D><>b<>}<7D><>T<EFBFBD>b<>}<7D><>T<EFBFBD><54>b<EFBFBD>}<7D><><EFBFBD>b<EFBFBD>}<7D><>b<>}<7D><>b<>}<7D><>T<EFBFBD>b<>}<7D><>T<EFBFBD><54>b<EFBFBD>}(<28><>b<EFBFBD>}(<28>b<>}8<>b<>}(<28>D<EFBFBD>b<>}(<28>D<EFBFBD><44>b<EFBFBD>}-<2D><>b<EFBFBD>}-<2D>b<>}=<3D>b<>}-<2D>D<EFBFBD>b<>}-<2D>D<EFBFBD><44>b<EFBFBD>}<7D><><EFBFBD>b<EFBFBD>}<7D><>b<>}<7D><>b<>}<7D><>D<EFBFBD>b<>}<7D><>D<EFBFBD><44>b<EFBFBD>}<7D><><EFBFBD>b<EFBFBD>}<7D><>b<>}<7D><>b<>}<7D><>D<EFBFBD>b<>}<7D><>D<EFBFBD><44>b}H<><48>bb}H<>bb}X<>b"}H<>D<EFBFBD>b"}H<>D<EFBFBD><44>b}M<><4D>bb}M<>bb}]<5D>b"}M<>D<EFBFBD>b"}M<>D<EFBFBD><44>b}<7D><><EFBFBD>bb}<7D><>bb}<7D><>b"}<7D><>D<EFBFBD>b"}<7D><>D<EFBFBD><44>b}<7D><><EFBFBD>bb}<7D><>bb}<7D><>b"}<7D><>D<EFBFBD>b"}<7D><>D<EFBFBD><44>b<EFBFBD><62><08><>b<EFBFBD><62><08>b<><62><18>b<><62><08>T<EFBFBD>b<><62><08>T<EFBFBD><54>b<EFBFBD><62> <EFBFBD>T<EFBFBD>b<><62> <EFBFBD><EFBFBD>b<EFBFBD><EFBFBD> <0A>b<><62><1D>b<><62> <0A>T<EFBFBD>b<><62> <EFBFBD><EFBFBD><EFBFBD>b<EFBFBD>}<7D><>b<>}<7D><>b<>}<7D><>T<EFBFBD>b<>}<7D><>T<EFBFBD><54>b<EFBFBD>}(<28><>b<EFBFBD>}(<28>b<>}8<>b<>}(<28>D<EFBFBD>b<>}(<28>D<EFBFBD><44>b<EFBFBD>}-<2D><>b<EFBFBD>}-<2D>b<>}=<3D>b<>}-<2D>D<EFBFBD>b<>}-<2D>D<EFBFBD><44>b<EFBFBD>}<7D><><EFBFBD>b<EFBFBD>}<7D><>b<>}<7D><>b<>}<7D><>D<EFBFBD>b<>}<7D><>D<EFBFBD><44>b<EFBFBD>}<7D><><EFBFBD>b<EFBFBD>}<7D><>b<>}<7D><>b<>}<7D><>D<EFBFBD>b<>}<7D><>D<EFBFBD><44>b}H<><48>bb}H<>bb}X<>b"}H<>D<EFBFBD>b"}H<>D<EFBFBD><44>b}M<><4D>bb}M<>bb}]<5D>b"}M<>D<EFBFBD>b"}M<>D<EFBFBD><44>b}<7D><><EFBFBD>bb}<7D><>bb}<7D><>b"}<7D><>D<EFBFBD>b"}<7D><>D<EFBFBD><44>b}<7D><><EFBFBD>bb}<7D><>bb}<7D><>b"}<7D><>D<EFBFBD>b"}<7D><>D<EFBFBD><44>b<EFBFBD><62><08><>b<EFBFBD><62><08>b<><62><18>b<><62><08>T<EFBFBD>b<><62><08>T<EFBFBD><54>b<EFBFBD><62> <EFBFBD>T<EFBFBD><EFBFBD>b<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>b<EFBFBD><EFBFBD><EFBFBD><EFBFBD>b<><62><EFBFBD><EFBFBD>b<><62><EFBFBD><EFBFBD>T<EFBFBD>b<><62><EFBFBD><EFBFBD>T<EFBFBD><54>b<EFBFBD><62><EFBFBD><EFBFBD><EFBFBD>b<EFBFBD><62><EFBFBD><EFBFBD>b<><62><EFBFBD><EFBFBD>b<><62><EFBFBD><EFBFBD>T<EFBFBD>b<><62><EFBFBD><EFBFBD>T<EFBFBD><54>b<EFBFBD><62>(<28><>b<EFBFBD><62>(<28>b<><62>8<EFBFBD>b<><62>(<28>D<EFBFBD>b<><62>(<28>D<EFBFBD><44>b<EFBFBD><62>-<2D><>b<EFBFBD><62>-<2D>b<><62>=<3D>b<><62>-<2D>D<EFBFBD>b<><62>-<2D>D<EFBFBD><44>b<EFBFBD><62><EFBFBD><EFBFBD><EFBFBD>b<EFBFBD><62><EFBFBD><EFBFBD>b<><62><EFBFBD><EFBFBD>b<><62><EFBFBD><EFBFBD>D<EFBFBD>b<><62><EFBFBD><EFBFBD>D<EFBFBD><44>b<EFBFBD><62><EFBFBD><EFBFBD><EFBFBD>b<EFBFBD><62><EFBFBD><EFBFBD>b<><62><EFBFBD><EFBFBD>b<><62><EFBFBD><EFBFBD>D<EFBFBD>b<><62><EFBFBD><EFBFBD>D<EFBFBD><44>b<02>H<EFBFBD><48>bb<62>H<EFBFBD>bb<62>X<EFBFBD>b"<22>H<EFBFBD>D<EFBFBD>b"<22>H<EFBFBD>D<EFBFBD><44>b<02>M<EFBFBD><4D>bb<62>M<EFBFBD>bb<62>]<5D>b"<22>M<EFBFBD>D<EFBFBD>b"<22>M<EFBFBD>D<EFBFBD><44>b<02><><EFBFBD><EFBFBD>bb<62><62><EFBFBD>bb<62><62><EFBFBD>b"<22><><EFBFBD>D<EFBFBD>b"<22><><EFBFBD>D<EFBFBD><44>b<02><><EFBFBD><EFBFBD>bb<62><62><EFBFBD>bb<62><62><EFBFBD>b"<22><><EFBFBD>D<EFBFBD>b"<22><><EFBFBD>D<EFBFBD><44>b<EFBFBD>}D<>b<EFBFBD>}Db<>}Db<>}DT<44>b<>}DT<44><54>b<EFBFBD>} D<>b<EFBFBD>} Db<>}Db<>} DT<44>b<>} DT<44><54>b<EFBFBD>}<7D>D<EFBFBD>b<EFBFBD>}<7D>Db<>}<7D>Db<>}<7D>DT<44>b<>}<7D>DT<44><54>b<EFBFBD>}(D<>b<EFBFBD>}(Db<>}8Db<>}(DD<44>b<>}(DD<44><44>b<EFBFBD>}-D<>b<EFBFBD>}-Db<>}=Db<>}-DD<44>b<>}-DD<44><44>b<EFBFBD>}<7D>D<EFBFBD>b<EFBFBD>}<7D>Db<>}<7D>Db<>}<7D>DD<44>b<>}<7D>DD<44><44>b}HD<48>bb}HDbb}XDb"}HDD<44>b"}HDD<44><44>b}MD<4D>bb}MDbb}]Db"}MDD<44>b"}MDD<44><44>b}<7D>D<EFBFBD>bb}<7D>Dbb}<7D>Db"}<7D>DD<44>b"}<7D>DD<44><44>b<EFBFBD><62>D<>b<EFBFBD><62>Db<><62>Db<><62>DT<44>b<><62>DT<44><54>b<EFBFBD><62> D<>b<EFBFBD><62> Db<><62>Db<><62> DT<44>b<><62> <0A><><EFBFBD>b<EFBFBD>}<7D><>b<>}<7D><>b<>}<7D><>T<EFBFBD>b<>}<7D><>T<EFBFBD><54>b<EFBFBD>}(<28><>b<EFBFBD>}(<28>b<>}8<>b<>}(<28>D<EFBFBD>b<>}(<28>D<EFBFBD><44>b<EFBFBD>}-<2D><>b<EFBFBD>}-<2D>b<>}=<3D>b<>}-<2D>D<EFBFBD>b<>}-<2D>D<EFBFBD><44>b<EFBFBD>}<7D><><EFBFBD>b<EFBFBD>}<7D><>b<>}<7D><>b<>}<7D><>D<EFBFBD>b<>}<7D><>D<EFBFBD><44>b<EFBFBD>}<7D><><EFBFBD>b<EFBFBD>}<7D><>b<>}<7D><>b<>}<7D><>D<EFBFBD>b<>}<7D><>D<EFBFBD><44>b}H<><48>bb}H<>bb}X<>b"}H<>D<EFBFBD>b"}H<>D<EFBFBD><44>b}M<><4D>bb}M<>bb}]<5D>b"}M<>D<EFBFBD>b"}M<>D<EFBFBD><44>b}<7D><><EFBFBD>bb}<7D><>bb}<7D><>b"}<7D><>D<EFBFBD>b"}<7D><>D<EFBFBD><44>b}<7D><><EFBFBD>bb}<7D><>bb}<7D><>b"}<7D><>D<EFBFBD>b"}<7D><>D<EFBFBD><44>b<EFBFBD><62><08><>b<EFBFBD><62><08>b<><62><18>b<><62><08>T<EFBFBD>b<><62><08>T<EFBFBD><54>b<EFBFBD><62> Db<>}Db<>} DD<44><44>b<02><>D<EFBFBD>bb<62><62>Dbb<62><62>Db"<22><>DD<44>b"<22><>DD<44><44>

60
bddisasm_test/avx512/avx512cd_64.asm
View File

@ -16,11 +16,6 @@
vpconflictd xmm2{k5}, [rbx]{1to4}
vpconflictd xmm2{k5}, [rbx+r11*8+256]
vpconflictd xmm2{k5}, [rbx+r11*8-256]
vpconflictd xmm2{z}, xmm0
vpconflictd xmm2{z}, [rbx]
vpconflictd xmm2{z}, [rbx]{1to4}
vpconflictd xmm2{z}, [rbx+r11*8+256]
vpconflictd xmm2{z}, [rbx+r11*8-256]
vpconflictd xmm2{k5}{z}, xmm0
vpconflictd xmm2{k5}{z}, [rbx]
vpconflictd xmm2{k5}{z}, [rbx]{1to4}
@ -36,11 +31,6 @@
vpconflictd ymm16{k5}, [rbx]{1to8}
vpconflictd ymm16{k5}, [rbx+r11*8+256]
vpconflictd ymm16{k5}, [rbx+r11*8-256]
vpconflictd ymm16{z}, ymm15
vpconflictd ymm16{z}, [rbx]
vpconflictd ymm16{z}, [rbx]{1to8}
vpconflictd ymm16{z}, [rbx+r11*8+256]
vpconflictd ymm16{z}, [rbx+r11*8-256]
vpconflictd ymm16{k5}{z}, ymm15
vpconflictd ymm16{k5}{z}, [rbx]
vpconflictd ymm16{k5}{z}, [rbx]{1to8}
@ -56,11 +46,6 @@
vpconflictd zmm24{k5}, [rbx]{1to16}
vpconflictd zmm24{k5}, [rbx+r11*8+256]
vpconflictd zmm24{k5}, [rbx+r11*8-256]
vpconflictd zmm24{z}, zmm31
vpconflictd zmm24{z}, [rbx]
vpconflictd zmm24{z}, [rbx]{1to16}
vpconflictd zmm24{z}, [rbx+r11*8+256]
vpconflictd zmm24{z}, [rbx+r11*8-256]
vpconflictd zmm24{k5}{z}, zmm31
vpconflictd zmm24{k5}{z}, [rbx]
vpconflictd zmm24{k5}{z}, [rbx]{1to16}
@ -76,11 +61,6 @@
vpconflictq xmm2{k5}, [rbx]{1to2}
vpconflictq xmm2{k5}, [rbx+r11*8+256]
vpconflictq xmm2{k5}, [rbx+r11*8-256]
vpconflictq xmm2{z}, xmm0
vpconflictq xmm2{z}, [rbx]
vpconflictq xmm2{z}, [rbx]{1to2}
vpconflictq xmm2{z}, [rbx+r11*8+256]
vpconflictq xmm2{z}, [rbx+r11*8-256]
vpconflictq xmm2{k5}{z}, xmm0
vpconflictq xmm2{k5}{z}, [rbx]
vpconflictq xmm2{k5}{z}, [rbx]{1to2}
@ -96,11 +76,6 @@
vpconflictq ymm16{k5}, [rbx]{1to4}
vpconflictq ymm16{k5}, [rbx+r11*8+256]
vpconflictq ymm16{k5}, [rbx+r11*8-256]
vpconflictq ymm16{z}, ymm15
vpconflictq ymm16{z}, [rbx]
vpconflictq ymm16{z}, [rbx]{1to4}
vpconflictq ymm16{z}, [rbx+r11*8+256]
vpconflictq ymm16{z}, [rbx+r11*8-256]
vpconflictq ymm16{k5}{z}, ymm15
vpconflictq ymm16{k5}{z}, [rbx]
vpconflictq ymm16{k5}{z}, [rbx]{1to4}
@ -116,11 +91,6 @@
vpconflictq zmm24{k5}, [rbx]{1to8}
vpconflictq zmm24{k5}, [rbx+r11*8+256]
vpconflictq zmm24{k5}, [rbx+r11*8-256]
vpconflictq zmm24{z}, zmm31
vpconflictq zmm24{z}, [rbx]
vpconflictq zmm24{z}, [rbx]{1to8}
vpconflictq zmm24{z}, [rbx+r11*8+256]
vpconflictq zmm24{z}, [rbx+r11*8-256]
vpconflictq zmm24{k5}{z}, zmm31
vpconflictq zmm24{k5}{z}, [rbx]
vpconflictq zmm24{k5}{z}, [rbx]{1to8}
@ -136,11 +106,6 @@
vplzcntd xmm2{k5}, [rbx]{1to4}
vplzcntd xmm2{k5}, [rbx+r11*8+256]
vplzcntd xmm2{k5}, [rbx+r11*8-256]
vplzcntd xmm2{z}, xmm0
vplzcntd xmm2{z}, [rbx]
vplzcntd xmm2{z}, [rbx]{1to4}
vplzcntd xmm2{z}, [rbx+r11*8+256]
vplzcntd xmm2{z}, [rbx+r11*8-256]
vplzcntd xmm2{k5}{z}, xmm0
vplzcntd xmm2{k5}{z}, [rbx]
vplzcntd xmm2{k5}{z}, [rbx]{1to4}
@ -156,11 +121,6 @@
vplzcntd ymm16{k5}, [rbx]{1to8}
vplzcntd ymm16{k5}, [rbx+r11*8+256]
vplzcntd ymm16{k5}, [rbx+r11*8-256]
vplzcntd ymm16{z}, ymm15
vplzcntd ymm16{z}, [rbx]
vplzcntd ymm16{z}, [rbx]{1to8}
vplzcntd ymm16{z}, [rbx+r11*8+256]
vplzcntd ymm16{z}, [rbx+r11*8-256]
vplzcntd ymm16{k5}{z}, ymm15
vplzcntd ymm16{k5}{z}, [rbx]
vplzcntd ymm16{k5}{z}, [rbx]{1to8}
@ -176,11 +136,6 @@
vplzcntd zmm24{k5}, [rbx]{1to16}
vplzcntd zmm24{k5}, [rbx+r11*8+256]
vplzcntd zmm24{k5}, [rbx+r11*8-256]
vplzcntd zmm24{z}, zmm31
vplzcntd zmm24{z}, [rbx]
vplzcntd zmm24{z}, [rbx]{1to16}
vplzcntd zmm24{z}, [rbx+r11*8+256]
vplzcntd zmm24{z}, [rbx+r11*8-256]
vplzcntd zmm24{k5}{z}, zmm31
vplzcntd zmm24{k5}{z}, [rbx]
vplzcntd zmm24{k5}{z}, [rbx]{1to16}
@ -196,11 +151,6 @@
vplzcntq xmm2{k5}, [rbx]{1to2}
vplzcntq xmm2{k5}, [rbx+r11*8+256]
vplzcntq xmm2{k5}, [rbx+r11*8-256]
vplzcntq xmm2{z}, xmm0
vplzcntq xmm2{z}, [rbx]
vplzcntq xmm2{z}, [rbx]{1to2}
vplzcntq xmm2{z}, [rbx+r11*8+256]
vplzcntq xmm2{z}, [rbx+r11*8-256]
vplzcntq xmm2{k5}{z}, xmm0
vplzcntq xmm2{k5}{z}, [rbx]
vplzcntq xmm2{k5}{z}, [rbx]{1to2}
@ -216,11 +166,6 @@
vplzcntq ymm16{k5}, [rbx]{1to4}
vplzcntq ymm16{k5}, [rbx+r11*8+256]
vplzcntq ymm16{k5}, [rbx+r11*8-256]
vplzcntq ymm16{z}, ymm15
vplzcntq ymm16{z}, [rbx]
vplzcntq ymm16{z}, [rbx]{1to4}
vplzcntq ymm16{z}, [rbx+r11*8+256]
vplzcntq ymm16{z}, [rbx+r11*8-256]
vplzcntq ymm16{k5}{z}, ymm15
vplzcntq ymm16{k5}{z}, [rbx]
vplzcntq ymm16{k5}{z}, [rbx]{1to4}
@ -236,11 +181,6 @@
vplzcntq zmm24{k5}, [rbx]{1to8}
vplzcntq zmm24{k5}, [rbx+r11*8+256]
vplzcntq zmm24{k5}, [rbx+r11*8-256]
vplzcntq zmm24{z}, zmm31
vplzcntq zmm24{z}, [rbx]
vplzcntq zmm24{z}, [rbx]{1to8}
vplzcntq zmm24{z}, [rbx+r11*8+256]
vplzcntq zmm24{z}, [rbx+r11*8-256]
vplzcntq zmm24{k5}{z}, zmm31
vplzcntq zmm24{k5}{z}, [rbx]
vplzcntq zmm24{k5}{z}, [rbx]{1to8}

1600
bddisasm_test/avx512/avx512cd_64.result
View File

File diff suppressed because it is too large Load Diff

BIN
bddisasm_test/avx512/avx512dq_64
View File

Binary file not shown.

453
bddisasm_test/avx512/avx512dq_64.asm
View File

File diff suppressed because it is too large Load Diff

12667
bddisasm_test/avx512/avx512dq_64.result
View File

File diff suppressed because it is too large Load Diff

2
bddisasm_test/avx512/avx512er_64
View File

@ -1 +1 @@
býHÈÇbýÈÇbbýHÈbbýXÈb"ýHÈDÛb"ýHÈDÛübýMÈÇbýÈÇbbýMÈbbý]Èb"ýMÈDÛb"ýMÈDÛübýÈÈÇbý˜ÈÇbbýÈÈbbýØÈb"ýÈÈDÛb"ýÈÈDÛübýÍÈÇbý<>ÈÇbbýÍÈbbýÝÈb"ýÍÈDÛb"ýÍÈDÛüb}HÈÇb}ÈÇbb}HÈbb}XÈb"}HÈDÛb"}HÈDÛüb}MÈÇb}ÈÇbb}MÈbb}]Èb"}MÈDÛb"}MÈDÛüb}ÈÈÇb}˜ÈÇbb}ÈÈbb}ØÈb"}ÈÈDÛb"}ÈÈDÛüb}ÍÈÇb}<7D>ÈÇbb}ÍÈbb}ÝÈb"}ÍÈDÛb"}ÍÈDÛübýHÊÇbýÊÇbbýHÊbbýXÊb"ýHÊDÛb"ýHÊDÛübýMÊÇbýÊÇbbýMÊbbý]Êb"ýMÊDÛb"ýMÊDÛübýÈÊÇbý˜ÊÇbbýÈÊbbýØÊb"ýÈÊDÛb"ýÈÊDÛübýÍÊÇbý<>ÊÇbbýÍÊbbýÝÊb"ýÍÊDÛb"ýÍÊDÛüb}HÊÇb}ÊÇbb}HÊbb}XÊb"}HÊDÛb"}HÊDÛüb}MÊÇb}ÊÇbb}MÊbb}]Êb"}MÊDÛb"}MÊDÛüb}ÈÊÇb}˜ÊÇbb}ÈÊbb}ØÊb"}ÈÊDÛb"}ÈÊDÛüb}ÍÊÇb}<7D>ÊÇbb}ÍÊbb}ÝÊb"}ÍÊDÛb"}ÍÊDÛübòÅËÐbòÅËÐbòÅËb²ÅËTÛ b²ÅËTÛàbòÅ ËÐbòÅËÐbòÅ Ëb²Å ËTÛ b²Å ËTÛàbòňËÐbòŘËÐbòňËb²ÅˆËTÛ b²ÅˆËTÛàbòÅ<EFBFBD>ËÐbòÅ<EFBFBD>ËÐbòÅ<EFBFBD>Ëb²Å<C2B2>ËTÛ b²Å<C2B2>ËTÛàbòEËÐbòEËÐbòEËb²EËTÛ@b²EËTÛÀbòE ËÐbòEËÐbòE Ëb²E ËTÛ@b²E ËTÛÀbòEˆËÐbòE˜ËÐbòEˆËb²EˆËTÛ@b²EˆËTÛÀbòE<EFBFBD>ËÐbòE<EFBFBD>ËÐbòE<EFBFBD>Ëb²E<C2B2>ËTÛ@b²E<C2B2>ËTÛÀbýHÌÇbýÌÇbbýHÌbbýXÌb"ýHÌDÛb"ýHÌDÛübýMÌÇbýÌÇbbýMÌbbý]Ìb"ýMÌDÛb"ýMÌDÛübýÈÌÇbý˜ÌÇbbýÈÌbbýØÌb"ýÈÌDÛb"ýÈÌDÛübýÍÌÇbý<>ÌÇbbýÍÌbbýÝÌb"ýÍÌDÛb"ýÍÌDÛüb}HÌÇb}ÌÇbb}HÌbb}XÌb"}HÌDÛb"}HÌDÛüb}MÌÇb}ÌÇbb}MÌbb}]Ìb"}MÌDÛb"}MÌDÛüb}ÈÌÇb}˜ÌÇbb}ÈÌbb}ØÌb"}ÈÌDÛb"}ÈÌDÛüb}ÍÌÇb}<7D>ÌÇbb}ÍÌbb}ÝÌb"}ÍÌDÛb"}ÍÌDÛübòÅÍÐbòÅÍÐbòÅÍb²ÅÍTÛ b²ÅÍTÛàbòÅ ÍÐbòÅÍÐbòÅ Íb²Å ÍTÛ b²Å ÈÈÇbý˜ÈÇbbýÈÈbbýØÈb"ýÈÈDÛb"ýÈÈDÛübýÍÈÇbý<>ÈÇbbýÍÈbbýÝÈb"ýÍÈDÛb"ýÍÈDÛüb}HÈÇb}ÈÇbb}HÈbb}XÈb"}HÈDÛb"}HÈDÛüb}MÈÇb}ÈÇbb}MÈbb}]Èb"}MÈDÛb"}MÈDÛüb}ÈÈÇb}˜ÈÇbb}ÈÈbb}ØÈb"}ÈÈDÛb"}ÈÈDÛüb}ÍÈÇb}<7D>ÈÇbb}ÍÈbb}ÝÈb"}ÍÈDÛb"}ÍÈDÛübýHÊÇbýÊÇbbýHÊbbýXÊb"ýHÊDÛb"ýHÊDÛübýMÊÇbýÊÇbbýMÊbbý]Êb"ýMÊDÛb"ýMÊDÛübýÈÊÇbý˜ÊÇbbýÈÊbbýØÊb"ýÈÊDÛb"ýÈÊDÛübýÍÊÇbý<>ÊÇbbýÍÊbbýÝÊb"ýÍÊDÛb"ýÍÊDÛüb}HÊÇb}ÊÇbb}HÊbb}XÊb"}HÊDÛb"}HÊDÛüb}MÊÇb}ÊÇbb}MÊbb}]Êb"}MÊDÛb"}MÊDÛüb}ÈÊÇb}˜ÊÇbb}ÈÊbb}ØÊb"}ÈÊDÛb"}ÈÊDÛüb}ÍÊÇb}<7D>ÊÇbb}ÍÊbb}ÝÊb"}ÍÊDÛb"}ÍÊDÛübòÅËÐbòÅËÐbòÅËb²ÅËTÛ b²ÅËTÛàbòÅ Ëb²Å ÍÐbòEÍÐbòE Íb²E ÍTÛ@b²E ÍTÛÀbòEˆÍÐbòE˜ÍÐbòEˆÍb²EˆÍTÛ@b²EˆÍTÛÀbòE<EFBFBD>ÍÐbòE<EFBFBD>ÍÐbòE<EFBFBD>Íb²E<C2B2>ÍTÛ@b²E<C2B2>ÍTÛÀ
býHÈÇbýÈÇbbýHÈbbýXÈb"ýHÈDÛb"ýHÈDÛübýMÈÇbýÈÇbbýMÈbbý]Èb"ýMÈDÛb"ýMÈDÛübýÈÈÇbý˜ÈÇbbýÈÈbbýØÈb"ýÈÈDÛb"ýÈÈDÛübýÍÈÇbý<>ÈÇbbýÍÈbbýÝÈb"ýÍÈDÛb"ýÍÈDÛüb}HÈÇb}ÈÇbb}HÈbb}XÈb"}HÈDÛb"}HÈDÛüb}MÈÇb}ÈÇbb}MÈbb}]Èb"}MÈDÛb"}MÈDÛüb}ÈÈÇb}˜ÈÇbb}ÈÈbb}ØÈb"}ÈÈDÛb"}ÈÈDÛüb}ÍÈÇb}<7D>ÈÇbb}ÍÈbb}ÝÈb"}ÍÈDÛb"}ÍÈDÛübýHÊÇbýÊÇbbýHÊbbýXÊb"ýHÊDÛb"ýHÊDÛübýMÊÇbýÊÇbbýMÊbbý]Êb"ýMÊDÛb"ýMÊDÛübýÈÊÇbý˜ÊÇbbýÈÊbbýØÊb"ýÈÊDÛb"ýÈÊDÛübýÍÊÇbý<>ÊÇbbýÍÊbbýÝÊb"ýÍÊDÛb"ýÍÊDÛüb}HÊÇb}ÊÇbb}HÊbb}XÊb"}HÊDÛb"}HÊDÛüb}MÊÇb}ÊÇbb}MÊbb}]Êb"}MÊDÛb"}MÊDÛüb}ÈÊÇb}˜ÊÇbb}ÈÊbb}ØÊb"}ÈÊDÛb"}ÈÊDÛüb}ÍÊÇb}<7D>ÊÇbb}ÍÊbb}ÝÊb"}ÍÊDÛb"}ÍÊDÛübòÅËÐbòÅËÐbòÅËb²ÅËTÛ b²ÅËTÛàbòÅ ËTÛ@b²E ËÐbòÅËÐbòÅ Ëb²Å ËTÛ b²Å ËTÛàbòÅ<C3B2>ËÐbòÅ<C3B2>ËÐbòÅ<C3B2>Ëb²Å<C2B2>ËTÛ b²Å<C2B2>ËTÛàbòEËÐbòEËÐbòEËb²EËTÛ@b²EËTÛÀbòE ËÐbòEËÐbòE Ëb²E ËTÛ@b²E ËTÛÀbòE<C3B2>ËÐbòE<C3B2>ËÐbòE<C3B2>Ëb²E<C2B2>ËTÛ@b²E<C2B2>ËTÛÀbýHÌÇbýÌÇbbýHÌbbýXÌb"ýHÌDÛb"ýHÌDÛübýMÌÇbýÌÇbbýMÌbbý]Ìb"ýMÌDÛb"ýMÌDÛübýÍÌÇbý<>ÌÇbbýÍÌbbýÝÌb"ýÍÌDÛb"ýÍÌDÛüb}HÌÇb}ÌÇbb}HÌbb}XÌb"}HÌDÛb"}HÌDÛüb}MÌÇb}ÌÇbb}MÌbb}]Ìb"}MÌDÛb"}MÌDÛüb}ÍÌÇb}<7D>ÌÇbb}ÍÌbb}ÝÌb"}ÍÌDÛb"}ÍÌDÛübòÅÍÐbòÅÍÐbòÅÍb²ÅÍTÛ b²ÅÍTÛàbòÅ ÍÐbòÅÍÐbòÅ Íb²Å ÍTÛ b²Å ËÐbòÅËÐbòÅ ÈÈÇbý˜ÈÇbbýÈÈbbýØÈb"ýÈÈDÛb"ýÈÈDÛübýÍÈÇbý<>ÈÇbbýÍÈbbýÝÈb"ýÍÈDÛb"ýÍÈDÛüb}HÈÇb}ÈÇbb}HÈbb}XÈb"}HÈDÛb"}HÈDÛüb}MÈÇb}ÈÇbb}MÈbb}]Èb"}MÈDÛb"}MÈDÛüb}ÈÈÇb}˜ÈÇbb}ÈÈbb}ØÈb"}ÈÈDÛb"}ÈÈDÛüb}ÍÈÇb}<7D>ÈÇbb}ÍÈbb}ÝÈb"}ÍÈDÛb"}ÍÈDÛübýHÊÇbýÊÇbbýHÊbbýXÊb"ýHÊDÛb"ýHÊDÛübýMÊÇbýÊÇbbýMÊbbý]Êb"ýMÊDÛb"ýMÊDÛübýÈÊÇbý˜ÊÇbbýÈÊbbýØÊb"ýÈÊDÛb"ýÈÊDÛübýÍÊÇbý<>ÊÇbbýÍÊbbýÝÊb"ýÍÊDÛb"ýÍÊDÛüb}HÊÇb}ÊÇbb}HÊbb}XÊb"}HÊDÛb"}HÊDÛüb}MÊÇb}ÊÇbb}MÊbb}]Êb"}MÊDÛb"}MÊDÛüb}ÈÊÇb}˜ÊÇbb}ÈÊbb}ØÊb"}ÈÊDÛb"}ÈÊDÛüb}ÍÊÇb}<7D>ÊÇbb}ÍÊbb}ÝÊb"}ÍÊDÛb"}ÍÊDÛübòÅËÐbòÅËÐbòÅËb²ÅËTÛ b²ÅËTÛàbòÅ ÍÐbòEÍÐbòE Íb²E ÍTÛ@b²E ÍTÛÀbòE<C3B2>ÍÐbòE<C3B2>ÍÐbòE<C3B2>Íb²E<C2B2>ÍTÛ@b²E<C2B2>ÍTÛÀ

56
bddisasm_test/avx512/avx512er_64.asm
View File

@ -12,12 +12,6 @@
vexp2pd zmm24{k5}, [rbx]{1to8}
vexp2pd zmm24{k5}, [rbx+r11*8+256]
vexp2pd zmm24{k5}, [rbx+r11*8-256]
vexp2pd zmm24{z}, zmm31
vexp2pd zmm24{z}, zmm31, {sae}
vexp2pd zmm24{z}, [rbx]
vexp2pd zmm24{z}, [rbx]{1to8}
vexp2pd zmm24{z}, [rbx+r11*8+256]
vexp2pd zmm24{z}, [rbx+r11*8-256]
vexp2pd zmm24{k5}{z}, zmm31
vexp2pd zmm24{k5}{z}, zmm31, {sae}
vexp2pd zmm24{k5}{z}, [rbx]
@ -36,12 +30,6 @@
vexp2ps zmm24{k5}, [rbx]{1to16}
vexp2ps zmm24{k5}, [rbx+r11*8+256]
vexp2ps zmm24{k5}, [rbx+r11*8-256]
vexp2ps zmm24{z}, zmm31
vexp2ps zmm24{z}, zmm31, {sae}
vexp2ps zmm24{z}, [rbx]
vexp2ps zmm24{z}, [rbx]{1to16}
vexp2ps zmm24{z}, [rbx+r11*8+256]
vexp2ps zmm24{z}, [rbx+r11*8-256]
vexp2ps zmm24{k5}{z}, zmm31
vexp2ps zmm24{k5}{z}, zmm31, {sae}
vexp2ps zmm24{k5}{z}, [rbx]
@ -60,12 +48,6 @@
vrcp28pd zmm24{k5}, [rbx]{1to8}
vrcp28pd zmm24{k5}, [rbx+r11*8+256]
vrcp28pd zmm24{k5}, [rbx+r11*8-256]
vrcp28pd zmm24{z}, zmm31
vrcp28pd zmm24{z}, zmm31, {sae}
vrcp28pd zmm24{z}, [rbx]
vrcp28pd zmm24{z}, [rbx]{1to8}
vrcp28pd zmm24{z}, [rbx+r11*8+256]
vrcp28pd zmm24{z}, [rbx+r11*8-256]
vrcp28pd zmm24{k5}{z}, zmm31
vrcp28pd zmm24{k5}{z}, zmm31, {sae}
vrcp28pd zmm24{k5}{z}, [rbx]
@ -84,12 +66,6 @@
vrcp28ps zmm24{k5}, [rbx]{1to16}
vrcp28ps zmm24{k5}, [rbx+r11*8+256]
vrcp28ps zmm24{k5}, [rbx+r11*8-256]
vrcp28ps zmm24{z}, zmm31
vrcp28ps zmm24{z}, zmm31, {sae}
vrcp28ps zmm24{z}, [rbx]
vrcp28ps zmm24{z}, [rbx]{1to16}
vrcp28ps zmm24{z}, [rbx+r11*8+256]
vrcp28ps zmm24{z}, [rbx+r11*8-256]
vrcp28ps zmm24{k5}{z}, zmm31
vrcp28ps zmm24{k5}{z}, zmm31, {sae}
vrcp28ps zmm24{k5}{z}, [rbx]
@ -106,11 +82,6 @@
vrcp28sd xmm2{k5}, xmm7, [rbx]
vrcp28sd xmm2{k5}, xmm7, [rbx+r11*8+256]
vrcp28sd xmm2{k5}, xmm7, [rbx+r11*8-256]
vrcp28sd xmm2{z}, xmm7, xmm0
vrcp28sd xmm2{z}, xmm7, xmm0, {sae}
vrcp28sd xmm2{z}, xmm7, [rbx]
vrcp28sd xmm2{z}, xmm7, [rbx+r11*8+256]
vrcp28sd xmm2{z}, xmm7, [rbx+r11*8-256]
vrcp28sd xmm2{k5}{z}, xmm7, xmm0
vrcp28sd xmm2{k5}{z}, xmm7, xmm0, {sae}
vrcp28sd xmm2{k5}{z}, xmm7, [rbx]
@ -126,11 +97,6 @@
vrcp28ss xmm2{k5}, xmm7, [rbx]
vrcp28ss xmm2{k5}, xmm7, [rbx+r11*8+256]
vrcp28ss xmm2{k5}, xmm7, [rbx+r11*8-256]
vrcp28ss xmm2{z}, xmm7, xmm0
vrcp28ss xmm2{z}, xmm7, xmm0, {sae}
vrcp28ss xmm2{z}, xmm7, [rbx]
vrcp28ss xmm2{z}, xmm7, [rbx+r11*8+256]
vrcp28ss xmm2{z}, xmm7, [rbx+r11*8-256]
vrcp28ss xmm2{k5}{z}, xmm7, xmm0
vrcp28ss xmm2{k5}{z}, xmm7, xmm0, {sae}
vrcp28ss xmm2{k5}{z}, xmm7, [rbx]
@ -148,12 +114,6 @@
vrsqrt28pd zmm24{k5}, [rbx]{1to8}
vrsqrt28pd zmm24{k5}, [rbx+r11*8+256]
vrsqrt28pd zmm24{k5}, [rbx+r11*8-256]
vrsqrt28pd zmm24{z}, zmm31
vrsqrt28pd zmm24{z}, zmm31, {sae}
vrsqrt28pd zmm24{z}, [rbx]
vrsqrt28pd zmm24{z}, [rbx]{1to8}
vrsqrt28pd zmm24{z}, [rbx+r11*8+256]
vrsqrt28pd zmm24{z}, [rbx+r11*8-256]
vrsqrt28pd zmm24{k5}{z}, zmm31
vrsqrt28pd zmm24{k5}{z}, zmm31, {sae}
vrsqrt28pd zmm24{k5}{z}, [rbx]
@ -172,12 +132,6 @@
vrsqrt28ps zmm24{k5}, [rbx]{1to16}
vrsqrt28ps zmm24{k5}, [rbx+r11*8+256]
vrsqrt28ps zmm24{k5}, [rbx+r11*8-256]
vrsqrt28ps zmm24{z}, zmm31
vrsqrt28ps zmm24{z}, zmm31, {sae}
vrsqrt28ps zmm24{z}, [rbx]
vrsqrt28ps zmm24{z}, [rbx]{1to16}
vrsqrt28ps zmm24{z}, [rbx+r11*8+256]
vrsqrt28ps zmm24{z}, [rbx+r11*8-256]
vrsqrt28ps zmm24{k5}{z}, zmm31
vrsqrt28ps zmm24{k5}{z}, zmm31, {sae}
vrsqrt28ps zmm24{k5}{z}, [rbx]
@ -194,11 +148,6 @@
vrsqrt28sd xmm2{k5}, xmm7, [rbx]
vrsqrt28sd xmm2{k5}, xmm7, [rbx+r11*8+256]
vrsqrt28sd xmm2{k5}, xmm7, [rbx+r11*8-256]
vrsqrt28sd xmm2{z}, xmm7, xmm0
vrsqrt28sd xmm2{z}, xmm7, xmm0, {sae}
vrsqrt28sd xmm2{z}, xmm7, [rbx]
vrsqrt28sd xmm2{z}, xmm7, [rbx+r11*8+256]
vrsqrt28sd xmm2{z}, xmm7, [rbx+r11*8-256]
vrsqrt28sd xmm2{k5}{z}, xmm7, xmm0
vrsqrt28sd xmm2{k5}{z}, xmm7, xmm0, {sae}
vrsqrt28sd xmm2{k5}{z}, xmm7, [rbx]
@ -214,11 +163,6 @@
vrsqrt28ss xmm2{k5}, xmm7, [rbx]
vrsqrt28ss xmm2{k5}, xmm7, [rbx+r11*8+256]
vrsqrt28ss xmm2{k5}, xmm7, [rbx+r11*8-256]
vrsqrt28ss xmm2{z}, xmm7, xmm0
vrsqrt28ss xmm2{z}, xmm7, xmm0, {sae}
vrsqrt28ss xmm2{z}, xmm7, [rbx]
vrsqrt28ss xmm2{z}, xmm7, [rbx+r11*8+256]
vrsqrt28ss xmm2{z}, xmm7, [rbx+r11*8-256]
vrsqrt28ss xmm2{k5}{z}, xmm7, xmm0
vrsqrt28ss xmm2{k5}{z}, xmm7, xmm0, {sae}
vrsqrt28ss xmm2{k5}{z}, xmm7, [rbx]

1494
bddisasm_test/avx512/avx512er_64.result
View File

File diff suppressed because it is too large Load Diff

BIN
bddisasm_test/avx512/avx512f_64
View File

Binary file not shown.

3085
bddisasm_test/avx512/avx512f_64.asm
View File

File diff suppressed because it is too large Load Diff

87863
bddisasm_test/avx512/avx512f_64.result
View File

File diff suppressed because it is too large Load Diff

2
bddisasm_test/avx512/avx512fma_64
View File

@ -1 +1 @@
bòŵÐbòŵbòŵb²ÅµTÛb²ÅµTÛðbòÅ µÐbòÅ µbòŵb²Å µTÛb²Å µTÛðbòňµÐbòňµbòصb²ÅˆµTÛb²ÅˆµTÛðbòÅ<EFBFBD>µÐbòÅ<EFBFBD>µbòÅ<C3B2>µb²Å<C2B2>µTÛb²Å<C2B2>µTÛðb•(µÇbâ•(µbâ•8µb¢•(µDÛb¢•(µDÛøb•-µÇbâ•-µbâ•=µb¢•-µDÛb¢•-µDÛøb•¨µÇb╨µb╸µb¢•¨µDÛb¢•¨µDÛøb•­µÇbâ•­µb╽µb¢•­µDÛb¢•­µDÛøb½@µÇbb½@µbb½Pµb"½@µDÛb"½@µDÛüb½EµÇbb½Eµbb½Uµb"½EµDÛb"½EµDÛüb½ÀµÇbb½Àµbb½Ðµb"½ÀµDÛb"½ÀµDÛüb½ÅµÇbb½Åµbb½Õµb"½ÅµDÛb"½ÅµDÛübòÅ´ÐbòÅ´bòÅ´b²Å´TÛb²Å´TÛðbòÅ ´ÐbòÅ ´bòÅ´b²Å ´TÛb²Å ´TÛðbòň´Ðbòň´bòŘ´b²Åˆ´TÛb²Åˆ´TÛðbòÅ<EFBFBD>´ÐbòÅ<EFBFBD>´bòÅ<C3B2>´b²Å<C2B2>´TÛb²Å<C2B2>´TÛðb•(´Çbâ•(´bâ•8´b¢•(´DÛb¢•(´DÛøb•-´Çbâ•-´bâ•=´b¢•-´DÛb¢•-´DÛøb•¨´Çb╨´b╸´b¢•¨´DÛb¢•¨´DÛøb•­´Çbâ•­´b╽´b¢•­´DÛb¢•­´DÛøb½@´Çbb½@´bb½P´b"½@´DÛb"½@´DÛüb½E´Çbb½E´bb½U´b"½E´DÛb"½E´DÛüb½À´Çbb½À´bb½Ð´b"½À´DÛb"½À´DÛüb½Å´Çbb½Å´bb½Õ´b"½Å´DÛb"½Å´DÛü
bòŵÐbòŵbòŵb²ÅµTÛb²ÅµTÛðbòÅ µÐbòÅ µbòŵb²Å µTÛb²Å µTÛðbòÅ<C3B2>µÐbòÅ<C3B2>µbòÅ<C3B2>µb²Å<C2B2>µTÛb²Å<C2B2>µTÛðb•(µÇbâ•(µbâ•8µb¢•(µDÛb¢•(µDÛøb•-µÇbâ•-µbâ•=µb¢•-µDÛb¢•-µDÛøb•­µÇbâ•­µb╽µb¢•­µDÛb¢•­µDÛøb½@µÇbb½@µbb½Pµb"½@µDÛb"½@µDÛüb½EµÇbb½Eµbb½Uµb"½EµDÛb"½EµDÛüb½ÅµÇbb½Åµbb½Õµb"½ÅµDÛb"½ÅµDÛübòÅ´ÐbòÅ´bòÅ´b²Å´TÛb²Å´TÛðbòÅ ´ÐbòÅ ´bòÅ´b²Å ´TÛb²Å ´TÛðbòÅ<C3B2>´ÐbòÅ<C3B2>´bòÅ<C3B2>´b²Å<C2B2>´TÛb²Å<C2B2>´TÛðb•(´Çbâ•(´bâ•8´b¢•(´DÛb¢•(´DÛøb•-´Çbâ•-´bâ•=´b¢•-´DÛb¢•-´DÛøb•­´Çbâ•­´b╽´b¢•­´DÛb¢•­´DÛøb½@´Çbb½@´bb½P´b"½@´DÛb"½@´DÛüb½E´Çbb½E´bb½U´b"½E´DÛb"½E´DÛüb½Å´Çbb½Å´bb½Õ´b"½Å´DÛb"½Å´DÛü

30
bddisasm_test/avx512/avx512fma_64.asm
View File

@ -10,11 +10,6 @@
vpmadd52huq xmm2{k5}, xmm7, [rbx]{1to2}
vpmadd52huq xmm2{k5}, xmm7, [rbx+r11*8+256]
vpmadd52huq xmm2{k5}, xmm7, [rbx+r11*8-256]
vpmadd52huq xmm2{z}, xmm7, xmm0
vpmadd52huq xmm2{z}, xmm7, [rbx]
vpmadd52huq xmm2{z}, xmm7, [rbx]{1to2}
vpmadd52huq xmm2{z}, xmm7, [rbx+r11*8+256]
vpmadd52huq xmm2{z}, xmm7, [rbx+r11*8-256]
vpmadd52huq xmm2{k5}{z}, xmm7, xmm0
vpmadd52huq xmm2{k5}{z}, xmm7, [rbx]
vpmadd52huq xmm2{k5}{z}, xmm7, [rbx]{1to2}
@ -30,11 +25,6 @@
vpmadd52huq ymm16{k5}, ymm13, [rbx]{1to4}
vpmadd52huq ymm16{k5}, ymm13, [rbx+r11*8+256]
vpmadd52huq ymm16{k5}, ymm13, [rbx+r11*8-256]
vpmadd52huq ymm16{z}, ymm13, ymm15
vpmadd52huq ymm16{z}, ymm13, [rbx]
vpmadd52huq ymm16{z}, ymm13, [rbx]{1to4}
vpmadd52huq ymm16{z}, ymm13, [rbx+r11*8+256]
vpmadd52huq ymm16{z}, ymm13, [rbx+r11*8-256]
vpmadd52huq ymm16{k5}{z}, ymm13, ymm15
vpmadd52huq ymm16{k5}{z}, ymm13, [rbx]
vpmadd52huq ymm16{k5}{z}, ymm13, [rbx]{1to4}
@ -50,11 +40,6 @@
vpmadd52huq zmm24{k5}, zmm24, [rbx]{1to8}
vpmadd52huq zmm24{k5}, zmm24, [rbx+r11*8+256]
vpmadd52huq zmm24{k5}, zmm24, [rbx+r11*8-256]
vpmadd52huq zmm24{z}, zmm24, zmm31
vpmadd52huq zmm24{z}, zmm24, [rbx]
vpmadd52huq zmm24{z}, zmm24, [rbx]{1to8}
vpmadd52huq zmm24{z}, zmm24, [rbx+r11*8+256]
vpmadd52huq zmm24{z}, zmm24, [rbx+r11*8-256]
vpmadd52huq zmm24{k5}{z}, zmm24, zmm31
vpmadd52huq zmm24{k5}{z}, zmm24, [rbx]
vpmadd52huq zmm24{k5}{z}, zmm24, [rbx]{1to8}
@ -70,11 +55,6 @@
vpmadd52luq xmm2{k5}, xmm7, [rbx]{1to2}
vpmadd52luq xmm2{k5}, xmm7, [rbx+r11*8+256]
vpmadd52luq xmm2{k5}, xmm7, [rbx+r11*8-256]
vpmadd52luq xmm2{z}, xmm7, xmm0
vpmadd52luq xmm2{z}, xmm7, [rbx]
vpmadd52luq xmm2{z}, xmm7, [rbx]{1to2}
vpmadd52luq xmm2{z}, xmm7, [rbx+r11*8+256]
vpmadd52luq xmm2{z}, xmm7, [rbx+r11*8-256]
vpmadd52luq xmm2{k5}{z}, xmm7, xmm0
vpmadd52luq xmm2{k5}{z}, xmm7, [rbx]
vpmadd52luq xmm2{k5}{z}, xmm7, [rbx]{1to2}
@ -90,11 +70,6 @@
vpmadd52luq ymm16{k5}, ymm13, [rbx]{1to4}
vpmadd52luq ymm16{k5}, ymm13, [rbx+r11*8+256]
vpmadd52luq ymm16{k5}, ymm13, [rbx+r11*8-256]
vpmadd52luq ymm16{z}, ymm13, ymm15
vpmadd52luq ymm16{z}, ymm13, [rbx]
vpmadd52luq ymm16{z}, ymm13, [rbx]{1to4}
vpmadd52luq ymm16{z}, ymm13, [rbx+r11*8+256]
vpmadd52luq ymm16{z}, ymm13, [rbx+r11*8-256]
vpmadd52luq ymm16{k5}{z}, ymm13, ymm15
vpmadd52luq ymm16{k5}{z}, ymm13, [rbx]
vpmadd52luq ymm16{k5}{z}, ymm13, [rbx]{1to4}
@ -110,11 +85,6 @@
vpmadd52luq zmm24{k5}, zmm24, [rbx]{1to8}
vpmadd52luq zmm24{k5}, zmm24, [rbx+r11*8+256]
vpmadd52luq zmm24{k5}, zmm24, [rbx+r11*8-256]
vpmadd52luq zmm24{z}, zmm24, zmm31
vpmadd52luq zmm24{z}, zmm24, [rbx]
vpmadd52luq zmm24{z}, zmm24, [rbx]{1to8}
vpmadd52luq zmm24{z}, zmm24, [rbx+r11*8+256]
vpmadd52luq zmm24{z}, zmm24, [rbx+r11*8-256]
vpmadd52luq zmm24{k5}{z}, zmm24, zmm31
vpmadd52luq zmm24{k5}{z}, zmm24, [rbx]
vpmadd52luq zmm24{k5}{z}, zmm24, [rbx]{1to8}

820
bddisasm_test/avx512/avx512fma_64.result
View File

File diff suppressed because it is too large Load Diff

121
bddisasm_test/avx512/avx512fp16_32 Normal file
View File

File diff suppressed because one or more lines are too long

236064
bddisasm_test/avx512/avx512fp16_32.result Normal file
View File

File diff suppressed because it is too large Load Diff

121
bddisasm_test/avx512/avx512fp16_64 Normal file
View File

File diff suppressed because one or more lines are too long

236064
bddisasm_test/avx512/avx512fp16_64.result Normal file
View File

File diff suppressed because it is too large Load Diff

2
bddisasm_test/avx512/avx512vbmi_64
View File

File diff suppressed because one or more lines are too long

225
bddisasm_test/avx512/avx512vbmi_64.asm
View File

@ -32,10 +32,6 @@
vpermb xmm2{k5}, xmm7, [rbx]
vpermb xmm2{k5}, xmm7, [rbx+r11*8+256]
vpermb xmm2{k5}, xmm7, [rbx+r11*8-256]
vpermb xmm2{z}, xmm7, xmm0
vpermb xmm2{z}, xmm7, [rbx]
vpermb xmm2{z}, xmm7, [rbx+r11*8+256]
vpermb xmm2{z}, xmm7, [rbx+r11*8-256]
vpermb xmm2{k5}{z}, xmm7, xmm0
vpermb xmm2{k5}{z}, xmm7, [rbx]
vpermb xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
@ -48,10 +44,6 @@
vpermb ymm16{k5}, ymm13, [rbx]
vpermb ymm16{k5}, ymm13, [rbx+r11*8+256]
vpermb ymm16{k5}, ymm13, [rbx+r11*8-256]
vpermb ymm16{z}, ymm13, ymm15
vpermb ymm16{z}, ymm13, [rbx]
vpermb ymm16{z}, ymm13, [rbx+r11*8+256]
vpermb ymm16{z}, ymm13, [rbx+r11*8-256]
vpermb ymm16{k5}{z}, ymm13, ymm15
vpermb ymm16{k5}{z}, ymm13, [rbx]
vpermb ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
@ -64,10 +56,6 @@
vpermb zmm24{k5}, zmm24, [rbx]
vpermb zmm24{k5}, zmm24, [rbx+r11*8+256]
vpermb zmm24{k5}, zmm24, [rbx+r11*8-256]
vpermb zmm24{z}, zmm24, zmm31
vpermb zmm24{z}, zmm24, [rbx]
vpermb zmm24{z}, zmm24, [rbx+r11*8+256]
vpermb zmm24{z}, zmm24, [rbx+r11*8-256]
vpermb zmm24{k5}{z}, zmm24, zmm31
vpermb zmm24{k5}{z}, zmm24, [rbx]
vpermb zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
@ -80,10 +68,6 @@
vpermi2b xmm2{k5}, xmm7, [rbx]
vpermi2b xmm2{k5}, xmm7, [rbx+r11*8+256]
vpermi2b xmm2{k5}, xmm7, [rbx+r11*8-256]
vpermi2b xmm2{z}, xmm7, xmm0
vpermi2b xmm2{z}, xmm7, [rbx]
vpermi2b xmm2{z}, xmm7, [rbx+r11*8+256]
vpermi2b xmm2{z}, xmm7, [rbx+r11*8-256]
vpermi2b xmm2{k5}{z}, xmm7, xmm0
vpermi2b xmm2{k5}{z}, xmm7, [rbx]
vpermi2b xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
@ -96,10 +80,6 @@
vpermi2b ymm16{k5}, ymm13, [rbx]
vpermi2b ymm16{k5}, ymm13, [rbx+r11*8+256]
vpermi2b ymm16{k5}, ymm13, [rbx+r11*8-256]
vpermi2b ymm16{z}, ymm13, ymm15
vpermi2b ymm16{z}, ymm13, [rbx]
vpermi2b ymm16{z}, ymm13, [rbx+r11*8+256]
vpermi2b ymm16{z}, ymm13, [rbx+r11*8-256]
vpermi2b ymm16{k5}{z}, ymm13, ymm15
vpermi2b ymm16{k5}{z}, ymm13, [rbx]
vpermi2b ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
@ -112,10 +92,6 @@
vpermi2b zmm24{k5}, zmm24, [rbx]
vpermi2b zmm24{k5}, zmm24, [rbx+r11*8+256]
vpermi2b zmm24{k5}, zmm24, [rbx+r11*8-256]
vpermi2b zmm24{z}, zmm24, zmm31
vpermi2b zmm24{z}, zmm24, [rbx]
vpermi2b zmm24{z}, zmm24, [rbx+r11*8+256]
vpermi2b zmm24{z}, zmm24, [rbx+r11*8-256]
vpermi2b zmm24{k5}{z}, zmm24, zmm31
vpermi2b zmm24{k5}{z}, zmm24, [rbx]
vpermi2b zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
@ -128,10 +104,6 @@
vpermt2b xmm2{k5}, xmm7, [rbx]
vpermt2b xmm2{k5}, xmm7, [rbx+r11*8+256]
vpermt2b xmm2{k5}, xmm7, [rbx+r11*8-256]
vpermt2b xmm2{z}, xmm7, xmm0
vpermt2b xmm2{z}, xmm7, [rbx]
vpermt2b xmm2{z}, xmm7, [rbx+r11*8+256]
vpermt2b xmm2{z}, xmm7, [rbx+r11*8-256]
vpermt2b xmm2{k5}{z}, xmm7, xmm0
vpermt2b xmm2{k5}{z}, xmm7, [rbx]
vpermt2b xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
@ -144,10 +116,6 @@
vpermt2b ymm16{k5}, ymm13, [rbx]
vpermt2b ymm16{k5}, ymm13, [rbx+r11*8+256]
vpermt2b ymm16{k5}, ymm13, [rbx+r11*8-256]
vpermt2b ymm16{z}, ymm13, ymm15
vpermt2b ymm16{z}, ymm13, [rbx]
vpermt2b ymm16{z}, ymm13, [rbx+r11*8+256]
vpermt2b ymm16{z}, ymm13, [rbx+r11*8-256]
vpermt2b ymm16{k5}{z}, ymm13, ymm15
vpermt2b ymm16{k5}{z}, ymm13, [rbx]
vpermt2b ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
@ -160,37 +128,27 @@
vpermt2b zmm24{k5}, zmm24, [rbx]
vpermt2b zmm24{k5}, zmm24, [rbx+r11*8+256]
vpermt2b zmm24{k5}, zmm24, [rbx+r11*8-256]
vpermt2b zmm24{z}, zmm24, zmm31
vpermt2b zmm24{z}, zmm24, [rbx]
vpermt2b zmm24{z}, zmm24, [rbx+r11*8+256]
vpermt2b zmm24{z}, zmm24, [rbx+r11*8-256]
vpermt2b zmm24{k5}{z}, zmm24, zmm31
vpermt2b zmm24{k5}{z}, zmm24, [rbx]
vpermt2b zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
vpermt2b zmm24{k5}{z}, zmm24, [rbx+r11*8-256]
vpexpandb xmm2, xmm0
vpexpandb xmm2{k5}, xmm0
vpexpandb xmm2{z}, xmm0
vpexpandb xmm2{k5}{z}, xmm0
vpexpandb ymm16, ymm15
vpexpandb ymm16{k5}, ymm15
vpexpandb ymm16{z}, ymm15
vpexpandb ymm16{k5}{z}, ymm15
vpexpandb zmm24, zmm31
vpexpandb zmm24{k5}, zmm31
vpexpandb zmm24{z}, zmm31
vpexpandb zmm24{k5}{z}, zmm31
vpexpandw xmm2, xmm0
vpexpandw xmm2{k5}, xmm0
vpexpandw xmm2{z}, xmm0
vpexpandw xmm2{k5}{z}, xmm0
vpexpandw ymm16, ymm15
vpexpandw ymm16{k5}, ymm15
vpexpandw ymm16{z}, ymm15
vpexpandw ymm16{k5}{z}, ymm15
vpexpandw zmm24, zmm31
vpexpandw zmm24{k5}, zmm31
vpexpandw zmm24{z}, zmm31
vpexpandw zmm24{k5}{z}, zmm31
vpmultishiftqb xmm2, xmm7, xmm0
vpmultishiftqb xmm2, xmm7, [rbx]
@ -202,11 +160,6 @@
vpmultishiftqb xmm2{k5}, xmm7, [rbx]{1to2}
vpmultishiftqb xmm2{k5}, xmm7, [rbx+r11*8+256]
vpmultishiftqb xmm2{k5}, xmm7, [rbx+r11*8-256]
vpmultishiftqb xmm2{z}, xmm7, xmm0
vpmultishiftqb xmm2{z}, xmm7, [rbx]
vpmultishiftqb xmm2{z}, xmm7, [rbx]{1to2}
vpmultishiftqb xmm2{z}, xmm7, [rbx+r11*8+256]
vpmultishiftqb xmm2{z}, xmm7, [rbx+r11*8-256]
vpmultishiftqb xmm2{k5}{z}, xmm7, xmm0
vpmultishiftqb xmm2{k5}{z}, xmm7, [rbx]
vpmultishiftqb xmm2{k5}{z}, xmm7, [rbx]{1to2}
@ -222,11 +175,6 @@
vpmultishiftqb ymm16{k5}, ymm13, [rbx]{1to4}
vpmultishiftqb ymm16{k5}, ymm13, [rbx+r11*8+256]
vpmultishiftqb ymm16{k5}, ymm13, [rbx+r11*8-256]
vpmultishiftqb ymm16{z}, ymm13, ymm15
vpmultishiftqb ymm16{z}, ymm13, [rbx]
vpmultishiftqb ymm16{z}, ymm13, [rbx]{1to4}
vpmultishiftqb ymm16{z}, ymm13, [rbx+r11*8+256]
vpmultishiftqb ymm16{z}, ymm13, [rbx+r11*8-256]
vpmultishiftqb ymm16{k5}{z}, ymm13, ymm15
vpmultishiftqb ymm16{k5}{z}, ymm13, [rbx]
vpmultishiftqb ymm16{k5}{z}, ymm13, [rbx]{1to4}
@ -242,11 +190,6 @@
vpmultishiftqb zmm24{k5}, zmm24, [rbx]{1to8}
vpmultishiftqb zmm24{k5}, zmm24, [rbx+r11*8+256]
vpmultishiftqb zmm24{k5}, zmm24, [rbx+r11*8-256]
vpmultishiftqb zmm24{z}, zmm24, zmm31
vpmultishiftqb zmm24{z}, zmm24, [rbx]
vpmultishiftqb zmm24{z}, zmm24, [rbx]{1to8}
vpmultishiftqb zmm24{z}, zmm24, [rbx+r11*8+256]
vpmultishiftqb zmm24{z}, zmm24, [rbx+r11*8-256]
vpmultishiftqb zmm24{k5}{z}, zmm24, zmm31
vpmultishiftqb zmm24{k5}{z}, zmm24, [rbx]
vpmultishiftqb zmm24{k5}{z}, zmm24, [rbx]{1to8}
@ -262,11 +205,6 @@
vpshldd xmm2{k5}, xmm7, [rbx]{1to4}, 0x90
vpshldd xmm2{k5}, xmm7, [rbx+r11*8+256], 0x90
vpshldd xmm2{k5}, xmm7, [rbx+r11*8-256], 0x90
vpshldd xmm2{z}, xmm7, xmm0, 0x90
vpshldd xmm2{z}, xmm7, [rbx], 0x90
vpshldd xmm2{z}, xmm7, [rbx]{1to4}, 0x90
vpshldd xmm2{z}, xmm7, [rbx+r11*8+256], 0x90
vpshldd xmm2{z}, xmm7, [rbx+r11*8-256], 0x90
vpshldd xmm2{k5}{z}, xmm7, xmm0, 0x90
vpshldd xmm2{k5}{z}, xmm7, [rbx], 0x90
vpshldd xmm2{k5}{z}, xmm7, [rbx]{1to4}, 0x90
@ -282,11 +220,6 @@
vpshldd ymm16{k5}, ymm13, [rbx]{1to8}, 0x90
vpshldd ymm16{k5}, ymm13, [rbx+r11*8+256], 0x90
vpshldd ymm16{k5}, ymm13, [rbx+r11*8-256], 0x90
vpshldd ymm16{z}, ymm13, ymm15, 0x90
vpshldd ymm16{z}, ymm13, [rbx], 0x90
vpshldd ymm16{z}, ymm13, [rbx]{1to8}, 0x90
vpshldd ymm16{z}, ymm13, [rbx+r11*8+256], 0x90
vpshldd ymm16{z}, ymm13, [rbx+r11*8-256], 0x90
vpshldd ymm16{k5}{z}, ymm13, ymm15, 0x90
vpshldd ymm16{k5}{z}, ymm13, [rbx], 0x90
vpshldd ymm16{k5}{z}, ymm13, [rbx]{1to8}, 0x90
@ -302,11 +235,6 @@
vpshldd zmm24{k5}, zmm24, [rbx]{1to16}, 0x90
vpshldd zmm24{k5}, zmm24, [rbx+r11*8+256], 0x90
vpshldd zmm24{k5}, zmm24, [rbx+r11*8-256], 0x90
vpshldd zmm24{z}, zmm24, zmm31, 0x90
vpshldd zmm24{z}, zmm24, [rbx], 0x90
vpshldd zmm24{z}, zmm24, [rbx]{1to16}, 0x90
vpshldd zmm24{z}, zmm24, [rbx+r11*8+256], 0x90
vpshldd zmm24{z}, zmm24, [rbx+r11*8-256], 0x90
vpshldd zmm24{k5}{z}, zmm24, zmm31, 0x90
vpshldd zmm24{k5}{z}, zmm24, [rbx], 0x90
vpshldd zmm24{k5}{z}, zmm24, [rbx]{1to16}, 0x90
@ -322,11 +250,6 @@
vpshldq xmm2{k5}, xmm7, [rbx]{1to2}, 0x90
vpshldq xmm2{k5}, xmm7, [rbx+r11*8+256], 0x90
vpshldq xmm2{k5}, xmm7, [rbx+r11*8-256], 0x90
vpshldq xmm2{z}, xmm7, xmm0, 0x90
vpshldq xmm2{z}, xmm7, [rbx], 0x90
vpshldq xmm2{z}, xmm7, [rbx]{1to2}, 0x90
vpshldq xmm2{z}, xmm7, [rbx+r11*8+256], 0x90
vpshldq xmm2{z}, xmm7, [rbx+r11*8-256], 0x90
vpshldq xmm2{k5}{z}, xmm7, xmm0, 0x90
vpshldq xmm2{k5}{z}, xmm7, [rbx], 0x90
vpshldq xmm2{k5}{z}, xmm7, [rbx]{1to2}, 0x90
@ -342,11 +265,6 @@
vpshldq ymm16{k5}, ymm13, [rbx]{1to4}, 0x90
vpshldq ymm16{k5}, ymm13, [rbx+r11*8+256], 0x90
vpshldq ymm16{k5}, ymm13, [rbx+r11*8-256], 0x90
vpshldq ymm16{z}, ymm13, ymm15, 0x90
vpshldq ymm16{z}, ymm13, [rbx], 0x90
vpshldq ymm16{z}, ymm13, [rbx]{1to4}, 0x90
vpshldq ymm16{z}, ymm13, [rbx+r11*8+256], 0x90
vpshldq ymm16{z}, ymm13, [rbx+r11*8-256], 0x90
vpshldq ymm16{k5}{z}, ymm13, ymm15, 0x90
vpshldq ymm16{k5}{z}, ymm13, [rbx], 0x90
vpshldq ymm16{k5}{z}, ymm13, [rbx]{1to4}, 0x90
@ -362,11 +280,6 @@
vpshldq zmm24{k5}, zmm24, [rbx]{1to8}, 0x90
vpshldq zmm24{k5}, zmm24, [rbx+r11*8+256], 0x90
vpshldq zmm24{k5}, zmm24, [rbx+r11*8-256], 0x90
vpshldq zmm24{z}, zmm24, zmm31, 0x90
vpshldq zmm24{z}, zmm24, [rbx], 0x90
vpshldq zmm24{z}, zmm24, [rbx]{1to8}, 0x90
vpshldq zmm24{z}, zmm24, [rbx+r11*8+256], 0x90
vpshldq zmm24{z}, zmm24, [rbx+r11*8-256], 0x90
vpshldq zmm24{k5}{z}, zmm24, zmm31, 0x90
vpshldq zmm24{k5}{z}, zmm24, [rbx], 0x90
vpshldq zmm24{k5}{z}, zmm24, [rbx]{1to8}, 0x90
@ -382,11 +295,6 @@
vpshldvd xmm2{k5}, xmm7, [rbx]{1to4}
vpshldvd xmm2{k5}, xmm7, [rbx+r11*8+256]
vpshldvd xmm2{k5}, xmm7, [rbx+r11*8-256]
vpshldvd xmm2{z}, xmm7, xmm0
vpshldvd xmm2{z}, xmm7, [rbx]
vpshldvd xmm2{z}, xmm7, [rbx]{1to4}
vpshldvd xmm2{z}, xmm7, [rbx+r11*8+256]
vpshldvd xmm2{z}, xmm7, [rbx+r11*8-256]
vpshldvd xmm2{k5}{z}, xmm7, xmm0
vpshldvd xmm2{k5}{z}, xmm7, [rbx]
vpshldvd xmm2{k5}{z}, xmm7, [rbx]{1to4}
@ -402,11 +310,6 @@
vpshldvd ymm16{k5}, ymm13, [rbx]{1to8}
vpshldvd ymm16{k5}, ymm13, [rbx+r11*8+256]
vpshldvd ymm16{k5}, ymm13, [rbx+r11*8-256]
vpshldvd ymm16{z}, ymm13, ymm15
vpshldvd ymm16{z}, ymm13, [rbx]
vpshldvd ymm16{z}, ymm13, [rbx]{1to8}
vpshldvd ymm16{z}, ymm13, [rbx+r11*8+256]
vpshldvd ymm16{z}, ymm13, [rbx+r11*8-256]
vpshldvd ymm16{k5}{z}, ymm13, ymm15
vpshldvd ymm16{k5}{z}, ymm13, [rbx]
vpshldvd ymm16{k5}{z}, ymm13, [rbx]{1to8}
@ -422,11 +325,6 @@
vpshldvd zmm24{k5}, zmm24, [rbx]{1to16}
vpshldvd zmm24{k5}, zmm24, [rbx+r11*8+256]
vpshldvd zmm24{k5}, zmm24, [rbx+r11*8-256]
vpshldvd zmm24{z}, zmm24, zmm31
vpshldvd zmm24{z}, zmm24, [rbx]
vpshldvd zmm24{z}, zmm24, [rbx]{1to16}
vpshldvd zmm24{z}, zmm24, [rbx+r11*8+256]
vpshldvd zmm24{z}, zmm24, [rbx+r11*8-256]
vpshldvd zmm24{k5}{z}, zmm24, zmm31
vpshldvd zmm24{k5}{z}, zmm24, [rbx]
vpshldvd zmm24{k5}{z}, zmm24, [rbx]{1to16}
@ -442,11 +340,6 @@
vpshldvq xmm2{k5}, xmm7, [rbx]{1to2}
vpshldvq xmm2{k5}, xmm7, [rbx+r11*8+256]
vpshldvq xmm2{k5}, xmm7, [rbx+r11*8-256]
vpshldvq xmm2{z}, xmm7, xmm0
vpshldvq xmm2{z}, xmm7, [rbx]
vpshldvq xmm2{z}, xmm7, [rbx]{1to2}
vpshldvq xmm2{z}, xmm7, [rbx+r11*8+256]
vpshldvq xmm2{z}, xmm7, [rbx+r11*8-256]
vpshldvq xmm2{k5}{z}, xmm7, xmm0
vpshldvq xmm2{k5}{z}, xmm7, [rbx]
vpshldvq xmm2{k5}{z}, xmm7, [rbx]{1to2}
@ -462,11 +355,6 @@
vpshldvq ymm16{k5}, ymm13, [rbx]{1to4}
vpshldvq ymm16{k5}, ymm13, [rbx+r11*8+256]
vpshldvq ymm16{k5}, ymm13, [rbx+r11*8-256]
vpshldvq ymm16{z}, ymm13, ymm15
vpshldvq ymm16{z}, ymm13, [rbx]
vpshldvq ymm16{z}, ymm13, [rbx]{1to4}
vpshldvq ymm16{z}, ymm13, [rbx+r11*8+256]
vpshldvq ymm16{z}, ymm13, [rbx+r11*8-256]
vpshldvq ymm16{k5}{z}, ymm13, ymm15
vpshldvq ymm16{k5}{z}, ymm13, [rbx]
vpshldvq ymm16{k5}{z}, ymm13, [rbx]{1to4}
@ -482,11 +370,6 @@
vpshldvq zmm24{k5}, zmm24, [rbx]{1to8}
vpshldvq zmm24{k5}, zmm24, [rbx+r11*8+256]
vpshldvq zmm24{k5}, zmm24, [rbx+r11*8-256]
vpshldvq zmm24{z}, zmm24, zmm31
vpshldvq zmm24{z}, zmm24, [rbx]
vpshldvq zmm24{z}, zmm24, [rbx]{1to8}
vpshldvq zmm24{z}, zmm24, [rbx+r11*8+256]
vpshldvq zmm24{z}, zmm24, [rbx+r11*8-256]
vpshldvq zmm24{k5}{z}, zmm24, zmm31
vpshldvq zmm24{k5}{z}, zmm24, [rbx]
vpshldvq zmm24{k5}{z}, zmm24, [rbx]{1to8}
@ -500,10 +383,6 @@
vpshldvw xmm2{k5}, xmm7, [rbx]
vpshldvw xmm2{k5}, xmm7, [rbx+r11*8+256]
vpshldvw xmm2{k5}, xmm7, [rbx+r11*8-256]
vpshldvw xmm2{z}, xmm7, xmm0
vpshldvw xmm2{z}, xmm7, [rbx]
vpshldvw xmm2{z}, xmm7, [rbx+r11*8+256]
vpshldvw xmm2{z}, xmm7, [rbx+r11*8-256]
vpshldvw xmm2{k5}{z}, xmm7, xmm0
vpshldvw xmm2{k5}{z}, xmm7, [rbx]
vpshldvw xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
@ -516,10 +395,6 @@
vpshldvw ymm16{k5}, ymm13, [rbx]
vpshldvw ymm16{k5}, ymm13, [rbx+r11*8+256]
vpshldvw ymm16{k5}, ymm13, [rbx+r11*8-256]
vpshldvw ymm16{z}, ymm13, ymm15
vpshldvw ymm16{z}, ymm13, [rbx]
vpshldvw ymm16{z}, ymm13, [rbx+r11*8+256]
vpshldvw ymm16{z}, ymm13, [rbx+r11*8-256]
vpshldvw ymm16{k5}{z}, ymm13, ymm15
vpshldvw ymm16{k5}{z}, ymm13, [rbx]
vpshldvw ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
@ -532,10 +407,6 @@
vpshldvw zmm24{k5}, zmm24, [rbx]
vpshldvw zmm24{k5}, zmm24, [rbx+r11*8+256]
vpshldvw zmm24{k5}, zmm24, [rbx+r11*8-256]
vpshldvw zmm24{z}, zmm24, zmm31
vpshldvw zmm24{z}, zmm24, [rbx]
vpshldvw zmm24{z}, zmm24, [rbx+r11*8+256]
vpshldvw zmm24{z}, zmm24, [rbx+r11*8-256]
vpshldvw zmm24{k5}{z}, zmm24, zmm31
vpshldvw zmm24{k5}{z}, zmm24, [rbx]
vpshldvw zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
@ -548,10 +419,6 @@
vpshldw xmm2{k5}, xmm7, [rbx], 0x90
vpshldw xmm2{k5}, xmm7, [rbx+r11*8+256], 0x90
vpshldw xmm2{k5}, xmm7, [rbx+r11*8-256], 0x90
vpshldw xmm2{z}, xmm7, xmm0, 0x90
vpshldw xmm2{z}, xmm7, [rbx], 0x90
vpshldw xmm2{z}, xmm7, [rbx+r11*8+256], 0x90
vpshldw xmm2{z}, xmm7, [rbx+r11*8-256], 0x90
vpshldw xmm2{k5}{z}, xmm7, xmm0, 0x90
vpshldw xmm2{k5}{z}, xmm7, [rbx], 0x90
vpshldw xmm2{k5}{z}, xmm7, [rbx+r11*8+256], 0x90
@ -564,10 +431,6 @@
vpshldw ymm16{k5}, ymm13, [rbx], 0x90
vpshldw ymm16{k5}, ymm13, [rbx+r11*8+256], 0x90
vpshldw ymm16{k5}, ymm13, [rbx+r11*8-256], 0x90
vpshldw ymm16{z}, ymm13, ymm15, 0x90
vpshldw ymm16{z}, ymm13, [rbx], 0x90
vpshldw ymm16{z}, ymm13, [rbx+r11*8+256], 0x90
vpshldw ymm16{z}, ymm13, [rbx+r11*8-256], 0x90
vpshldw ymm16{k5}{z}, ymm13, ymm15, 0x90
vpshldw ymm16{k5}{z}, ymm13, [rbx], 0x90
vpshldw ymm16{k5}{z}, ymm13, [rbx+r11*8+256], 0x90
@ -580,10 +443,6 @@
vpshldw zmm24{k5}, zmm24, [rbx], 0x90
vpshldw zmm24{k5}, zmm24, [rbx+r11*8+256], 0x90
vpshldw zmm24{k5}, zmm24, [rbx+r11*8-256], 0x90
vpshldw zmm24{z}, zmm24, zmm31, 0x90
vpshldw zmm24{z}, zmm24, [rbx], 0x90
vpshldw zmm24{z}, zmm24, [rbx+r11*8+256], 0x90
vpshldw zmm24{z}, zmm24, [rbx+r11*8-256], 0x90
vpshldw zmm24{k5}{z}, zmm24, zmm31, 0x90
vpshldw zmm24{k5}{z}, zmm24, [rbx], 0x90
vpshldw zmm24{k5}{z}, zmm24, [rbx+r11*8+256], 0x90
@ -598,11 +457,6 @@
vpshrdd xmm2{k5}, xmm7, [rbx]{1to4}, 0x90
vpshrdd xmm2{k5}, xmm7, [rbx+r11*8+256], 0x90
vpshrdd xmm2{k5}, xmm7, [rbx+r11*8-256], 0x90
vpshrdd xmm2{z}, xmm7, xmm0, 0x90
vpshrdd xmm2{z}, xmm7, [rbx], 0x90
vpshrdd xmm2{z}, xmm7, [rbx]{1to4}, 0x90
vpshrdd xmm2{z}, xmm7, [rbx+r11*8+256], 0x90
vpshrdd xmm2{z}, xmm7, [rbx+r11*8-256], 0x90
vpshrdd xmm2{k5}{z}, xmm7, xmm0, 0x90
vpshrdd xmm2{k5}{z}, xmm7, [rbx], 0x90
vpshrdd xmm2{k5}{z}, xmm7, [rbx]{1to4}, 0x90
@ -618,11 +472,6 @@
vpshrdd ymm16{k5}, ymm13, [rbx]{1to8}, 0x90
vpshrdd ymm16{k5}, ymm13, [rbx+r11*8+256], 0x90
vpshrdd ymm16{k5}, ymm13, [rbx+r11*8-256], 0x90
vpshrdd ymm16{z}, ymm13, ymm15, 0x90
vpshrdd ymm16{z}, ymm13, [rbx], 0x90
vpshrdd ymm16{z}, ymm13, [rbx]{1to8}, 0x90
vpshrdd ymm16{z}, ymm13, [rbx+r11*8+256], 0x90
vpshrdd ymm16{z}, ymm13, [rbx+r11*8-256], 0x90
vpshrdd ymm16{k5}{z}, ymm13, ymm15, 0x90
vpshrdd ymm16{k5}{z}, ymm13, [rbx], 0x90
vpshrdd ymm16{k5}{z}, ymm13, [rbx]{1to8}, 0x90
@ -638,11 +487,6 @@
vpshrdd zmm24{k5}, zmm24, [rbx]{1to16}, 0x90
vpshrdd zmm24{k5}, zmm24, [rbx+r11*8+256], 0x90
vpshrdd zmm24{k5}, zmm24, [rbx+r11*8-256], 0x90
vpshrdd zmm24{z}, zmm24, zmm31, 0x90
vpshrdd zmm24{z}, zmm24, [rbx], 0x90
vpshrdd zmm24{z}, zmm24, [rbx]{1to16}, 0x90
vpshrdd zmm24{z}, zmm24, [rbx+r11*8+256], 0x90
vpshrdd zmm24{z}, zmm24, [rbx+r11*8-256], 0x90
vpshrdd zmm24{k5}{z}, zmm24, zmm31, 0x90
vpshrdd zmm24{k5}{z}, zmm24, [rbx], 0x90
vpshrdd zmm24{k5}{z}, zmm24, [rbx]{1to16}, 0x90
@ -658,11 +502,6 @@
vpshrdq xmm2{k5}, xmm7, [rbx]{1to2}, 0x90
vpshrdq xmm2{k5}, xmm7, [rbx+r11*8+256], 0x90
vpshrdq xmm2{k5}, xmm7, [rbx+r11*8-256], 0x90
vpshrdq xmm2{z}, xmm7, xmm0, 0x90
vpshrdq xmm2{z}, xmm7, [rbx], 0x90
vpshrdq xmm2{z}, xmm7, [rbx]{1to2}, 0x90
vpshrdq xmm2{z}, xmm7, [rbx+r11*8+256], 0x90
vpshrdq xmm2{z}, xmm7, [rbx+r11*8-256], 0x90
vpshrdq xmm2{k5}{z}, xmm7, xmm0, 0x90
vpshrdq xmm2{k5}{z}, xmm7, [rbx], 0x90
vpshrdq xmm2{k5}{z}, xmm7, [rbx]{1to2}, 0x90
@ -678,11 +517,6 @@
vpshrdq ymm16{k5}, ymm13, [rbx]{1to4}, 0x90
vpshrdq ymm16{k5}, ymm13, [rbx+r11*8+256], 0x90
vpshrdq ymm16{k5}, ymm13, [rbx+r11*8-256], 0x90
vpshrdq ymm16{z}, ymm13, ymm15, 0x90
vpshrdq ymm16{z}, ymm13, [rbx], 0x90
vpshrdq ymm16{z}, ymm13, [rbx]{1to4}, 0x90
vpshrdq ymm16{z}, ymm13, [rbx+r11*8+256], 0x90
vpshrdq ymm16{z}, ymm13, [rbx+r11*8-256], 0x90
vpshrdq ymm16{k5}{z}, ymm13, ymm15, 0x90
vpshrdq ymm16{k5}{z}, ymm13, [rbx], 0x90
vpshrdq ymm16{k5}{z}, ymm13, [rbx]{1to4}, 0x90
@ -698,11 +532,6 @@
vpshrdq zmm24{k5}, zmm24, [rbx]{1to8}, 0x90
vpshrdq zmm24{k5}, zmm24, [rbx+r11*8+256], 0x90
vpshrdq zmm24{k5}, zmm24, [rbx+r11*8-256], 0x90
vpshrdq zmm24{z}, zmm24, zmm31, 0x90
vpshrdq zmm24{z}, zmm24, [rbx], 0x90
vpshrdq zmm24{z}, zmm24, [rbx]{1to8}, 0x90
vpshrdq zmm24{z}, zmm24, [rbx+r11*8+256], 0x90
vpshrdq zmm24{z}, zmm24, [rbx+r11*8-256], 0x90
vpshrdq zmm24{k5}{z}, zmm24, zmm31, 0x90
vpshrdq zmm24{k5}{z}, zmm24, [rbx], 0x90
vpshrdq zmm24{k5}{z}, zmm24, [rbx]{1to8}, 0x90
@ -718,11 +547,6 @@
vpshrdvd xmm2{k5}, xmm7, [rbx]{1to4}
vpshrdvd xmm2{k5}, xmm7, [rbx+r11*8+256]
vpshrdvd xmm2{k5}, xmm7, [rbx+r11*8-256]
vpshrdvd xmm2{z}, xmm7, xmm0
vpshrdvd xmm2{z}, xmm7, [rbx]
vpshrdvd xmm2{z}, xmm7, [rbx]{1to4}
vpshrdvd xmm2{z}, xmm7, [rbx+r11*8+256]
vpshrdvd xmm2{z}, xmm7, [rbx+r11*8-256]
vpshrdvd xmm2{k5}{z}, xmm7, xmm0
vpshrdvd xmm2{k5}{z}, xmm7, [rbx]
vpshrdvd xmm2{k5}{z}, xmm7, [rbx]{1to4}
@ -738,11 +562,6 @@
vpshrdvd ymm16{k5}, ymm13, [rbx]{1to8}
vpshrdvd ymm16{k5}, ymm13, [rbx+r11*8+256]
vpshrdvd ymm16{k5}, ymm13, [rbx+r11*8-256]
vpshrdvd ymm16{z}, ymm13, ymm15
vpshrdvd ymm16{z}, ymm13, [rbx]
vpshrdvd ymm16{z}, ymm13, [rbx]{1to8}
vpshrdvd ymm16{z}, ymm13, [rbx+r11*8+256]
vpshrdvd ymm16{z}, ymm13, [rbx+r11*8-256]
vpshrdvd ymm16{k5}{z}, ymm13, ymm15
vpshrdvd ymm16{k5}{z}, ymm13, [rbx]
vpshrdvd ymm16{k5}{z}, ymm13, [rbx]{1to8}
@ -758,11 +577,6 @@
vpshrdvd zmm24{k5}, zmm24, [rbx]{1to16}
vpshrdvd zmm24{k5}, zmm24, [rbx+r11*8+256]
vpshrdvd zmm24{k5}, zmm24, [rbx+r11*8-256]
vpshrdvd zmm24{z}, zmm24, zmm31
vpshrdvd zmm24{z}, zmm24, [rbx]
vpshrdvd zmm24{z}, zmm24, [rbx]{1to16}
vpshrdvd zmm24{z}, zmm24, [rbx+r11*8+256]
vpshrdvd zmm24{z}, zmm24, [rbx+r11*8-256]
vpshrdvd zmm24{k5}{z}, zmm24, zmm31
vpshrdvd zmm24{k5}{z}, zmm24, [rbx]
vpshrdvd zmm24{k5}{z}, zmm24, [rbx]{1to16}
@ -778,11 +592,6 @@
vpshrdvq xmm2{k5}, xmm7, [rbx]{1to2}
vpshrdvq xmm2{k5}, xmm7, [rbx+r11*8+256]
vpshrdvq xmm2{k5}, xmm7, [rbx+r11*8-256]
vpshrdvq xmm2{z}, xmm7, xmm0
vpshrdvq xmm2{z}, xmm7, [rbx]
vpshrdvq xmm2{z}, xmm7, [rbx]{1to2}
vpshrdvq xmm2{z}, xmm7, [rbx+r11*8+256]
vpshrdvq xmm2{z}, xmm7, [rbx+r11*8-256]
vpshrdvq xmm2{k5}{z}, xmm7, xmm0
vpshrdvq xmm2{k5}{z}, xmm7, [rbx]
vpshrdvq xmm2{k5}{z}, xmm7, [rbx]{1to2}
@ -798,11 +607,6 @@
vpshrdvq ymm16{k5}, ymm13, [rbx]{1to4}
vpshrdvq ymm16{k5}, ymm13, [rbx+r11*8+256]
vpshrdvq ymm16{k5}, ymm13, [rbx+r11*8-256]
vpshrdvq ymm16{z}, ymm13, ymm15
vpshrdvq ymm16{z}, ymm13, [rbx]
vpshrdvq ymm16{z}, ymm13, [rbx]{1to4}
vpshrdvq ymm16{z}, ymm13, [rbx+r11*8+256]
vpshrdvq ymm16{z}, ymm13, [rbx+r11*8-256]
vpshrdvq ymm16{k5}{z}, ymm13, ymm15
vpshrdvq ymm16{k5}{z}, ymm13, [rbx]
vpshrdvq ymm16{k5}{z}, ymm13, [rbx]{1to4}
@ -818,11 +622,6 @@
vpshrdvq zmm24{k5}, zmm24, [rbx]{1to8}
vpshrdvq zmm24{k5}, zmm24, [rbx+r11*8+256]
vpshrdvq zmm24{k5}, zmm24, [rbx+r11*8-256]
vpshrdvq zmm24{z}, zmm24, zmm31
vpshrdvq zmm24{z}, zmm24, [rbx]
vpshrdvq zmm24{z}, zmm24, [rbx]{1to8}
vpshrdvq zmm24{z}, zmm24, [rbx+r11*8+256]
vpshrdvq zmm24{z}, zmm24, [rbx+r11*8-256]
vpshrdvq zmm24{k5}{z}, zmm24, zmm31
vpshrdvq zmm24{k5}{z}, zmm24, [rbx]
vpshrdvq zmm24{k5}{z}, zmm24, [rbx]{1to8}
@ -836,10 +635,6 @@
vpshrdvw xmm2{k5}, xmm7, [rbx]
vpshrdvw xmm2{k5}, xmm7, [rbx+r11*8+256]
vpshrdvw xmm2{k5}, xmm7, [rbx+r11*8-256]
vpshrdvw xmm2{z}, xmm7, xmm0
vpshrdvw xmm2{z}, xmm7, [rbx]
vpshrdvw xmm2{z}, xmm7, [rbx+r11*8+256]
vpshrdvw xmm2{z}, xmm7, [rbx+r11*8-256]
vpshrdvw xmm2{k5}{z}, xmm7, xmm0
vpshrdvw xmm2{k5}{z}, xmm7, [rbx]
vpshrdvw xmm2{k5}{z}, xmm7, [rbx+r11*8+256]
@ -852,10 +647,6 @@
vpshrdvw ymm16{k5}, ymm13, [rbx]
vpshrdvw ymm16{k5}, ymm13, [rbx+r11*8+256]
vpshrdvw ymm16{k5}, ymm13, [rbx+r11*8-256]
vpshrdvw ymm16{z}, ymm13, ymm15
vpshrdvw ymm16{z}, ymm13, [rbx]
vpshrdvw ymm16{z}, ymm13, [rbx+r11*8+256]
vpshrdvw ymm16{z}, ymm13, [rbx+r11*8-256]
vpshrdvw ymm16{k5}{z}, ymm13, ymm15
vpshrdvw ymm16{k5}{z}, ymm13, [rbx]
vpshrdvw ymm16{k5}{z}, ymm13, [rbx+r11*8+256]
@ -868,10 +659,6 @@
vpshrdvw zmm24{k5}, zmm24, [rbx]
vpshrdvw zmm24{k5}, zmm24, [rbx+r11*8+256]
vpshrdvw zmm24{k5}, zmm24, [rbx+r11*8-256]
vpshrdvw zmm24{z}, zmm24, zmm31
vpshrdvw zmm24{z}, zmm24, [rbx]
vpshrdvw zmm24{z}, zmm24, [rbx+r11*8+256]
vpshrdvw zmm24{z}, zmm24, [rbx+r11*8-256]
vpshrdvw zmm24{k5}{z}, zmm24, zmm31
vpshrdvw zmm24{k5}{z}, zmm24, [rbx]
vpshrdvw zmm24{k5}{z}, zmm24, [rbx+r11*8+256]
@ -884,10 +671,6 @@
vpshrdw xmm2{k5}, xmm7, [rbx], 0x90
vpshrdw xmm2{k5}, xmm7, [rbx+r11*8+256], 0x90
vpshrdw xmm2{k5}, xmm7, [rbx+r11*8-256], 0x90
vpshrdw xmm2{z}, xmm7, xmm0, 0x90
vpshrdw xmm2{z}, xmm7, [rbx], 0x90
vpshrdw xmm2{z}, xmm7, [rbx+r11*8+256], 0x90
vpshrdw xmm2{z}, xmm7, [rbx+r11*8-256], 0x90
vpshrdw xmm2{k5}{z}, xmm7, xmm0, 0x90
vpshrdw xmm2{k5}{z}, xmm7, [rbx], 0x90
vpshrdw xmm2{k5}{z}, xmm7, [rbx+r11*8+256], 0x90
@ -900,10 +683,6 @@
vpshrdw ymm16{k5}, ymm13, [rbx], 0x90
vpshrdw ymm16{k5}, ymm13, [rbx+r11*8+256], 0x90
vpshrdw ymm16{k5}, ymm13, [rbx+r11*8-256], 0x90
vpshrdw ymm16{z}, ymm13, ymm15, 0x90
vpshrdw ymm16{z}, ymm13, [rbx], 0x90
vpshrdw ymm16{z}, ymm13, [rbx+r11*8+256], 0x90
vpshrdw ymm16{z}, ymm13, [rbx+r11*8-256], 0x90
vpshrdw ymm16{k5}{z}, ymm13, ymm15, 0x90
vpshrdw ymm16{k5}{z}, ymm13, [rbx], 0x90
vpshrdw ymm16{k5}{z}, ymm13, [rbx+r11*8+256], 0x90
@ -916,10 +695,6 @@
vpshrdw zmm24{k5}, zmm24, [rbx], 0x90
vpshrdw zmm24{k5}, zmm24, [rbx+r11*8+256], 0x90
vpshrdw zmm24{k5}, zmm24, [rbx+r11*8-256], 0x90
vpshrdw zmm24{z}, zmm24, zmm31, 0x90
vpshrdw zmm24{z}, zmm24, [rbx], 0x90
vpshrdw zmm24{z}, zmm24, [rbx+r11*8+256], 0x90
vpshrdw zmm24{z}, zmm24, [rbx+r11*8-256], 0x90
vpshrdw zmm24{k5}{z}, zmm24, zmm31, 0x90
vpshrdw zmm24{k5}{z}, zmm24, [rbx], 0x90
vpshrdw zmm24{k5}{z}, zmm24, [rbx+r11*8+256], 0x90

13573
bddisasm_test/avx512/avx512vbmi_64.result
View File

File diff suppressed because it is too large Load Diff

2
bddisasm_test/avx512/avx512vnni_64
View File

@ -1 +1 @@
bòEPÐbòEPbòEPb²EPTÛb²EPTÛðbòE PÐbòE PbòEPb²E PTÛb²E PTÛðbòEˆPÐbòEˆPbòE˜Pb²EˆPTÛb²EˆPTÛðbòE<C3B2>PÐbòE<C3B2>PbòE<C3B2>Pb²E<C2B2>PTÛb²E<C2B2>PTÛðbÂ(PÇbâ(Pbâ8Pb¢(PDÛb¢(PDÛøbÂ-PÇbâ-Pbâ=Pb¢-PDÛb¢-PDÛøb¨PÇbâ¨Pbâ¸Pb¢¨PDÛb¢¨PDÛøb­PÇbâ­Pbâ½Pb¢­PDÛb¢­PDÛøb=@PÇbb=@Pbb=PPb"=@PDÛb"=@PDÛüb=EPÇbb=EPbb=UPb"=EPDÛb"=EPDÛüb=ÀPÇbb=ÀPbb=ÐPb"=ÀPDÛb"=ÀPDÛüb=ÅPÇbb=ÅPbb=ÕPb"=ÅPDÛb"=ÅPDÛübòEQÐbòEQbòEQb²EQTÛb²EQTÛðbòE QÐbòE QbòEQb²E QTÛb²E QTÛðbòEˆQÐbòEˆQbòE˜Qb²EˆQTÛb²EˆQTÛðbòE<C3B2>QÐbòE<C3B2>QbòE<C3B2>Qb²E<C2B2>QTÛb²E<C2B2>QTÛðbÂ(QÇbâ(Qbâ8Qb¢(QDÛb¢(QDÛøbÂ-QÇbâ-Qbâ=Qb¢-QDÛb¢-QDÛøb¨QÇbâ¨Qbâ¸Qb¢¨QDÛb¢¨QDÛøb­QÇbâ­Qbâ½Qb¢­QDÛb¢­QDÛøb=@QÇbb=@Qbb=PQb"=@QDÛb"=@QDÛüb=EQÇbb=EQbb=UQb"=EQDÛb"=EQDÛüb=ÀQÇbb=ÀQbb=ÐQb"=ÀQDÛb"=ÀQDÛüb=ÅQÇbb=ÅQbb=ÕQb"=ÅQDÛb"=ÅQDÛübòERÐbòERbòERb²ERTÛb²ERTÛðbòE RÐbòE RbòERb²E RTÛb²E RTÛðbòEˆRÐbòEˆRbòE˜Rb²EˆRTÛb²EˆRTÛðbòE<EFBFBD>RÐbòE<EFBFBD>RbòE<C3B2>Rb²E<C2B2>RTÛb²E<C2B2>RTÛðbÂ(RÇbâ(Rbâ8Rb¢(RDÛb¢(RDÛøbÂ-RÇbâ-Rbâ=Rb¢-RDÛb¢-RDÛøb¨RÇbâ¨Rbâ¸Rb¢¨RDÛb¢¨RDÛøb­RÇbâ­Rbâ½Rb¢­RDÛb¢­RDÛøb=@RÇbb=@Rbb=PRb"=@RDÛb"=@RDÛüb=ERÇbb=ERbb=URb"=ERDÛb"=ERDÛüb=ÀRÇbb=ÀRbb=ÐRb"=ÀRDÛb"=ÀRDÛüb=ÅRÇbb=ÅRbb=ÕRb"=ÅRDÛb"=ÅRDÛübòESÐbòESbòESb²ESTÛb²ESTÛðbòE SÐbòE SbòESb²E STÛb²E ˆPÐbòEˆPbòE˜Pb²EˆPTÛb²EˆPTÛðbòE<C3B2>PÐbòE<C3B2>PbòE<C3B2>Pb²E<C2B2>PTÛb²E<C2B2>PTÛðbÂ(PÇbâ(Pbâ8Pb¢(PDÛb¢(PDÛøbÂ-PÇbâ-Pbâ=Pb¢-PDÛb¢-PDÛøb¨PÇbâ¨Pbâ¸Pb¢¨PDÛb¢¨PDÛøb­PÇbâ­Pbâ½Pb¢­PDÛb¢­PDÛøb=@PÇbb=@Pbb=PPb"=@PDÛb"=@PDÛüb=EPÇbb=EPbb=UPb"=EPDÛb"=EPDÛüb=ÀPÇbb=ÀPbb=ÐPb"=ÀPDÛb"=ÀPDÛüb=ÅPÇbb=ÅPbb=ÕPb"=ÅPDÛb"=ÅPDÛübòEQÐbòEQbòEQb²EQTÛb²EQTÛðbòE QbòEQb²E SDÛüb=ÅSÇbb=ÅSbb=ÕSb"=ÅSDÛb"=ÅSDÛü
bòEPÐbòEPbòEPb²EPTÛb²EPTÛðbòE PÐbòE PbòEPb²E PTÛb²E PTÛðbòEˆPÐbòEˆPbòE˜Pb²EˆPTÛb²EˆPTÛðbòE<C3B2>PÐbòE<C3B2>PbòE<C3B2>Pb²E<C2B2>PTÛb²E<C2B2>PTÛðbÂ(PÇbâ(Pbâ8Pb¢(PDÛb¢(PDÛøbÂ-PÇbâ-Pbâ=Pb¢-PDÛb¢-PDÛøb¨PÇbâ¨Pbâ¸Pb¢¨PDÛb¢¨PDÛøb­PÇbâ­Pbâ½Pb¢­PDÛb¢­PDÛøb=@PÇbb=@Pbb=PPb"=@PDÛb"=@PDÛüb=EPÇbb=EPbb=UPb"=EPDÛb"=EPDÛüb=ÀPÇbb=ÀPbb=ÐPb"=ÀPDÛb"=ÀPDÛüb=ÅPÇbb=ÅPbb=ÕPb"=ÅPDÛb"=ÅPDÛübòEQÐbòEQbòEQb²EQTÛb²EQTÛðbòE QTÛb²E QÐbòE QbòEQb²E QTÛb²E ˆPÐbòEˆPbòE˜Pb²EˆPTÛb²EˆPTÛðbòE<C3B2>PÐbòE<C3B2>PbòE<C3B2>Pb²E<C2B2>PTÛb²E<C2B2>PTÛðbÂ(PÇbâ(Pbâ8Pb¢(PDÛb¢(PDÛøbÂ-PÇbâ-Pbâ=Pb¢-PDÛb¢-PDÛøb¨PÇbâ¨Pbâ¸Pb¢¨PDÛb¢¨PDÛøb­PÇbâ­Pbâ½Pb¢­PDÛb¢­PDÛøb=@PÇbb=@Pbb=PPb"=@PDÛb"=@PDÛüb=EPÇbb=EPbb=UPb"=EPDÛb"=EPDÛüb=ÀPÇbb=ÀPbb=ÐPb"=ÀPDÛb"=ÀPDÛüb=ÅPÇbb=ÅPbb=ÕPb"=ÅPDÛb"=ÅPDÛübòEQÐbòEQbòEQb²EQTÛb²EQTÛðbòE QTÛðbòEˆQÐbòEˆQbòE˜Qb²EˆQTÛb²EˆQTÛðbòE<C3B2>QÐbòE<C3B2>QbòE<C3B2>Qb²E<C2B2>QTÛb²E<C2B2>QTÛðbÂ(QÇbâ(Qbâ8Qb¢(QDÛb¢(QDÛøbÂ-QÇbâ-Qbâ=Qb¢-QDÛb¢-QDÛøb¨QÇbâ¨Qbâ¸Qb¢¨QDÛb¢¨QDÛøb­QÇbâ­Qbâ½Qb¢­QDÛb¢­QDÛøb=@QÇbb=@Qbb=PQb"=@QDÛb"=@QDÛüb=EQÇbb=EQbb=UQb"=EQDÛb"=EQDÛüb=ÀQÇbb=ÀQbb=ÐQb"=ÀQDÛb"=ÀQDÛüb=ÅQÇbb=ÅQbb=ÕQb"=ÅQDÛb"=ÅQDÛübòERÐbòERbòERb²ERTÛb²ERTÛðbòE RÐbòE RbòERb²E RTÛb²E RTÛðbòE<C3B2>RÐbòE<C3B2>RbòE<C3B2>Rb²E<C2B2>RTÛb²E<C2B2>RTÛðbÂ(RÇbâ(Rbâ8Rb¢(RDÛb¢(RDÛøbÂ-RÇbâ-Rbâ=Rb¢-RDÛb¢-RDÛøb­RÇbâ­Rbâ½Rb¢­RDÛb¢­RDÛøb=@RÇbb=@Rbb=PRb"=@RDÛb"=@RDÛüb=ERÇbb=ERbb=URb"=ERDÛb"=ERDÛüb=ÅRÇbb=ÅRbb=ÕRb"=ÅRDÛb"=ÅRDÛübòESÐbòESbòESb²ESTÛb²ESTÛðbòE SÐbòE SbòESb²E STÛb²E ˆPÐbòEˆPbòE˜Pb²EˆPTÛb²EˆPTÛðbòE<C3B2>PÐbòE<C3B2>PbòE<C3B2>Pb²E<C2B2>PTÛb²E<C2B2>PTÛðbÂ(PÇbâ(Pbâ8Pb¢(PDÛb¢(PDÛøbÂ-PÇbâ-Pbâ=Pb¢-PDÛb¢-PDÛøb¨PÇbâ¨Pbâ¸Pb¢¨PDÛb¢¨PDÛøb­PÇbâ­Pbâ½Pb¢­PDÛb¢­PDÛøb=@PÇbb=@Pbb=PPb"=@PDÛb"=@PDÛüb=EPÇbb=EPbb=UPb"=EPDÛb"=EPDÛüb=ÀPÇbb=ÀPbb=ÐPb"=ÀPDÛb"=ÀPDÛüb=ÅPÇbb=ÅPbb=ÕPb"=ÅPDÛb"=ÅPDÛübòEQÐbòEQbòEQb²EQTÛb²EQTÛðbòE RbòERb²E SDÛüb=ÅSÇbb=ÅSbb=ÕSb"=ÅSDÛb"=ÅSDÛü

60
bddisasm_test/avx512/avx512vnni_64.asm
View File

@ -10,11 +10,6 @@
vpdpbusd xmm2{k5}, xmm7, [rbx]{1to4}
vpdpbusd xmm2{k5}, xmm7, [rbx+r11*8+256]
vpdpbusd xmm2{k5}, xmm7, [rbx+r11*8-256]
vpdpbusd xmm2{z}, xmm7, xmm0
vpdpbusd xmm2{z}, xmm7, [rbx]
vpdpbusd xmm2{z}, xmm7, [rbx]{1to4}
vpdpbusd xmm2{z}, xmm7, [rbx+r11*8+256]
vpdpbusd xmm2{z}, xmm7, [rbx+r11*8-256]
vpdpbusd xmm2{k5}{z}, xmm7, xmm0
vpdpbusd xmm2{k5}{z}, xmm7, [rbx]
vpdpbusd xmm2{k5}{z}, xmm7, [rbx]{1to4}
@ -30,11 +25,6 @@
vpdpbusd ymm16{k5}, ymm13, [rbx]{1to8}
vpdpbusd ymm16{k5}, ymm13, [rbx+r11*8+256]
vpdpbusd ymm16{k5}, ymm13, [rbx+r11*8-256]
vpdpbusd ymm16{z}, ymm13, ymm15
vpdpbusd ymm16{z}, ymm13, [rbx]
vpdpbusd ymm16{z}, ymm13, [rbx]{1to8}
vpdpbusd ymm16{z}, ymm13, [rbx+r11*8+256]
vpdpbusd ymm16{z}, ymm13, [rbx+r11*8-256]
vpdpbusd ymm16{k5}{z}, ymm13, ymm15
vpdpbusd ymm16{k5}{z}, ymm13, [rbx]
vpdpbusd ymm16{k5}{z}, ymm13, [rbx]{1to8}
@ -50,11 +40,6 @@
vpdpbusd zmm24{k5}, zmm24, [rbx]{1to16}
vpdpbusd zmm24{k5}, zmm24, [rbx+r11*8+256]
vpdpbusd zmm24{k5}, zmm24, [rbx+r11*8-256]
vpdpbusd zmm24{z}, zmm24, zmm31
vpdpbusd zmm24{z}, zmm24, [rbx]
vpdpbusd zmm24{z}, zmm24, [rbx]{1to16}
vpdpbusd zmm24{z}, zmm24, [rbx+r11*8+256]
vpdpbusd zmm24{z}, zmm24, [rbx+r11*8-256]
vpdpbusd zmm24{k5}{z}, zmm24, zmm31
vpdpbusd zmm24{k5}{z}, zmm24, [rbx]
vpdpbusd zmm24{k5}{z}, zmm24, [rbx]{1to16}
@ -70,11 +55,6 @@
vpdpbusds xmm2{k5}, xmm7, [rbx]{1to4}
vpdpbusds xmm2{k5}, xmm7, [rbx+r11*8+256]
vpdpbusds xmm2{k5}, xmm7, [rbx+r11*8-256]
vpdpbusds xmm2{z}, xmm7, xmm0
vpdpbusds xmm2{z}, xmm7, [rbx]
vpdpbusds xmm2{z}, xmm7, [rbx]{1to4}
vpdpbusds xmm2{z}, xmm7, [rbx+r11*8+256]
vpdpbusds xmm2{z}, xmm7, [rbx+r11*8-256]
vpdpbusds xmm2{k5}{z}, xmm7, xmm0
vpdpbusds xmm2{k5}{z}, xmm7, [rbx]
vpdpbusds xmm2{k5}{z}, xmm7, [rbx]{1to4}
@ -90,11 +70,6 @@
vpdpbusds ymm16{k5}, ymm13, [rbx]{1to8}
vpdpbusds ymm16{k5}, ymm13, [rbx+r11*8+256]
vpdpbusds ymm16{k5}, ymm13, [rbx+r11*8-256]
vpdpbusds ymm16{z}, ymm13, ymm15
vpdpbusds ymm16{z}, ymm13, [rbx]
vpdpbusds ymm16{z}, ymm13, [rbx]{1to8}
vpdpbusds ymm16{z}, ymm13, [rbx+r11*8+256]
vpdpbusds ymm16{z}, ymm13, [rbx+r11*8-256]
vpdpbusds ymm16{k5}{z}, ymm13, ymm15
vpdpbusds ymm16{k5}{z}, ymm13, [rbx]
vpdpbusds ymm16{k5}{z}, ymm13, [rbx]{1to8}
@ -110,11 +85,6 @@
vpdpbusds zmm24{k5}, zmm24, [rbx]{1to16}
vpdpbusds zmm24{k5}, zmm24, [rbx+r11*8+256]
vpdpbusds zmm24{k5}, zmm24, [rbx+r11*8-256]
vpdpbusds zmm24{z}, zmm24, zmm31
vpdpbusds zmm24{z}, zmm24, [rbx]
vpdpbusds zmm24{z}, zmm24, [rbx]{1to16}
vpdpbusds zmm24{z}, zmm24, [rbx+r11*8+256]
vpdpbusds zmm24{z}, zmm24, [rbx+r11*8-256]
vpdpbusds zmm24{k5}{z}, zmm24, zmm31
vpdpbusds zmm24{k5}{z}, zmm24, [rbx]
vpdpbusds zmm24{k5}{z}, zmm24, [rbx]{1to16}
@ -130,11 +100,6 @@
vpdpwssd xmm2{k5}, xmm7, [rbx]{1to4}
vpdpwssd xmm2{k5}, xmm7, [rbx+r11*8+256]
vpdpwssd xmm2{k5}, xmm7, [rbx+r11*8-256]
vpdpwssd xmm2{z}, xmm7, xmm0
vpdpwssd xmm2{z}, xmm7, [rbx]
vpdpwssd xmm2{z}, xmm7, [rbx]{1to4}
vpdpwssd xmm2{z}, xmm7, [rbx+r11*8+256]
vpdpwssd xmm2{z}, xmm7, [rbx+r11*8-256]
vpdpwssd xmm2{k5}{z}, xmm7, xmm0
vpdpwssd xmm2{k5}{z}, xmm7, [rbx]
vpdpwssd xmm2{k5}{z}, xmm7, [rbx]{1to4}
@ -150,11 +115,6 @@
vpdpwssd ymm16{k5}, ymm13, [rbx]{1to8}
vpdpwssd ymm16{k5}, ymm13, [rbx+r11*8+256]
vpdpwssd ymm16{k5}, ymm13, [rbx+r11*8-256]
vpdpwssd ymm16{z}, ymm13, ymm15
vpdpwssd ymm16{z}, ymm13, [rbx]
vpdpwssd ymm16{z}, ymm13, [rbx]{1to8}
vpdpwssd ymm16{z}, ymm13, [rbx+r11*8+256]
vpdpwssd ymm16{z}, ymm13, [rbx+r11*8-256]
vpdpwssd ymm16{k5}{z}, ymm13, ymm15
vpdpwssd ymm16{k5}{z}, ymm13, [rbx]
vpdpwssd ymm16{k5}{z}, ymm13, [rbx]{1to8}
@ -170,11 +130,6 @@
vpdpwssd zmm24{k5}, zmm24, [rbx]{1to16}
vpdpwssd zmm24{k5}, zmm24, [rbx+r11*8+256]
vpdpwssd zmm24{k5}, zmm24, [rbx+r11*8-256]
vpdpwssd zmm24{z}, zmm24, zmm31
vpdpwssd zmm24{z}, zmm24, [rbx]
vpdpwssd zmm24{z}, zmm24, [rbx]{1to16}
vpdpwssd zmm24{z}, zmm24, [rbx+r11*8+256]
vpdpwssd zmm24{z}, zmm24, [rbx+r11*8-256]
vpdpwssd zmm24{k5}{z}, zmm24, zmm31
vpdpwssd zmm24{k5}{z}, zmm24, [rbx]
vpdpwssd zmm24{k5}{z}, zmm24, [rbx]{1to16}
@ -190,11 +145,6 @@
vpdpwssds xmm2{k5}, xmm7, [rbx]{1to4}
vpdpwssds xmm2{k5}, xmm7, [rbx+r11*8+256]
vpdpwssds xmm2{k5}, xmm7, [rbx+r11*8-256]
vpdpwssds xmm2{z}, xmm7, xmm0
vpdpwssds xmm2{z}, xmm7, [rbx]
vpdpwssds xmm2{z}, xmm7, [rbx]{1to4}
vpdpwssds xmm2{z}, xmm7, [rbx+r11*8+256]
vpdpwssds xmm2{z}, xmm7, [rbx+r11*8-256]
vpdpwssds xmm2{k5}{z}, xmm7, xmm0
vpdpwssds xmm2{k5}{z}, xmm7, [rbx]
vpdpwssds xmm2{k5}{z}, xmm7, [rbx]{1to4}
@ -210,11 +160,6 @@
vpdpwssds ymm16{k5}, ymm13, [rbx]{1to8}
vpdpwssds ymm16{k5}, ymm13, [rbx+r11*8+256]
vpdpwssds ymm16{k5}, ymm13, [rbx+r11*8-256]
vpdpwssds ymm16{z}, ymm13, ymm15
vpdpwssds ymm16{z}, ymm13, [rbx]
vpdpwssds ymm16{z}, ymm13, [rbx]{1to8}
vpdpwssds ymm16{z}, ymm13, [rbx+r11*8+256]
vpdpwssds ymm16{z}, ymm13, [rbx+r11*8-256]
vpdpwssds ymm16{k5}{z}, ymm13, ymm15
vpdpwssds ymm16{k5}{z}, ymm13, [rbx]
vpdpwssds ymm16{k5}{z}, ymm13, [rbx]{1to8}
@ -230,11 +175,6 @@
vpdpwssds zmm24{k5}, zmm24, [rbx]{1to16}
vpdpwssds zmm24{k5}, zmm24, [rbx+r11*8+256]
vpdpwssds zmm24{k5}, zmm24, [rbx+r11*8-256]
vpdpwssds zmm24{z}, zmm24, zmm31
vpdpwssds zmm24{z}, zmm24, [rbx]
vpdpwssds zmm24{z}, zmm24, [rbx]{1to16}
vpdpwssds zmm24{z}, zmm24, [rbx+r11*8+256]
vpdpwssds zmm24{z}, zmm24, [rbx+r11*8-256]
vpdpwssds zmm24{k5}{z}, zmm24, zmm31
vpdpwssds zmm24{k5}{z}, zmm24, [rbx]
vpdpwssds zmm24{k5}{z}, zmm24, [rbx]{1to16}

1660
bddisasm_test/avx512/avx512vnni_64.result
View File

File diff suppressed because it is too large Load Diff

BIN
bddisasm_test/special/amx_64_skip Normal file
View File

Binary file not shown.

46
bddisasm_test/special/amx_64_skip.asm Normal file
View File

@ -0,0 +1,46 @@
bits 64
; srcdest == src1, src1 == src2 or srcdest == src2 => #UD.
db 0xc4, 0xe2, 0x78, 0x5e, 0xC0 ; TDPBUUD tmm0, tmm0, tmm0
db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
db 0xc4, 0xe2, 0x78, 0x5e, 0xC1 ; TDPBUUD tmm0, tmm1, tmm0
db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
db 0xc4, 0xe2, 0x78, 0x5e, 0xC8 ; TDPBUUD tmm1, tmm0, tmm0
db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
db 0xc4, 0xe2, 0x70, 0x5e, 0xC0 ; TDPBUUD tmm0, tmm0, tmm1
db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
; tileload or tilestore without SIB => #UD.
db 0xc4, 0xe2, 0x79, 0x4b, 0x00 ; TILELOADDT1 tmm0, [rax]
db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
db 0xc4, 0xe2, 0x7b, 0x4b, 0x00, ; TILELOADD tmm0, [rax]
db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
db 0xc4, 0xe2, 0x7a, 0x4b, 0x00 ; TILESTORED tmm0, [rax+rax]
db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
; using vex.vvvv != 0b1111 => #UD
db 0xc4, 0xe2, 0x70, 0x49, 0x00 ; LDTILECFG zmmword ptr [rax]
db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
db 0xc4, 0xe2, 0x71, 0x49, 0x00 ; STTILECFG zmmword ptr [rax]
db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
db 0xc4, 0xe2, 0x71, 0x4b, 0x04, 0x00 ; TILELOADDT1 tmm0, [rax+rax]
db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
db 0xc4, 0xe2, 0x73, 0x4b, 0x04, 0x00 ; TILELOADD tmm0, [rax+rax]
db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
db 0xc4, 0xe2, 0x72, 0x4b, 0x04, 0x00 ; TILESTORED tmm0, [rax+rax]
db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
db 0xc4, 0xe2, 0x71, 0x4b, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00 ; TILELOADDT1 tmm0, [rax+rax+0]
db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
db 0xc4, 0xe2, 0x73, 0x4b, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00 ; TILELOADD tmm0, [rax+rax+0]
db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
db 0xc4, 0xe2, 0x72, 0x4b, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00 ; TILESTORED tmm0, [rax+rax+0]
db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
db 0xc4, 0xe2, 0x70, 0x49, 0xC0 ; TILERELEASE
db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
db 0xc4, 0xe2, 0x73, 0x49, 0xC0 ; TILEZERO tmm0
db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
db 0xc4, 0xe2, 0x73, 0x49, 0xf8 ; TILEZERO tmm7
db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90

18
bddisasm_test/special/amx_64_skip.result Normal file
View File

@ -0,0 +1,18 @@
0000000000000000 c4 db 0xc4 (0x80000043)
0000000000000010 c4 db 0xc4 (0x80000043)
0000000000000020 c4 db 0xc4 (0x80000043)
0000000000000030 c4 db 0xc4 (0x80000043)
0000000000000040 c4 db 0xc4 (0x80000042)
0000000000000050 c4 db 0xc4 (0x80000042)
0000000000000060 c4 db 0xc4 (0x80000042)
0000000000000070 c4 db 0xc4 (0x80000032)
0000000000000080 c4 db 0xc4 (0x80000032)
0000000000000090 c4 db 0xc4 (0x80000032)
00000000000000A0 c4 db 0xc4 (0x80000032)
00000000000000B0 c4 db 0xc4 (0x80000032)
00000000000000C0 c4 db 0xc4 (0x80000032)
00000000000000D0 c4 db 0xc4 (0x80000032)
00000000000000E0 c4 db 0xc4 (0x80000032)
00000000000000F0 c4 db 0xc4 (0x80000032)
0000000000000100 c4 db 0xc4 (0x80000032)
0000000000000110 c4 db 0xc4 (0x80000032)

BIN
bddisasm_test/special/avx2gather_1_64_skip Normal file
View File

Binary file not shown.

3
bddisasm_test/special/avx2gather_1_64_skip.asm Normal file
View File

@ -0,0 +1,3 @@
bits 64
vpgatherqq xmm2, [rbx+xmm2*8+0x1000], xmm13

1
bddisasm_test/special/avx2gather_1_64_skip.result Normal file
View File

@ -0,0 +1 @@
0000000000000000 c4 db 0xc4 (0x80000031)

BIN
bddisasm_test/special/avx2gather_2_64_skip Normal file
View File

Binary file not shown.

3
bddisasm_test/special/avx2gather_2_64_skip.asm Normal file
View File

@ -0,0 +1,3 @@
bits 64
vpgatherqq xmm2, [rbx+xmm7*8+0x1000], xmm2

1
bddisasm_test/special/avx2gather_2_64_skip.result Normal file
View File

@ -0,0 +1 @@
0000000000000000 c4 db 0xc4 (0x80000031)

BIN
bddisasm_test/special/avx2gather_3_64_skip Normal file
View File

Binary file not shown.

3
bddisasm_test/special/avx2gather_3_64_skip.asm Normal file
View File

@ -0,0 +1,3 @@
bits 64
vpgatherqq xmm2, [rbx+xmm7*8+0x1000], xmm7

1
bddisasm_test/special/avx2gather_3_64_skip.result Normal file
View File

@ -0,0 +1 @@
0000000000000000 c4 db 0xc4 (0x80000031)

1
bddisasm_test/special/ignorew_evex_32 Normal file
View File

@ -0,0 +1 @@
bЯЩnиbЯЩ~иbЯH*иbЯЪH*иbЯH-иbЯЪH-и

110
bddisasm_test/special/ignorew_evex_32.result Normal file
View File

@ -0,0 +1,110 @@
0000000000000000 62f1fd086ec9 VMOVD xmm1, ecx
DSIZE: 32, ASIZE: 32, VLEN: 128
ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no
CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16
EVEX Tuple Type: Tuple 1 Scalar
Exception class: EVEX, exception type: E9NF
Valid modes
R0: yes, R1: yes, R2: yes, R3: yes
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
Valid prefixes
REP: no, REPcc: no, LOCK: no
HLE: no, XACQUIRE only: no, XRELEASE only: no
BND: no, BHINT: no, DNT: no
Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 1, RegCount: 1
Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1
0000000000000006 62f1fd087ec9 VMOVD ecx, xmm1
DSIZE: 32, ASIZE: 32, VLEN: 128
ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no
CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16
EVEX Tuple Type: Tuple 1 Scalar
Exception class: EVEX, exception type: E9NF
Valid modes
R0: yes, R1: yes, R2: yes, R3: yes
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
Valid prefixes
REP: no, REPcc: no, LOCK: no
HLE: no, XACQUIRE only: no, XRELEASE only: no
BND: no, BHINT: no, DNT: no
Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1
Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 1, RegCount: 1
000000000000000C 62f17f482ac9 VCVTSI2SD xmm1, xmm0, ecx
DSIZE: 32, ASIZE: 32, VLEN: 512
ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no
CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16
EVEX Tuple Type: Tuple 1 Scalar
Exception class: EVEX, exception type: E10NF
Valid modes
R0: yes, R1: yes, R2: yes, R3: yes
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
Valid prefixes
REP: no, REPcc: no, LOCK: no
HLE: no, XACQUIRE only: no, XRELEASE only: no
BND: no, BHINT: no, DNT: no
Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 1, RegCount: 1
Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1
Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1
0000000000000012 62f1ff482ac9 VCVTSI2SD xmm1, xmm0, ecx
DSIZE: 32, ASIZE: 32, VLEN: 512
ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no
CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16
EVEX Tuple Type: Tuple 1 Scalar
Exception class: EVEX, exception type: E10NF
Valid modes
R0: yes, R1: yes, R2: yes, R3: yes
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
Valid prefixes
REP: no, REPcc: no, LOCK: no
HLE: no, XACQUIRE only: no, XRELEASE only: no
BND: no, BHINT: no, DNT: no
Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 1, RegCount: 1
Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1
Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1
0000000000000018 62f17f482dc9 VCVTSD2SI ecx, xmm1
DSIZE: 32, ASIZE: 32, VLEN: 512
ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no
CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16
EVEX Tuple Type: Tuple 1 Fixes
Exception class: EVEX, exception type: E3
Valid modes
R0: yes, R1: yes, R2: yes, R3: yes
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
Valid prefixes
REP: no, REPcc: no, LOCK: no
HLE: no, XACQUIRE only: no, XRELEASE only: no
BND: no, BHINT: no, DNT: no
Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1
Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 1, RegCount: 1
000000000000001E 62f1ff482dc9 VCVTSD2SI ecx, xmm1
DSIZE: 32, ASIZE: 32, VLEN: 512
ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no
CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16
EVEX Tuple Type: Tuple 1 Fixes
Exception class: EVEX, exception type: E3
Valid modes
R0: yes, R1: yes, R2: yes, R3: yes
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
Valid prefixes
REP: no, REPcc: no, LOCK: no
HLE: no, XACQUIRE only: no, XRELEASE only: no
BND: no, BHINT: no, DNT: no
Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1
Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 1, RegCount: 1

1
bddisasm_test/special/ignorew_evex_64 Normal file
View File

@ -0,0 +1 @@
bЯЩnиbЯЩ~иbЯH*иbЯЪH*иbЯH-иbЯЪH-и

110
bddisasm_test/special/ignorew_evex_64.result Normal file
View File

@ -0,0 +1,110 @@
0000000000000000 62f1fd086ec9 VMOVQ xmm1, rcx
DSIZE: 64, ASIZE: 64, VLEN: 128
ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no
CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16
EVEX Tuple Type: Tuple 1 Scalar
Exception class: EVEX, exception type: E9NF
Valid modes
R0: yes, R1: yes, R2: yes, R3: yes
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
Valid prefixes
REP: no, REPcc: no, LOCK: no
HLE: no, XACQUIRE only: no, XRELEASE only: no
BND: no, BHINT: no, DNT: no
Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 1, RegCount: 1
Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1
0000000000000006 62f1fd087ec9 VMOVQ rcx, xmm1
DSIZE: 64, ASIZE: 64, VLEN: 128
ISA Set: AVX512F, Ins cat: DATAXFER, CET tracked: no
CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16
EVEX Tuple Type: Tuple 1 Scalar
Exception class: EVEX, exception type: E9NF
Valid modes
R0: yes, R1: yes, R2: yes, R3: yes
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
Valid prefixes
REP: no, REPcc: no, LOCK: no
HLE: no, XACQUIRE only: no, XRELEASE only: no
BND: no, BHINT: no, DNT: no
Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1
Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 1, RegCount: 1
000000000000000C 62f17f482ac9 VCVTSI2SD xmm1, xmm0, ecx
DSIZE: 32, ASIZE: 64, VLEN: 512
ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no
CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16
EVEX Tuple Type: Tuple 1 Scalar
Exception class: EVEX, exception type: E10NF
Valid modes
R0: yes, R1: yes, R2: yes, R3: yes
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
Valid prefixes
REP: no, REPcc: no, LOCK: no
HLE: no, XACQUIRE only: no, XRELEASE only: no
BND: no, BHINT: no, DNT: no
Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 1, RegCount: 1
Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1
Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: M, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1
0000000000000012 62f1ff482ac9 VCVTSI2SD xmm1, xmm0, rcx
DSIZE: 64, ASIZE: 64, VLEN: 512
ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no
CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16
EVEX Tuple Type: Tuple 1 Scalar
Exception class: EVEX, exception type: E3
Valid modes
R0: yes, R1: yes, R2: yes, R3: yes
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
Valid prefixes
REP: no, REPcc: no, LOCK: no
HLE: no, XACQUIRE only: no, XRELEASE only: no
BND: no, BHINT: no, DNT: no
Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 1, RegCount: 1
Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1
Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1
0000000000000018 62f17f482dc9 VCVTSD2SI ecx, xmm1
DSIZE: 32, ASIZE: 64, VLEN: 512
ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no
CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16
EVEX Tuple Type: Tuple 1 Fixes
Exception class: EVEX, exception type: E3
Valid modes
R0: yes, R1: yes, R2: yes, R3: yes
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
Valid prefixes
REP: no, REPcc: no, LOCK: no
HLE: no, XACQUIRE only: no, XRELEASE only: no
BND: no, BHINT: no, DNT: no
Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1
Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 1, RegCount: 1
000000000000001E 62f1ff482dc9 VCVTSD2SI rcx, xmm1
DSIZE: 64, ASIZE: 64, VLEN: 512
ISA Set: AVX512F, Ins cat: CONVERT, CET tracked: no
CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16
EVEX Tuple Type: Tuple 1 Fixes
Exception class: EVEX, exception type: E3
Valid modes
R0: yes, R1: yes, R2: yes, R3: yes
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
Valid prefixes
REP: no, REPcc: no, LOCK: no
HLE: no, XACQUIRE only: no, XRELEASE only: no
BND: no, BHINT: no, DNT: no
Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1
Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: Vector, RegSize: 16, RegId: 1, RegCount: 1

1
bddisasm_test/special/invalid_32_skip Normal file
View File

@ -0,0 +1 @@
ø<><C3B8><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><05><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><07><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ó®À<C2AE><C380><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ó®È<C2AE><C388><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ó®Ð<C2AE><C390><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ó®Ø<C2AE><C398><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>

19
bddisasm_test/special/invalid_32_skip.asm Normal file
View File

@ -0,0 +1,19 @@
bits 32
db 0x0F, 0x01, 0xF8 ; SWAPGS
db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
db 0x0F, 0x05 ; SYSCALL
db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
db 0x0F, 0x07 ; SYSRET
db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
db 0xF3, 0x0F, 0xAE, 0xC0 ; RDFSBASE eax
db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
db 0xF3, 0x0F, 0xAE, 0xC8 ; RDGSBASE eax
db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
db 0xF3, 0x0F, 0xAE, 0xD0 ; WRFSBASE eax
db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
db 0xF3, 0x0F, 0xAE, 0xD8 ; WRGSBASE eax
db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90

55
bddisasm_test/special/invalid_32_skip.result Normal file
View File

@ -0,0 +1,55 @@
0000000000000000 0f db 0x0f (0x80000009)
0000000000000010 0f05 SYSCALL
DSIZE: 32, ASIZE: 32, VLEN: -
ISA Set: AMD, Ins cat: SYSCALL, CET tracked: no
CPUID leaf: 0x80000001, reg: ecx, bit: 11
FLAGS access
Entire register
Valid modes
R0: yes, R1: yes, R2: yes, R3: yes
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
SMM on: yes, SMM off: yes, SGX on: no, SGX off: yes, TSX on: yes, TSX off: yes
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
Valid prefixes
REP: no, REPcc: no, LOCK: no
HLE: no, XACQUIRE only: no, XRELEASE only: no
BND: no, BHINT: no, DNT: no
Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Model Specific, RegSize: 8, RegId: 0xc0000081, RegCount: 1
Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Model Specific, RegSize: 8, RegId: 0xc0000082, RegCount: 1
Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Model Specific, RegSize: 8, RegId: 0xc0000084, RegCount: 1
Operand: 3, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Segment, RegSize: 4, RegId: 2, RegCount: 1
Operand: 4, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1
Operand: 5, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 11, RegCount: 1
Operand: 6, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Segment, RegSize: 4, RegId: 1, RegCount: 1
Operand: 7, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: IP, RegSize: 4, RegId: 0, RegCount: 1
Operand: 8, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1
Operand: 9, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: SSP, RegSize: 4, RegId: 0, RegCount: 1
0000000000000020 0f07 SYSRET
DSIZE: 32, ASIZE: 32, VLEN: -
ISA Set: AMD, Ins cat: SYSRET, CET tracked: no
CPUID leaf: 0x80000001, reg: ecx, bit: 11
FLAGS access
Entire register
Valid modes
R0: yes, R1: no, R2: no, R3: no
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
SMM on: yes, SMM off: yes, SGX on: no, SGX off: yes, TSX on: yes, TSX off: yes
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
Valid prefixes
REP: no, REPcc: no, LOCK: no
HLE: no, XACQUIRE only: no, XRELEASE only: no
BND: no, BHINT: no, DNT: no
Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: Model Specific, RegSize: 8, RegId: 0xc0000081, RegCount: 1
Operand: 1, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Segment, RegSize: 4, RegId: 2, RegCount: 1
Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1
Operand: 3, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: S, RegType: General Purpose, RegSize: 8, RegId: 11, RegCount: 1
Operand: 4, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Segment, RegSize: 4, RegId: 1, RegCount: 1
Operand: 5, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: IP, RegSize: 4, RegId: 0, RegCount: 1
Operand: 6, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: Flags, RegSize: 4, RegId: 0, RegCount: 1
Operand: 7, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: SSP, RegSize: 4, RegId: 0, RegCount: 1
0000000000000030 f3 db 0xf3 (0x80000002)
0000000000000040 f3 db 0xf3 (0x80000002)
0000000000000050 f3 db 0xf3 (0x80000002)
0000000000000060 f3 db 0xf3 (0x80000002)

1
bddisasm_test/special/invalid_64_skip Normal file
View File

@ -0,0 +1 @@
<06><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><07><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><0E><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><16><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><17><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><1E><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><1F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>'<27><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>/<2F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>7<EFBFBD><37><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>?<3F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Ô<EFBFBD><C394><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>Õ<EFBFBD><C395><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>`<60><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>a<EFBFBD><61><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>š<EFBFBD><C5A1><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>ê<EFBFBD><C3AA><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>

36
bddisasm_test/special/invalid_64_skip.asm Normal file
View File

@ -0,0 +1,36 @@
bits 64
db 0x06 ; PUSH es
db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
db 0x07 ; POP es
db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
db 0x0E ; PUSH cs
db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
db 0x16 ; PUSH ss
db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
db 0x17 ; POP ss
db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
db 0x1E ; PUSH ds
db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
db 0x1F ; POP ds
db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
db 0x27 ; DAA
db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
db 0x2F ; DAS
db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
db 0x37 ; AAA
db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
db 0x3F ; AAS
db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
db 0xD4, 0x90 ; AAM
db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
db 0xD5, 0x90 ; AAD
db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
db 0x60 ; PUSHA
db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
db 0x61 ; POPA
db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
db 0x9A, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90 ; CALL far
db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
db 0xEA, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90 ; JMP far
db 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90

17
bddisasm_test/special/invalid_64_skip.result Normal file
View File

@ -0,0 +1,17 @@
0000000000000000 06 db 0x06 (0x80000009)
0000000000000010 07 db 0x07 (0x80000009)
0000000000000020 0e db 0x0e (0x80000009)
0000000000000030 16 db 0x16 (0x80000009)
0000000000000040 17 db 0x17 (0x80000009)
0000000000000050 1e db 0x1e (0x80000009)
0000000000000060 1f db 0x1f (0x80000009)
0000000000000070 27 db 0x27 (0x80000009)
0000000000000080 2f db 0x2f (0x80000009)
0000000000000090 37 db 0x37 (0x80000009)
00000000000000A0 3f db 0x3f (0x80000009)
00000000000000B0 d4 db 0xd4 (0x80000009)
00000000000000C0 d5 db 0xd5 (0x80000009)
00000000000000D0 60 db 0x60 (0x80000009)
00000000000000E0 61 db 0x61 (0x80000009)
00000000000000F0 9a db 0x9a (0x80000009)
0000000000000100 ea db 0xea (0x80000009)

1
bddisasm_test/special/invalid_evex_64_skip Normal file
View File

@ -0,0 +1 @@
bñ}ÄR@<40><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>bñ}ÄÒ<C384><C392><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>bñ} ÄR@<40><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>bñ} ÄÒ<C384><C392><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>bñ}ˆÄR@<40><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>bñ}ˆÄÒ<C384><C392><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>bòý’R@<40><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>bòý(’R@<40><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>bòýH’R@<40><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>bòý’R@<40><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>bòý9’R@<40><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>bòýY’R@<40><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>bòý‰’R@<40><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>bòý©’R@<40><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>bòýÉ’R@<40><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>böIVÛ<56><C39B><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>bögIVß<56><C39F><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>bñd©ß<><C39F><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>bñ|¡ß<><C39F><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>bñ|©<1F><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>bó}¨É<><C389><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>bóý¨ É<><C389><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>

67
bddisasm_test/special/invalid_evex_64_skip.asm Normal file
View File

@ -0,0 +1,67 @@
bits 64
; EVEX.b (broadcast) enabled for an instruction which does not support broadcast (mod: mem)
db 0x62, 0xf1, 0x7d, 0x18, 0xc4, 0x52, 0x40, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
; EVEX.b (ER/SAE) enabled for an instruction which does not support ER/SAE (mod: reg)
db 0x62, 0xf1, 0x7d, 0x18, 0xc4, 0xd2, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
; EVEX.aaa != 0 for an instruction which does not support masking
db 0x62, 0xf1, 0x7d, 0x0b, 0xc4, 0x52, 0x40, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
; EVEX.aaa != 0 for an instruction which does not support masking
db 0x62, 0xf1, 0x7d, 0x0b, 0xc4, 0xd2, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
; EVEX.z enabled for an instruction which does not support zeroing
db 0x62, 0xf1, 0x7d, 0x88, 0xc4, 0x52, 0x40, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
; EVEX.z enabled for an instruction which does not support zeroing
db 0x62, 0xf1, 0x7d, 0x88, 0xc4, 0xd2, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
; EVEX.aaa == 0 for an instruction which has mandatory masking
db 0x62, 0xf2, 0xfd, 0x08, 0x92, 0x52, 0x40, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
; EVEX.aaa == 0 for an instruction which has mandatory masking
db 0x62, 0xf2, 0xfd, 0x28, 0x92, 0x52, 0x40, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
; EVEX.aaa == 0 for an instruction which has mandatory masking
db 0x62, 0xf2, 0xfd, 0x48, 0x92, 0x52, 0x40, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
; EVEX.b (broadcast) enabled for an instruction which does not support broadcast (mod: mem)
db 0x62, 0xf2, 0xfd, 0x19, 0x92, 0x52, 0x40, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
; EVEX.b (broadcast) enabled for an instruction which does not support broadcast (mod: mem)
db 0x62, 0xf2, 0xfd, 0x39, 0x92, 0x52, 0x40, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
; EVEX.b (broadcast) enabled for an instruction which does not support broadcast (mod: mem)
db 0x62, 0xf2, 0xfd, 0x59, 0x92, 0x52, 0x40, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
; EVEX.z enabled for an instruction which does not support zeroing
db 0x62, 0xf2, 0xfd, 0x89, 0x92, 0x52, 0x40, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
; EVEX.z enabled for an instruction which does not support zeroing
db 0x62, 0xf2, 0xfd, 0xa9, 0x92, 0x52, 0x40, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
; EVEX.z enabled for an instruction which does not support zeroing
db 0x62, 0xf2, 0xfd, 0xc9, 0x92, 0x52, 0x40, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
; Destination reg equal to the first source operand for instruction which must have dst != sources
db 0x62, 0xf6, 0x7f, 0x49, 0x56, 0xdb, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
; Destination reg equal to the second source operand for instruction which must have dst != sources
db 0x62, 0xf6, 0x67, 0x49, 0x56, 0xdf, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
; EVEX.VVVV != 0 for instruction that does not use EVEX.VVVV
db 0x62, 0xf1, 0x64, 0xa9, 0x11, 0xdf, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
; EVEX.V' set for an instruction which does not use it
db 0x62, 0xf1, 0x7c, 0xa1, 0x11, 0xdf, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
; EVEX.z set for memory operand
db 0x62, 0xf1, 0x7c, 0xa9, 0x11, 0x1f, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
; EVEX.z set but EVEX.aaa == 0
db 0x62, 0xf3, 0x7d, 0xa8, 0x19, 0xc9, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90
; EVEX.z set but EVEX.aaa == 0
db 0x62, 0xf3, 0xfd, 0xa8, 0x0b, 0xc9, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x90

22
bddisasm_test/special/invalid_evex_64_skip.result Normal file
View File

@ -0,0 +1,22 @@
0000000000000000 62 db 0x62 (0x80000039)
0000000000000010 62 db 0x62 (0x80000035)
0000000000000020 62 db 0x62 (0x80000033)
0000000000000030 62 db 0x62 (0x80000033)
0000000000000040 62 db 0x62 (0x80000036)
0000000000000050 62 db 0x62 (0x80000036)
0000000000000060 62 db 0x62 (0x80000034)
0000000000000070 62 db 0x62 (0x80000034)
0000000000000080 62 db 0x62 (0x80000034)
0000000000000090 62 db 0x62 (0x80000039)
00000000000000A0 62 db 0x62 (0x80000039)
00000000000000B0 62 db 0x62 (0x80000039)
00000000000000C0 62 db 0x62 (0x80000036)
00000000000000D0 62 db 0x62 (0x80000036)
00000000000000E0 62 db 0x62 (0x80000036)
00000000000000F0 62 db 0x62 (0x80000044)
0000000000000100 62 db 0x62 (0x80000044)
0000000000000110 62 db 0x62 (0x80000032)
0000000000000120 62 db 0x62 (0x80000040)
0000000000000130 62 db 0x62 (0x80000037)
0000000000000140 62 db 0x62 (0x80000038)
0000000000000150 62 db 0x62 (0x80000038)

4
bddisasm_test/test_all.py
View File

@ -75,6 +75,8 @@ def test_dir(dir):
mod = '-b64'
if 0 < f.find('_r0'):
mod += ' -k'
if 0 < f.find('_skip'):
mod += ' -skip16'
print(' * Running test case %s...' % f)
os.system('disasm -exi %s -f %s >%s.temp' % (mod, f, f))
@ -111,6 +113,8 @@ def regenerate(dir):
mod = '-b64'
if 0 < f.find('_r0'):
mod += ' -k'
if 0 < f.find('_skip'):
mod += ' -skip16'
print(' * Regenerating test case %s...' % f)
os.system('disasm -exi %s -f %s >%s.result' % (mod, f, f))

4
disasmtool/CMakeLists.txt
View File

@ -12,6 +12,10 @@ if (NOT CMAKE_BUILD_TYPE AND NOT CMAKE_CONFIGURATION_TYPES)
set_property(CACHE CMAKE_BUILD_TYPE PROPERTY STRINGS "Debug" "Release")
endif ()
if (NOT TARGET bddisasm)
find_package(bddisasm REQUIRED)
endif ()
add_executable(disasmtool disasmtool.c)
target_link_libraries(disasmtool PRIVATE bddisasm::bddisasm bddisasm::bdshemu)

30
disasmtool/disasmtool.c
View File

@ -29,6 +29,7 @@ typedef struct _DISASM_OPTIONS
BOOLEAN Highlight; // Highlight instruction components, if true.
BOOLEAN ExtendedInfo; // Display extended instruction info, if true.
BOOLEAN BitFields; // Display the various bitfields inside the instruction, if true.
BOOLEAN Skip16; // Automatically jump over 16 bytes after each instruction.
BOOLEAN Stats; // Display disassembly stats (clocks / instruction, instructions / second), if true.
BOOLEAN Search; // Search for the Target instruction in the provided buffer.
BOOLEAN Print; // Print instruction disassembly, if true.
@ -121,6 +122,7 @@ const char* set_to_string(
case ND_SET_AVX512VNNI: return "AVX512VNNI";
case ND_SET_AVX512VP2INTERSECT: return "AVX512VP2INTERSECT";
case ND_SET_AVX512VPOPCNTDQ: return "AVX512VPOPCNTDQ";
case ND_SET_AVX512FP16: return "AVX512FP16";
case ND_SET_AVXVNNI: return "AVXVNNI";
case ND_SET_BMI1: return "BMI1";
case ND_SET_BMI2: return "BMI2";
@ -237,6 +239,7 @@ const char* category_to_string(
case ND_CAT_AVX512BF16: return "AVX512BF16";
case ND_CAT_AVX512VBMI: return "AVX512VBMI";
case ND_CAT_AVX512VP2INTERSECT: return "AVX512VP2INTERSECT";
case ND_CAT_AVX512FP16: return "AVX512FP16";
case ND_CAT_AVXVNNI: return "AVXVNNI";
case ND_CAT_BITBYTE: return "BITBYTE";
case ND_CAT_BLEND: return "BLEND";
@ -1284,7 +1287,14 @@ handle_disasm(
printf("db 0x%02x (0x%08x)\n", buffer[rip], status);
}
rip++;
if (Options->Skip16)
{
rip += 16;
}
else
{
rip++;
}
}
else
{
@ -1293,7 +1303,14 @@ handle_disasm(
print_instruction(rip + Options->Rip, &instrux, Options);
}
rip += instrux.Length;
if (Options->Skip16)
{
rip += 16;
}
else
{
rip += instrux.Length;
}
}
}
@ -1700,7 +1717,7 @@ int main(
SIZE_T rip;
char text[ND_MIN_BUF_SIZE], *fname, *target, *shemuCtxFname;
BYTE mode, print, highlight, fmode, hmode, stats, exi, vend, feat, search, isShemu, isShemuCtxf, isKernel, bitfields;
BYTE bypassw;
BYTE bypassw, skip16;
INT ret, i;
BYTE hexbuf[256], *buffer;
DISASM_OPTIONS options;
@ -1731,6 +1748,7 @@ int main(
isKernel = 0;
bitfields = 0;
bypassw = 0;
skip16 = 0;
if (NULL == argv)
{
@ -1768,6 +1786,7 @@ int main(
printf(" -bw bypass self-modifications for shemu emulation.\n");
printf(" -hl highlight instruction parts:\n");
printf(" -bits display the instruction bit fields");
printf(" -skip16 skip 16 bytes after each decoded instruction");
SetConsoleTextAttribute(GetStdHandle(STD_OUTPUT_HANDLE),
FOREGROUND_BLUE|FOREGROUND_GREEN|FOREGROUND_RED|FOREGROUND_INTENSITY);
printf(" light white prefixes\n");
@ -1965,6 +1984,10 @@ int main(
{
bitfields = 1;
}
else if (0 == strcmp(argv[i], "-skip16"))
{
skip16 = 1;
}
else
{
printf("Unknown option: '%s'\n", argv[i]);
@ -2053,6 +2076,7 @@ int main(
options.Size = fsize;
options.ExtendedInfo = exi;
options.BitFields = bitfields;
options.Skip16 = skip16;
options.Highlight = highlight;
options.Mode = mode;
options.Ring = isKernel ? 0 : 3;

9
disasmtool_lix/CMakeLists.txt
View File

@ -1,4 +1,4 @@
cmake_minimum_required(VERSION 3.12)
cmake_minimum_required(VERSION 3.16)
project(disasmtool LANGUAGES CXX)
@ -39,7 +39,10 @@ target_compile_options(
-march=nehalem
-fno-omit-frame-pointer)
# find_package(bddisasm REQUIRED)
if (NOT TARGET bddisasm)
find_package(bddisasm REQUIRED)
endif ()
find_package(RapidJSON QUIET)
target_link_libraries(disasmtool PRIVATE bddisasm::bddisasm bddisasm::bdshemu)
@ -54,7 +57,7 @@ if ("${CMAKE_BUILD_TYPE}" STREQUAL "Release")
include(CheckIPOSupported)
check_ipo_supported(RESULT USE_IPO)
if (USE_IPO)
set_target_properties(bddisasm PROPERTIES INTERPROCEDURAL_OPTIMIZATION True)
set_target_properties(disasmtool PROPERTIES INTERPROCEDURAL_OPTIMIZATION True)
endif ()
endif ()

5
disasmtool_lix/dumpers.cpp
View File

@ -1541,14 +1541,13 @@ std::string ins_class_to_str(const ND_INS_CLASS cls)
case ND_INS_XSUSLDTRK: return "xsusldtrk";
case ND_INS_XSTORE: return "xstore";
case ND_INS_XTEST: return "xtest";
case ND_INS_HRESET: return "hreset";
case ND_INS_CLUI: return "clui";
case ND_INS_STUI: return "stui";
case ND_INS_TESTUI: return "testui";
case ND_INS_UIRET: return "uiret";
case ND_INS_SENDUIPI: return "senduipi";
default: return "unhandled!";
}
return "<unknown>";
@ -1571,6 +1570,7 @@ std::string ins_cat_to_str(ND_INS_CATEGORY category)
case ND_CAT_AVX512BF16: return "avx512bf16";
case ND_CAT_AVX512VBMI: return "avx512vbmi";
case ND_CAT_AVX512VP2INTERSECT: return "avx512vp2intersect";
case ND_CAT_AVX512FP16: return "avx512fp16";
case ND_CAT_AVXVNNI: return "avxvnni";
case ND_CAT_BITBYTE: return "bitbyte";
case ND_CAT_BLEND: return "blend";
@ -1698,6 +1698,7 @@ std::string ins_set_to_str(ND_INS_SET ins_set)
case ND_SET_AVX512VNNI: return "avx512vnni";
case ND_SET_AVX512VP2INTERSECT: return "avx512vp2intersect";
case ND_SET_AVX512VPOPCNTDQ: return "avx512vpopcntdq";
case ND_SET_AVX512FP16: return "avx512fp16";
case ND_SET_AVXVNNI: return "avxvnni";
case ND_SET_BMI1: return "bmi1";
case ND_SET_BMI2: return "bmi2";

9
inc/bddisasm.h
View File

@ -191,6 +191,7 @@ typedef uint32_t ND_REG_SIZE;
#define ND_FLAG_SIBMEM 0x08000000 // sibmem addressing is used (Intel AMX instructions).
#define ND_FLAG_I67 0x10000000 // Ignore the 0x67 prefix in 64 bit mode (Intel MPX instructions).
#define ND_FLAG_IER 0x20000000 // Ignore EVEX embedded rounding.
#define ND_FLAG_IWO64 0x40000000 // Ignore VEX/EVEX.W outside 64 bit mode. It behaves as if it's 0.
//
@ -545,6 +546,7 @@ typedef enum _ND_TUPLE
ND_TUPLE_None,
ND_TUPLE_FV, // Full Vector
ND_TUPLE_HV, // Half Vector
ND_TUPLE_QV, // Quarter Vector
ND_TUPLE_T1S8, // Tuple1 scalar, size 8 bit
ND_TUPLE_T1S16, // Tuple1 scalar, size 16 bit
ND_TUPLE_T1S, // Tuple1 scalar, size 32/64 bit
@ -621,6 +623,7 @@ typedef enum _ND_EX_TYPE_EVEX
ND_EXT_E3,
ND_EXT_E3NF,
ND_EXT_E4,
ND_EXT_E4S, // E4, with an additional case: if (dst == src1) or (dst == src2)
ND_EXT_E4nb,
ND_EXT_E4NF,
ND_EXT_E4NFnb,
@ -632,6 +635,7 @@ typedef enum _ND_EX_TYPE_EVEX
ND_EXT_E9,
ND_EXT_E9NF,
ND_EXT_E10,
ND_EXT_E10S, // E10, with an additional case: if (dst == src1) or (dst == src2)
ND_EXT_E10NF,
ND_EXT_E11,
ND_EXT_E12,
@ -1053,8 +1057,8 @@ typedef union _ND_EVEX
{
uint8_t op; // 0x62
uint8_t m : 2; // m0, m1
uint8_t zero : 2; // 00
uint8_t m : 3; // m0, m1, m2. Indicates opcode map.
uint8_t zero : 1; // 0, must be 0.
uint8_t rp : 1; // ~R'
uint8_t b : 1; // ~B
uint8_t x : 1; // ~X
@ -1284,6 +1288,7 @@ typedef struct _INSTRUX
bool HasZero:1; // TRUE - the instruction uses zeroing.
bool HasEr:1; // TRUE - the instruction has embedded rounding.
bool HasSae:1; // TRUE - the instruction has SAE.
bool HasIgnEr:1; // TRUE - the instruction ignores embedded rounding.
bool SignDisp:1; // Displacement sign. 0 is positive, 1 is negative.

108
inc/constants.h
View File

@ -729,8 +729,10 @@ typedef enum _ND_INS_CLASS
ND_INS_V4FNMADDPS,
ND_INS_V4FNMADDSS,
ND_INS_VADDPD,
ND_INS_VADDPH,
ND_INS_VADDPS,
ND_INS_VADDSD,
ND_INS_VADDSH,
ND_INS_VADDSS,
ND_INS_VADDSUBPD,
ND_INS_VADDSUBPS,
@ -767,61 +769,98 @@ typedef enum _ND_INS_CLASS
ND_INS_VBROADCASTSD,
ND_INS_VBROADCASTSS,
ND_INS_VCMPPD,
ND_INS_VCMPPH,
ND_INS_VCMPPS,
ND_INS_VCMPSD,
ND_INS_VCMPSH,
ND_INS_VCMPSS,
ND_INS_VCOMISD,
ND_INS_VCOMISH,
ND_INS_VCOMISS,
ND_INS_VCOMPRESSPD,
ND_INS_VCOMPRESSPS,
ND_INS_VCVTDQ2PD,
ND_INS_VCVTDQ2PH,
ND_INS_VCVTDQ2PS,
ND_INS_VCVTNE2PS2BF16,
ND_INS_VCVTNEPS2BF16,
ND_INS_VCVTPD2DQ,
ND_INS_VCVTPD2PH,
ND_INS_VCVTPD2PS,
ND_INS_VCVTPD2QQ,
ND_INS_VCVTPD2UDQ,
ND_INS_VCVTPD2UQQ,
ND_INS_VCVTPH2DQ,
ND_INS_VCVTPH2PD,
ND_INS_VCVTPH2PS,
ND_INS_VCVTPH2PSX,
ND_INS_VCVTPH2QQ,
ND_INS_VCVTPH2UDQ,
ND_INS_VCVTPH2UQQ,
ND_INS_VCVTPH2UW,
ND_INS_VCVTPH2W,
ND_INS_VCVTPS2DQ,
ND_INS_VCVTPS2PD,
ND_INS_VCVTPS2PH,
ND_INS_VCVTPS2PHX,
ND_INS_VCVTPS2QQ,
ND_INS_VCVTPS2UDQ,
ND_INS_VCVTPS2UQQ,
ND_INS_VCVTQQ2PD,
ND_INS_VCVTQQ2PH,
ND_INS_VCVTQQ2PS,
ND_INS_VCVTSD2SH,
ND_INS_VCVTSD2SI,
ND_INS_VCVTSD2SS,
ND_INS_VCVTSD2USI,
ND_INS_VCVTSH2SD,
ND_INS_VCVTSH2SI,
ND_INS_VCVTSH2SS,
ND_INS_VCVTSH2USI,
ND_INS_VCVTSI2SD,
ND_INS_VCVTSI2SH,
ND_INS_VCVTSI2SS,
ND_INS_VCVTSS2SD,
ND_INS_VCVTSS2SH,
ND_INS_VCVTSS2SI,
ND_INS_VCVTSS2USI,
ND_INS_VCVTTPD2DQ,
ND_INS_VCVTTPD2QQ,
ND_INS_VCVTTPD2UDQ,
ND_INS_VCVTTPD2UQQ,
ND_INS_VCVTTPH2DQ,
ND_INS_VCVTTPH2QQ,
ND_INS_VCVTTPH2UDQ,
ND_INS_VCVTTPH2UQQ,
ND_INS_VCVTTPH2UW,
ND_INS_VCVTTPH2W,
ND_INS_VCVTTPS2DQ,
ND_INS_VCVTTPS2QQ,
ND_INS_VCVTTPS2UDQ,
ND_INS_VCVTTPS2UQQ,
ND_INS_VCVTTSD2SI,
ND_INS_VCVTTSD2USI,
ND_INS_VCVTTSH2SI,
ND_INS_VCVTTSH2USI,
ND_INS_VCVTTSS2SI,
ND_INS_VCVTTSS2USI,
ND_INS_VCVTUDQ2PD,
ND_INS_VCVTUDQ2PH,
ND_INS_VCVTUDQ2PS,
ND_INS_VCVTUQQ2PD,
ND_INS_VCVTUQQ2PH,
ND_INS_VCVTUQQ2PS,
ND_INS_VCVTUSI2SD,
ND_INS_VCVTUSI2SH,
ND_INS_VCVTUSI2SS,
ND_INS_VCVTUW2PH,
ND_INS_VCVTW2PH,
ND_INS_VDBPSADBW,
ND_INS_VDIVPD,
ND_INS_VDIVPH,
ND_INS_VDIVPS,
ND_INS_VDIVSD,
ND_INS_VDIVSH,
ND_INS_VDIVSS,
ND_INS_VDPBF16PS,
ND_INS_VDPPD,
@ -843,51 +882,75 @@ typedef enum _ND_INS_CLASS
ND_INS_VEXTRACTI64X2,
ND_INS_VEXTRACTI64X4,
ND_INS_VEXTRACTPS,
ND_INS_VFCMADDCPH,
ND_INS_VFCMADDCSH,
ND_INS_VFCMULCPH,
ND_INS_VFCMULCSH,
ND_INS_VFIXUPIMMPD,
ND_INS_VFIXUPIMMPS,
ND_INS_VFIXUPIMMSD,
ND_INS_VFIXUPIMMSS,
ND_INS_VFMADD132PD,
ND_INS_VFMADD132PH,
ND_INS_VFMADD132PS,
ND_INS_VFMADD132SD,
ND_INS_VFMADD132SH,
ND_INS_VFMADD132SS,
ND_INS_VFMADD213PD,
ND_INS_VFMADD213PH,
ND_INS_VFMADD213PS,
ND_INS_VFMADD213SD,
ND_INS_VFMADD213SH,
ND_INS_VFMADD213SS,
ND_INS_VFMADD231PD,
ND_INS_VFMADD231PH,
ND_INS_VFMADD231PS,
ND_INS_VFMADD231SD,
ND_INS_VFMADD231SH,
ND_INS_VFMADD231SS,
ND_INS_VFMADDCPH,
ND_INS_VFMADDCSH,
ND_INS_VFMADDPD,
ND_INS_VFMADDPS,
ND_INS_VFMADDSD,
ND_INS_VFMADDSS,
ND_INS_VFMADDSUB132PD,
ND_INS_VFMADDSUB132PH,
ND_INS_VFMADDSUB132PS,
ND_INS_VFMADDSUB213PD,
ND_INS_VFMADDSUB213PH,
ND_INS_VFMADDSUB213PS,
ND_INS_VFMADDSUB231PD,
ND_INS_VFMADDSUB231PH,
ND_INS_VFMADDSUB231PS,
ND_INS_VFMADDSUBPD,
ND_INS_VFMADDSUBPS,
ND_INS_VFMSUB132PD,
ND_INS_VFMSUB132PH,
ND_INS_VFMSUB132PS,
ND_INS_VFMSUB132SD,
ND_INS_VFMSUB132SH,
ND_INS_VFMSUB132SS,
ND_INS_VFMSUB213PD,
ND_INS_VFMSUB213PH,
ND_INS_VFMSUB213PS,
ND_INS_VFMSUB213SD,
ND_INS_VFMSUB213SH,
ND_INS_VFMSUB213SS,
ND_INS_VFMSUB231PD,
ND_INS_VFMSUB231PH,
ND_INS_VFMSUB231PS,
ND_INS_VFMSUB231SD,
ND_INS_VFMSUB231SH,
ND_INS_VFMSUB231SS,
ND_INS_VFMSUBADD132PD,
ND_INS_VFMSUBADD132PH,
ND_INS_VFMSUBADD132PS,
ND_INS_VFMSUBADD213PD,
ND_INS_VFMSUBADD213PH,
ND_INS_VFMSUBADD213PS,
ND_INS_VFMSUBADD231PD,
ND_INS_VFMSUBADD231PH,
ND_INS_VFMSUBADD231PS,
ND_INS_VFMSUBADDPD,
ND_INS_VFMSUBADDPS,
@ -895,41 +958,57 @@ typedef enum _ND_INS_CLASS
ND_INS_VFMSUBPS,
ND_INS_VFMSUBSD,
ND_INS_VFMSUBSS,
ND_INS_VFMULCPH,
ND_INS_VFMULCSH,
ND_INS_VFNMADD132PD,
ND_INS_VFNMADD132PH,
ND_INS_VFNMADD132PS,
ND_INS_VFNMADD132SD,
ND_INS_VFNMADD132SH,
ND_INS_VFNMADD132SS,
ND_INS_VFNMADD213PD,
ND_INS_VFNMADD213PH,
ND_INS_VFNMADD213PS,
ND_INS_VFNMADD213SD,
ND_INS_VFNMADD213SH,
ND_INS_VFNMADD213SS,
ND_INS_VFNMADD231PD,
ND_INS_VFNMADD231PH,
ND_INS_VFNMADD231PS,
ND_INS_VFNMADD231SD,
ND_INS_VFNMADD231SH,
ND_INS_VFNMADD231SS,
ND_INS_VFNMADDPD,
ND_INS_VFNMADDPS,
ND_INS_VFNMADDSD,
ND_INS_VFNMADDSS,
ND_INS_VFNMSUB132PD,
ND_INS_VFNMSUB132PH,
ND_INS_VFNMSUB132PS,
ND_INS_VFNMSUB132SD,
ND_INS_VFNMSUB132SH,
ND_INS_VFNMSUB132SS,
ND_INS_VFNMSUB213PD,
ND_INS_VFNMSUB213PH,
ND_INS_VFNMSUB213PS,
ND_INS_VFNMSUB213SD,
ND_INS_VFNMSUB213SH,
ND_INS_VFNMSUB213SS,
ND_INS_VFNMSUB231PD,
ND_INS_VFNMSUB231PH,
ND_INS_VFNMSUB231PS,
ND_INS_VFNMSUB231SD,
ND_INS_VFNMSUB231SH,
ND_INS_VFNMSUB231SS,
ND_INS_VFNMSUBPD,
ND_INS_VFNMSUBPS,
ND_INS_VFNMSUBSD,
ND_INS_VFNMSUBSS,
ND_INS_VFPCLASSPD,
ND_INS_VFPCLASSPH,
ND_INS_VFPCLASSPS,
ND_INS_VFPCLASSSD,
ND_INS_VFPCLASSSH,
ND_INS_VFPCLASSSS,
ND_INS_VFRCZPD,
ND_INS_VFRCZPS,
@ -948,12 +1027,16 @@ typedef enum _ND_INS_CLASS
ND_INS_VGATHERQPD,
ND_INS_VGATHERQPS,
ND_INS_VGETEXPPD,
ND_INS_VGETEXPPH,
ND_INS_VGETEXPPS,
ND_INS_VGETEXPSD,
ND_INS_VGETEXPSH,
ND_INS_VGETEXPSS,
ND_INS_VGETMANTPD,
ND_INS_VGETMANTPH,
ND_INS_VGETMANTPS,
ND_INS_VGETMANTSD,
ND_INS_VGETMANTSH,
ND_INS_VGETMANTSS,
ND_INS_VGF2P8AFFINEINVQB,
ND_INS_VGF2P8AFFINEQB,
@ -979,16 +1062,20 @@ typedef enum _ND_INS_CLASS
ND_INS_VMASKMOVPD,
ND_INS_VMASKMOVPS,
ND_INS_VMAXPD,
ND_INS_VMAXPH,
ND_INS_VMAXPS,
ND_INS_VMAXSD,
ND_INS_VMAXSH,
ND_INS_VMAXSS,
ND_INS_VMCALL,
ND_INS_VMCLEAR,
ND_INS_VMFUNC,
ND_INS_VMGEXIT,
ND_INS_VMINPD,
ND_INS_VMINPH,
ND_INS_VMINPS,
ND_INS_VMINSD,
ND_INS_VMINSH,
ND_INS_VMINSS,
ND_INS_VMLAUNCH,
ND_INS_VMLOAD,
@ -1019,11 +1106,13 @@ typedef enum _ND_INS_CLASS
ND_INS_VMOVNTPS,
ND_INS_VMOVQ,
ND_INS_VMOVSD,
ND_INS_VMOVSH,
ND_INS_VMOVSHDUP,
ND_INS_VMOVSLDUP,
ND_INS_VMOVSS,
ND_INS_VMOVUPD,
ND_INS_VMOVUPS,
ND_INS_VMOVW,
ND_INS_VMPSADBW,
ND_INS_VMPTRLD,
ND_INS_VMPTRST,
@ -1032,8 +1121,10 @@ typedef enum _ND_INS_CLASS
ND_INS_VMRUN,
ND_INS_VMSAVE,
ND_INS_VMULPD,
ND_INS_VMULPH,
ND_INS_VMULPS,
ND_INS_VMULSD,
ND_INS_VMULSH,
ND_INS_VMULSS,
ND_INS_VMWRITE,
ND_INS_VMXOFF,
@ -1383,15 +1474,21 @@ typedef enum _ND_INS_CLASS
ND_INS_VRCP28PS,
ND_INS_VRCP28SD,
ND_INS_VRCP28SS,
ND_INS_VRCPPH,
ND_INS_VRCPPS,
ND_INS_VRCPSH,
ND_INS_VRCPSS,
ND_INS_VREDUCEPD,
ND_INS_VREDUCEPH,
ND_INS_VREDUCEPS,
ND_INS_VREDUCESD,
ND_INS_VREDUCESH,
ND_INS_VREDUCESS,
ND_INS_VRNDSCALEPD,
ND_INS_VRNDSCALEPH,
ND_INS_VRNDSCALEPS,
ND_INS_VRNDSCALESD,
ND_INS_VRNDSCALESH,
ND_INS_VRNDSCALESS,
ND_INS_VROUNDPD,
ND_INS_VROUNDPS,
@ -1405,11 +1502,15 @@ typedef enum _ND_INS_CLASS
ND_INS_VRSQRT28PS,
ND_INS_VRSQRT28SD,
ND_INS_VRSQRT28SS,
ND_INS_VRSQRTPH,
ND_INS_VRSQRTPS,
ND_INS_VRSQRTSH,
ND_INS_VRSQRTSS,
ND_INS_VSCALEFPD,
ND_INS_VSCALEFPH,
ND_INS_VSCALEFPS,
ND_INS_VSCALEFSD,
ND_INS_VSCALEFSH,
ND_INS_VSCALEFSS,
ND_INS_VSCATTERDPD,
ND_INS_VSCATTERDPS,
@ -1430,17 +1531,22 @@ typedef enum _ND_INS_CLASS
ND_INS_VSHUFPD,
ND_INS_VSHUFPS,
ND_INS_VSQRTPD,
ND_INS_VSQRTPH,
ND_INS_VSQRTPS,
ND_INS_VSQRTSD,
ND_INS_VSQRTSH,
ND_INS_VSQRTSS,
ND_INS_VSTMXCSR,
ND_INS_VSUBPD,
ND_INS_VSUBPH,
ND_INS_VSUBPS,
ND_INS_VSUBSD,
ND_INS_VSUBSH,
ND_INS_VSUBSS,
ND_INS_VTESTPD,
ND_INS_VTESTPS,
ND_INS_VUCOMISD,
ND_INS_VUCOMISH,
ND_INS_VUCOMISS,
ND_INS_VUNPCKHPD,
ND_INS_VUNPCKHPS,
@ -1514,6 +1620,7 @@ typedef enum _ND_INS_SET
ND_SET_AVX512DQ,
ND_SET_AVX512ER,
ND_SET_AVX512F,
ND_SET_AVX512FP16,
ND_SET_AVX512IFMA,
ND_SET_AVX512PF,
ND_SET_AVX512VBMI,
@ -1628,6 +1735,7 @@ typedef enum _ND_INS_TYPE
ND_CAT_AVX2GATHER,
ND_CAT_AVX512,
ND_CAT_AVX512BF16,
ND_CAT_AVX512FP16,
ND_CAT_AVX512VBMI,
ND_CAT_AVX512VP2INTERSECT,
ND_CAT_AVXVNNI,

5
inc/disasmstatus.h
View File

@ -44,6 +44,11 @@ typedef unsigned int NDSTATUS;
#define ND_STATUS_ZEROING_NO_MASK 0x80000038 // Zeroing without masking.
#define ND_STATUS_BROADCAST_NOT_SUPPORTED 0x80000039 // Broadcast not supported.
#define ND_STATUS_BAD_EVEX_V_PRIME 0x80000040 // EVEX.V' field must be one (negated 0).
#define ND_STATUS_BAD_EVEX_LL 0x80000041 // EVEX.L'L field is invalid for the instruction.
#define ND_STATUS_SIBMEM_WITHOUT_SIB 0x80000042 // Instruction uses SIBMEM, but SIB is not present.
#define ND_STATUS_INVALID_TILE_REGS 0x80000043 // Tile registers are not unique.
#define ND_STATUS_INVALID_DEST_REGS 0x80000044 // Destination register is not unique (used as src).
// Not encoding specific.
#define ND_STATUS_INVALID_PARAMETER 0x80000100 // An invalid parameter was provided.

4
inc/version.h
View File

@ -6,7 +6,7 @@
#define DISASM_VER_H
#define DISASM_VERSION_MAJOR 1
#define DISASM_VERSION_MINOR 32
#define DISASM_VERSION_REVISION 5
#define DISASM_VERSION_MINOR 33
#define DISASM_VERSION_REVISION 0
#endif // DISASM_VER_H

31
isagenerator/disasmlib.py
View File

@ -45,6 +45,7 @@ valid_attributes = {
'SIBMEM', # Instruction uses sibmem addressing (AMX instructions).
'I67', # Ignore the address size override (0x67) prefix in 64 bit mode.
'IER', # Ignore embedded rounding for the instruction.
'IWO64', # The VEX/EVEX.W field is ignored outside 64 bit mode, and behaves as if it's 0.
}
#
@ -175,12 +176,14 @@ valid_opsize = [
'oq', # 512 bit regardless the operand size/vector length.
'p', # 32, 48 or 80 bits pointer, depending on operand size.
'pd', # 128 bit or 256 bit double-precision fp data.
'ps', # 128 bit or 256 bit single-prevision fp data.
'ps', # 128 bit or 256 bit single-precision fp data.
'ph', # Packed FP16 values.
'q', # Always 1 QWORD.
'qq', # Always 4 QWORDs.
's', # 6-byte or 10-byte pseudo-descriptor.
'sd', # Scalar element of 128 bit double-precision fp data.
'ss', # Scalar element of 128 bit single-precision fp data.
'sh', # Scalar element of FP16.
'v', # WORD, DWORD or QWORD, depending on operand size.
'w', # Always WORD.
'x', # 128 bit, 256 bit, depending on operand size.
@ -476,11 +479,13 @@ valid_decorators = [
'{er}', # Embedded Rounding.
'|B32', # Broadcast 32.
'|B64', # Broadcast 64.
'|B16', # Broadcast 16.
]
valid_tuples = [
'fv', # Full Vector, Load+Op (Full Vector Dword/Qword).
'hv', # Half Vector, Load+Op (Half Vector).
'qv', # Quarter vector, Load+op (Quarter Vector, FP16)
'fvm', # Full Vector Memory, Load/store or subDword full vector.
'hvm', # Half Vector Memory, SubQword Conversion.
'qvm', # Quarter Vector Memory, SubDword Conversion.
@ -889,7 +894,7 @@ class Instruction():
# Post-process the operands. We fill up the flags with additional info based on the operands.
for op in self.ExpOps:
for deco in op.Decorators:
self.DecoFlags.append({'{K}':'MASK', '{z}':'ZERO', '{sae}':'SAE', '{er}':'ER', '|B32':'BROADCAST', '|B64':'BROADCAST'}[deco])
self.DecoFlags.append({'{K}':'MASK', '{z}':'ZERO', '{sae}':'SAE', '{er}':'ER', '|B32':'BROADCAST', '|B64':'BROADCAST', '|B16':'BROADCAST'}[deco])
if op.Type in ['U', 'V', 'W', 'H', 'L'] and 'VECT' not in self.Flags:
self.Flags.append('VECT')
@ -907,10 +912,26 @@ class Instruction():
# Split the instruction into encoding entities.
e = self.split_encoding()
if self.Vex or self.Xop or self.Evex:
self.Spec = { "mmmmm" : e[0], "opcodes" : e[1], "modrm" : e[2], "pp" : e[3], "l" : e[4], "w" : e[5] }
self.Spec = {
"mmmmm" : e[0],
"opcodes" : e[1],
"modrm" : e[2],
"pp" : e[3],
"l" : e[4],
"w" : e[5],
}
else:
self.Spec = { "opcodes" : e[0], "modrm" : e[1], "mpre" : e[2], "mode" : e[3], "dsize" : e[4], \
"asize" : e[5], "opre" : e[6], "vendor" : e[7], "feature": e[8] }
self.Spec = {
"opcodes" : e[0],
"modrm" : e[1],
"mpre" : e[2],
"mode" : e[3],
"dsize" : e[4],
"asize" : e[5],
"opre" : e[6],
"vendor" : e[7],
"feature": e[8]
}
def process_operands(self, ops, imp = False):
p = 1

18
isagenerator/generate_tables.py
View File

@ -42,6 +42,7 @@ flags = {
'SIBMEM' : 'ND_FLAG_SIBMEM',
'I67' : 'ND_FLAG_I67',
'IER' : 'ND_FLAG_IER',
'IWO64' : 'ND_FLAG_IWO64',
}
prefixes_map = {
@ -215,11 +216,13 @@ opsize = {
'p' : 'ND_OPS_p',
'pd' : 'ND_OPS_pd',
'ps' : 'ND_OPS_ps',
'ph' : 'ND_OPS_ph',
'q' : 'ND_OPS_q',
'qq' : 'ND_OPS_qq',
's' : 'ND_OPS_s',
'sd' : 'ND_OPS_sd',
'ss' : 'ND_OPS_ss',
'sh' : 'ND_OPS_sh',
'v' : 'ND_OPS_v',
'w' : 'ND_OPS_w',
'x' : 'ND_OPS_x',
@ -253,6 +256,7 @@ opdecorators = {
'{er}' : 'ND_OPD_ER',
'|B32' : 'ND_OPD_B32',
'|B64' : 'ND_OPD_B64',
'|B16' : 'ND_OPD_B16',
}
accessmap = {
@ -272,6 +276,7 @@ tuples = {
None : '0',
'fv' : 'ND_TUPLE_FV',
'hv' : 'ND_TUPLE_HV',
'qv' : 'ND_TUPLE_QV',
'fvm' : 'ND_TUPLE_FVM',
'hvm' : 'ND_TUPLE_HVM',
'qvm' : 'ND_TUPLE_QVM',
@ -313,6 +318,7 @@ extype = {
'E3' : 'ND_EXT_E3',
'E3NF' : 'ND_EXT_E3NF',
'E4' : 'ND_EXT_E4',
'E4S' : 'ND_EXT_E4S',
'E4nb' : 'ND_EXT_E4nb',
'E4NF' : 'ND_EXT_E4NF',
'E4NFnb': 'ND_EXT_E4NFnb',
@ -324,6 +330,7 @@ extype = {
'E9' : 'ND_EXT_E9',
'E9NF' : 'ND_EXT_E9NF',
'E10' : 'ND_EXT_E10',
'E10S' : 'ND_EXT_E10S',
'E10NF' : 'ND_EXT_E10NF',
'E11' : 'ND_EXT_E11',
'E12' : 'ND_EXT_E12',
@ -437,6 +444,7 @@ ilut = {
"pp" : ("ND_ILUT_VEX_PP", 4, "ND_TABLE_VEX_PP"),
"l" : ("ND_ILUT_VEX_L", 4, "ND_TABLE_VEX_L"),
"w" : ("ND_ILUT_VEX_W", 2, "ND_TABLE_VEX_W"),
"wi" : ("ND_ILUT_VEX_WI", 2, "ND_TABLE_VEX_W"),
}
@ -822,13 +830,15 @@ def group_instructions_vex_xop_evex(ilist):
elif i.Spec["modrm"]["rm"]:
if "__TYPE__" not in d or d["__TYPE__"] in ["w", "l"]:
d["__TYPE__"] = "modrmrm"
elif i.Spec["l"]:
if "__TYPE__" not in d or d["__TYPE__"] in ["w"]:
d["__TYPE__"] = "l"
elif i.Spec["w"]:
if "__TYPE__" not in d:
d["__TYPE__"] = "w"
if 'IWO64' in i.Flags:
d["__TYPE__"] = "wi"
else:
d["__TYPE__"] = "w"
elif len(ilist) == 1:
return ilist[0]
@ -914,7 +924,7 @@ def group_instructions_vex_xop_evex(ilist):
d[p].append(i)
# Remove the prefix from the list.
i.Spec["l"] = None
elif d["__TYPE__"] == "w":
elif d["__TYPE__"] in ["w", "wi"]:
p = int(i.Spec["w"])
if p not in d:
d[p] = [i]
@ -1189,7 +1199,7 @@ def dump_translation_tree_c(t, hname, f):
else:
name = dump_translation_tree_c(t[h], hname + '_%s' % h, f)
if ttype in ["opcode", "opcode_3dnow", "mmmmm", "pp", "l", "w", "modrmreg", "modrmrm"]:
if ttype in ["opcode", "opcode_3dnow", "mmmmm", "pp", "l", "w", "wi", "modrmreg", "modrmrm"]:
index = h
else:
index = indexes[h]

36
isagenerator/instructions/table_evex1.dat
View File

@ -38,15 +38,15 @@ VMOVAPS Vn{K}{z},Wn nil [evex m:1 p:0 l:x w:
VMOVAPD Vn{K}{z},Wn nil [evex m:1 p:1 l:x w:1 0x28 /r] s:AVX512F, t:DATAXFER, l:fvm, e:E1, w:W|R|R
VMOVAPS Wn{K}{z},Vn nil [evex m:1 p:0 l:x w:0 0x29 /r] s:AVX512F, t:DATAXFER, l:fvm, e:E1, w:W|R|R
VMOVAPD Wn{K}{z},Vn nil [evex m:1 p:1 l:x w:1 0x29 /r] s:AVX512F, t:DATAXFER, l:fvm, e:E1, w:W|R|R
VCVTSI2SS Vdq,Hdq{er},Ey nil [evex m:1 p:2 l:i w:x 0x2A /r] s:AVX512F, t:CONVERT, l:t1s, e:E3, w:W|R|R
VCVTSI2SD Vdq,Hdq,Ey nil [evex m:1 p:3 l:i w:0 0x2A /r] s:AVX512F, t:CONVERT, l:t1s, e:E10NF, w:W|R|R, a:IER
VCVTSI2SD Vdq,Hdq{er},Ey nil [evex m:1 p:3 l:i w:1 0x2A /r] s:AVX512F, t:CONVERT, l:t1s, e:E3, w:W|R|R
VCVTSI2SS Vdq,Hdq{er},Ey nil [evex m:1 p:2 l:i w:x 0x2A /r] s:AVX512F, t:CONVERT, l:t1s, e:E3, w:W|R|R, a:IWO64
VCVTSI2SD Vdq,Hdq,Ey nil [evex m:1 p:3 l:i w:0 0x2A /r] s:AVX512F, t:CONVERT, l:t1s, e:E10NF, w:W|R|R, a:IER|IWO64
VCVTSI2SD Vdq,Hdq{er},Ey nil [evex m:1 p:3 l:i w:1 0x2A /r] s:AVX512F, t:CONVERT, l:t1s, e:E3, w:W|R|R, a:IWO64
VMOVNTPS Mn,Vn nil [evex m:1 p:0 l:x w:0 0x2B /r:mem] s:AVX512F, t:DATAXFER, l:fvm, e:E1NF, w:W|R
VMOVNTPD Mn,Vn nil [evex m:1 p:1 l:x w:1 0x2B /r:mem] s:AVX512F, t:DATAXFER, l:fvm, e:E1NF, w:W|R
VCVTTSS2SI Gy,Wss{sae} nil [evex m:1 p:2 l:i w:x 0x2C /r] s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R
VCVTTSD2SI Gy,Wsd{sae} nil [evex m:1 p:3 l:i w:x 0x2C /r] s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R
VCVTSS2SI Gy,Wss{er} nil [evex m:1 p:2 l:i w:x 0x2D /r] s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R
VCVTSD2SI Gy,Wsd{er} nil [evex m:1 p:3 l:i w:x 0x2D /r] s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R
VCVTTSS2SI Gy,Wss{sae} nil [evex m:1 p:2 l:i w:x 0x2C /r] s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R, a:IWO64
VCVTTSD2SI Gy,Wsd{sae} nil [evex m:1 p:3 l:i w:x 0x2C /r] s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R, a:IWO64
VCVTSS2SI Gy,Wss{er} nil [evex m:1 p:2 l:i w:x 0x2D /r] s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R, a:IWO64
VCVTSD2SI Gy,Wsd{er} nil [evex m:1 p:3 l:i w:x 0x2D /r] s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R, a:IWO64
VUCOMISS Vdq,Wss{sae} Fv [evex m:1 p:0 l:i w:0 0x2E /r] s:AVX512F, t:AVX512, l:t1s, w:R|R|W, e:E3, f:COMIS
VUCOMISD Vdq,Wsd{sae} Fv [evex m:1 p:1 l:i w:1 0x2E /r] s:AVX512F, t:AVX512, l:t1s, w:R|R|W, e:E3, f:COMIS
VCOMISS Vdq,Wss{sae} Fv [evex m:1 p:0 l:i w:0 0x2F /r] s:AVX512F, t:AVX512, l:t1s, w:R|R|W, e:E3, f:COMIS
@ -113,8 +113,8 @@ VPUNPCKHDQ Vn{K}{z},Hn,Wn|B32 nil [evex m:1 p:1 l:x w:
VPACKSSDW Vn{K}{z},Hn,Wn|B32 nil [evex m:1 p:1 l:x w:0 0x6B /r] s:AVX512BW, t:AVX512, l:fv, e:E4NF, w:W|R|R|R
VPUNPCKLQDQ Vn{K}{z},Hn,Wn|B64 nil [evex m:1 p:1 l:x w:1 0x6C /r] s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R
VPUNPCKHQDQ Vn{K}{z},Hn,Wn|B64 nil [evex m:1 p:1 l:x w:1 0x6D /r] s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R
VMOVD Vdq,Ed nil [evex m:1 p:1 l:0 w:0 0x6E /r] s:AVX512F, t:DATAXFER, l:t1s, e:E9NF, w:W|R
VMOVQ Vdq,Eq nil [evex m:1 p:1 l:0 w:1 0x6E /r] s:AVX512F, t:DATAXFER, l:t1s, e:E9NF, w:W|R
VMOVD Vdq,Ed nil [evex m:1 p:1 l:0 w:0 0x6E /r] s:AVX512F, t:DATAXFER, l:t1s, e:E9NF, w:W|R, a:IWO64
VMOVQ Vdq,Eq nil [evex m:1 p:1 l:0 w:1 0x6E /r] s:AVX512F, t:DATAXFER, l:t1s, e:E9NF, w:W|R, a:IWO64
VMOVDQA32 Vn{K}{z},Wn nil [evex m:1 p:1 l:x w:0 0x6F /r] s:AVX512F, t:DATAXFER, l:fvm, e:E1, w:W|R|R
VMOVDQA64 Vn{K}{z},Wn nil [evex m:1 p:1 l:x w:1 0x6F /r] s:AVX512F, t:DATAXFER, l:fvm, e:E1, w:W|R|R
VMOVDQU32 Vn{K}{z},Wn nil [evex m:1 p:2 l:x w:0 0x6F /r] s:AVX512F, t:DATAXFER, l:fvm, e:E4nb, w:W|R|R
@ -148,14 +148,14 @@ VCVTTPS2UDQ Vn{K}{z},Wn|B32{sae} nil [evex m:1 p:0 l:x w:
VCVTTPD2UDQ Vh{K}{z},Wn|B64{sae} nil [evex m:1 p:0 l:x w:1 0x78 /r] s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R
VCVTTPS2UQQ Vn{K}{z},Wh|B32{sae} nil [evex m:1 p:1 l:x w:0 0x78 /r] s:AVX512DQ, t:CONVERT, l:hv, e:E3, w:W|R|R
VCVTTPD2UQQ Vn{K}{z},Wn|B64{sae} nil [evex m:1 p:1 l:x w:1 0x78 /r] s:AVX512DQ, t:CONVERT, l:fv, e:E2, w:W|R|R
VCVTTSS2USI Gy,Wss{sae} nil [evex m:1 p:2 l:i w:x 0x78 /r] s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R
VCVTTSD2USI Gy,Wsd{sae} nil [evex m:1 p:3 l:i w:x 0x78 /r] s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R
VCVTTSS2USI Gy,Wss{sae} nil [evex m:1 p:2 l:i w:x 0x78 /r] s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R, a:IWO64
VCVTTSD2USI Gy,Wsd{sae} nil [evex m:1 p:3 l:i w:x 0x78 /r] s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R, a:IWO64
VCVTPS2UDQ Vn{K}{z},Wn|B32{er} nil [evex m:1 p:0 l:x w:0 0x79 /r] s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R
VCVTPD2UDQ Vh{K}{z},Wn|B64{er} nil [evex m:1 p:0 l:x w:1 0x79 /r] s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R
VCVTPS2UQQ Vn{K}{z},Wh|B32{er} nil [evex m:1 p:1 l:x w:0 0x79 /r] s:AVX512DQ, t:CONVERT, l:hv, e:E3, w:W|R|R
VCVTPD2UQQ Vn{K}{z},Wn|B64{er} nil [evex m:1 p:1 l:x w:1 0x79 /r] s:AVX512DQ, t:CONVERT, l:fv, e:E2, w:W|R|R
VCVTSS2USI Gy,Wss{er} nil [evex m:1 p:2 l:i w:x 0x79 /r] s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R
VCVTSD2USI Gy,Wsd{er} nil [evex m:1 p:3 l:i w:x 0x79 /r] s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R
VCVTSS2USI Gy,Wss{er} nil [evex m:1 p:2 l:i w:x 0x79 /r] s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R, a:IWO64
VCVTSD2USI Gy,Wsd{er} nil [evex m:1 p:3 l:i w:x 0x79 /r] s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R, a:IWO64
VCVTTPS2QQ Vn{K}{z},Wh|B32{sae} nil [evex m:1 p:1 l:x w:0 0x7A /r] s:AVX512DQ, t:CONVERT, l:hv, e:E3, w:W|R|R
VCVTTPD2QQ Vn{K}{z},Wn|B64{sae} nil [evex m:1 p:1 l:x w:1 0x7A /r] s:AVX512DQ, t:CONVERT, l:fv, e:E2, w:W|R|R
VCVTUDQ2PD Vn{K}{z},Wh|B32 nil [evex m:1 p:2 l:x w:0 0x7A /r] s:AVX512F, t:CONVERT, l:hv, e:E5, w:W|R|R, a:IER
@ -164,11 +164,11 @@ VCVTUDQ2PS Vn{K}{z},Wn|B32{er} nil [evex m:1 p:3 l:x w:
VCVTUQQ2PS Vh{K}{z},Wn|B64{er} nil [evex m:1 p:3 l:x w:1 0x7A /r] s:AVX512DQ, t:CONVERT, l:fv, e:E2, w:W|R|R
VCVTPS2QQ Vn{K}{z},Wh|B32{er} nil [evex m:1 p:1 l:x w:0 0x7B /r] s:AVX512DQ, t:CONVERT, l:hv, e:E3, w:W|R|R
VCVTPD2QQ Vn{K}{z},Wn|B64{er} nil [evex m:1 p:1 l:x w:1 0x7B /r] s:AVX512DQ, t:CONVERT, l:fv, e:E2, w:W|R|R
VCVTUSI2SS Vss,Hss{er},Ey nil [evex m:1 p:2 l:i w:x 0x7B /r] s:AVX512F, t:CONVERT, l:t1s, e:E3, w:W|R|R
VCVTUSI2SD Vdq,Hdq,Ey nil [evex m:1 p:3 l:i w:0 0x7B /r] s:AVX512F, t:CONVERT, l:t1s, e:E10NF, w:W|R|R, a:IER
VCVTUSI2SD Vdq,Hdq{er},Ey nil [evex m:1 p:3 l:i w:1 0x7B /r] s:AVX512F, t:CONVERT, l:t1s, e:E3, w:W|R|R
VMOVD Ey,Vdq nil [evex m:1 p:1 l:0 w:0 0x7E /r] s:AVX512F, t:DATAXFER, l:t1s, e:E9NF, w:W|R
VMOVQ Ey,Vdq nil [evex m:1 p:1 l:0 w:1 0x7E /r] s:AVX512F, t:DATAXFER, l:t1s, e:E9NF, w:W|R
VCVTUSI2SS Vss,Hss{er},Ey nil [evex m:1 p:2 l:i w:x 0x7B /r] s:AVX512F, t:CONVERT, l:t1s, e:E3, w:W|R|R, a:IWO64
VCVTUSI2SD Vdq,Hdq,Ey nil [evex m:1 p:3 l:i w:0 0x7B /r] s:AVX512F, t:CONVERT, l:t1s, e:E10NF, w:W|R|R, a:IER|IWO64
VCVTUSI2SD Vdq,Hdq{er},Ey nil [evex m:1 p:3 l:i w:1 0x7B /r] s:AVX512F, t:CONVERT, l:t1s, e:E3, w:W|R|R, a:IWO64
VMOVD Ey,Vdq nil [evex m:1 p:1 l:0 w:0 0x7E /r] s:AVX512F, t:DATAXFER, l:t1s, e:E9NF, w:W|R, a:IWO64
VMOVQ Ey,Vdq nil [evex m:1 p:1 l:0 w:1 0x7E /r] s:AVX512F, t:DATAXFER, l:t1s, e:E9NF, w:W|R, a:IWO64
VMOVQ Vdq,Wq nil [evex m:1 p:2 l:0 w:1 0x7E /r] s:AVX512F, t:DATAXFER, l:t1s, e:E9NF, w:W|R
VMOVDQA32 Wn{K}{z},Vn nil [evex m:1 p:1 l:x w:0 0x7F /r] s:AVX512F, t:DATAXFER, l:fvm, e:E1, w:W|R|R
VMOVDQA64 Wn{K}{z},Vn nil [evex m:1 p:1 l:x w:1 0x7F /r] s:AVX512F, t:DATAXFER, l:fvm, e:E1, w:W|R|R

14
isagenerator/instructions/table_evex2.dat
View File

@ -45,10 +45,10 @@ VPMOVSXBQ Vn{K}{z},We nil [evex m:2 p:1 l:x w:
VPMOVSXWD Vn{K}{z},Wh nil [evex m:2 p:1 l:x w:i 0x23 /r] s:AVX512F, t:DATAXFER, l:hvm, e:E5, w:W|R|R
VPMOVSXWQ Vn{K}{z},Wf nil [evex m:2 p:1 l:x w:i 0x24 /r] s:AVX512F, t:DATAXFER, l:qvm, e:E5, w:W|R|R
VPMOVSXDQ Vn{K}{z},Wh nil [evex m:2 p:1 l:x w:0 0x25 /r] s:AVX512F, t:DATAXFER, l:hvm, e:E5, w:W|R|R
VPTESTMB rKq{K}{z},Hn,Wn nil [evex m:2 p:1 l:x w:0 0x26 /r] s:AVX512BW, t:LOGICAL, l:fvm, e:E4nb, w:W|R|R|R
VPTESTMW rKq{K}{z},Hn,Wn nil [evex m:2 p:1 l:x w:1 0x26 /r] s:AVX512BW, t:LOGICAL, l:fvm, e:E4nb, w:W|R|R|R
VPTESTMD rKq{K}{z},Hn,Wn|B32 nil [evex m:2 p:1 l:x w:0 0x27 /r] s:AVX512F, t:LOGICAL, l:fv, e:E4, w:W|R|R|R
VPTESTMQ rKq{K}{z},Hn,Wn|B64 nil [evex m:2 p:1 l:x w:1 0x27 /r] s:AVX512F, t:LOGICAL, l:fv, e:E4, w:W|R|R|R
VPTESTMB rKq{K},Hn,Wn nil [evex m:2 p:1 l:x w:0 0x26 /r] s:AVX512BW, t:LOGICAL, l:fvm, e:E4nb, w:W|R|R|R
VPTESTMW rKq{K},Hn,Wn nil [evex m:2 p:1 l:x w:1 0x26 /r] s:AVX512BW, t:LOGICAL, l:fvm, e:E4nb, w:W|R|R|R
VPTESTMD rKq{K},Hn,Wn|B32 nil [evex m:2 p:1 l:x w:0 0x27 /r] s:AVX512F, t:LOGICAL, l:fv, e:E4, w:W|R|R|R
VPTESTMQ rKq{K},Hn,Wn|B64 nil [evex m:2 p:1 l:x w:1 0x27 /r] s:AVX512F, t:LOGICAL, l:fv, e:E4, w:W|R|R|R
VPMOVSWB Wh{K}{z},Vn nil [evex m:2 p:2 l:x w:0 0x20 /r] s:AVX512BW, t:DATAXFER, l:hvm, e:E6, w:W|R|R
VPMOVSDB Wf{K}{z},Vn nil [evex m:2 p:2 l:x w:0 0x21 /r] s:AVX512F, t:DATAXFER, l:qvm, e:E6, w:W|R|R
VPMOVSQB We{K}{z},Vn nil [evex m:2 p:2 l:x w:0 0x22 /r] s:AVX512F, t:DATAXFER, l:ovm, e:E6, w:W|R|R
@ -186,8 +186,8 @@ VPBROADCASTB Vn{K}{z},Wb nil [evex m:2 p:1 l:x w:
VPBROADCASTW Vn{K}{z},Ww nil [evex m:2 p:1 l:x w:0 0x79 /r] s:AVX512BW, t:BROADCAST, l:t1s16, e:E6, w:W|R|R
VPBROADCASTB Vn{K}{z},Rb nil [evex m:2 p:1 l:x w:0 0x7A /r:reg] s:AVX512BW, t:BROADCAST, l:t1s8, e:E7NM, w:W|R|R
VPBROADCASTW Vn{K}{z},Rw nil [evex m:2 p:1 l:x w:0 0x7B /r:reg] s:AVX512BW, t:BROADCAST, l:t1s16, e:E7NM, w:W|R|R
VPBROADCASTD Vn{K}{z},Rd nil [evex m:2 p:1 l:x w:0 0x7C /r:reg] s:AVX512F, t:BROADCAST, l:t1s, e:E7NM, w:W|R|R
VPBROADCASTQ Vn{K}{z},Rq nil [evex m:2 p:1 l:x w:1 0x7C /r:reg] s:AVX512F, t:BROADCAST, l:t1s, e:E7NM, w:W|R|R
VPBROADCASTD Vn{K}{z},Rd nil [evex m:2 p:1 l:x w:0 0x7C /r:reg] s:AVX512F, t:BROADCAST, l:t1s, e:E7NM, w:W|R|R, a:IWO64
VPBROADCASTQ Vn{K}{z},Rq nil [evex m:2 p:1 l:x w:1 0x7C /r:reg] s:AVX512F, t:BROADCAST, l:t1s, e:E7NM, w:W|R|R, a:IWO64
VPERMT2B Vn{K}{z},Hn,Wn nil [evex m:2 p:1 l:x w:0 0x7D /r] s:AVX512VBMI, t:AVX512VBMI, l:fvm, e:E4NFnb, w:RW|R|R|R
VPERMT2W Vn{K}{z},Hn,Wn nil [evex m:2 p:1 l:x w:1 0x7D /r] s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:RW|R|R|R
VPERMT2D Vn{K}{z},Hn,Wn|B32 nil [evex m:2 p:1 l:x w:0 0x7E /r] s:AVX512F, t:AVX512, l:fv, e:E4NF, w:RW|R|R|R
@ -207,7 +207,7 @@ VPCOMPRESSD Wn{K}{z},Vn nil [evex m:2 p:1 l:x w:
VPCOMPRESSQ Wn{K}{z},Vn nil [evex m:2 p:1 l:x w:1 0x8B /r] s:AVX512F, t:COMPRESS, a:NOMZ, l:t1s, e:E4nb, w:W|R|R
VPERMB Vn{K}{z},Hn,Wn nil [evex m:2 p:1 l:x w:0 0x8D /r] s:AVX512VBMI, t:AVX512VBMI, a:NOMZ, l:fvm, e:E4NFnb, w:W|R|R|R
VPERMW Vn{K}{z},Hn,Wn nil [evex m:2 p:1 l:x w:1 0x8D /r] s:AVX512BW, t:AVX512, l:fv, a:NOMZ, l:fvm, e:E4NFnb, w:W|R|R|R
VPSHUFBITQMB rK{K}{z},Hn,Wn nil [evex m:2 p:1 l:x w:0 0x8F /r] s:AVX512BITALG, t:AVX512VBMI, l:fvm, w:W|R|R|R
VPSHUFBITQMB rK{K},Hn,Wn nil [evex m:2 p:1 l:x w:0 0x8F /r] s:AVX512BITALG, t:AVX512VBMI, l:fvm, w:W|R|R|R
# 0x90 - 0x9F

20
isagenerator/instructions/table_evex3.dat
View File

@ -7,8 +7,10 @@ VALIGND Vn{K}{z},Hn,Wn|B32,Ib nil [evex m:3 p:1 l:x w:
VALIGNQ Vn{K}{z},Hn,Wn|B64,Ib nil [evex m:3 p:1 l:x w:1 0x03 /r ib] s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R|R
VPERMILPS Vn{K}{z},Wn|B32,Ib nil [evex m:3 p:1 l:x w:0 0x04 /r ib] s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R
VPERMILPD Vn{K}{z},Wn|B64,Ib nil [evex m:3 p:1 l:x w:1 0x05 /r ib] s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R
VRNDSCALEPH Vn{K}{z},Wn|B16{sae},Ib nil [evex m:3 p:0 l:x w:0 0x08 /r ib] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R
VRNDSCALEPS Vn{K}{z},Wn|B32{sae},Ib nil [evex m:3 p:1 l:x w:0 0x08 /r ib] s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R
VRNDSCALEPD Vn{K}{z},Wn|B64{sae},Ib nil [evex m:3 p:1 l:x w:1 0x09 /r ib] s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R
VRNDSCALESH Vdq{K}{z},Hdq,Wsh{sae},Ib nil [evex m:3 p:0 l:i w:0 0x0A /r ib] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R|R
VRNDSCALESS Vdq{K}{z},Hdq,Wss{sae},Ib nil [evex m:3 p:1 l:i w:0 0x0A /r ib] s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R
VRNDSCALESD Vdq{K}{z},Hdq,Wsd{sae},Ib nil [evex m:3 p:1 l:i w:1 0x0B /r ib] s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R
VPALIGNR Vn{K}{z},Hn,Wn,Ib nil [evex m:3 p:1 l:x w:i 0x0F /r ib] s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:W|R|R|R|R
@ -18,8 +20,8 @@ VPEXTRB Mb,Vdq,Ib nil [evex m:3 p:1 l:0 w:
VPEXTRB Ry,Vdq,Ib nil [evex m:3 p:1 l:0 w:i 0x14 /r:reg ib] s:AVX512BW, t:AVX512, l:t1s8, e:E9NF, w:W|R|R
VPEXTRW Mw,Vdq,Ib nil [evex m:3 p:1 l:0 w:i 0x15 /r:mem ib] s:AVX512BW, t:AVX512, l:t1s16, e:E9NF, w:W|R|R
VPEXTRW Ry,Vdq,Ib nil [evex m:3 p:1 l:0 w:i 0x15 /r:reg ib] s:AVX512BW, t:AVX512, l:t1s16, e:E9NF, w:W|R|R
VPEXTRD Ed,Vdq,Ib nil [evex m:3 p:1 l:0 w:0 0x16 /r ib] s:AVX512DQ, t:AVX512, l:t1s, e:E9NF, w:W|R|R
VPEXTRQ Eq,Vdq,Ib nil [evex m:3 p:1 l:0 w:1 0x16 /r ib] s:AVX512DQ, t:AVX512, l:t1s, e:E9NF, w:W|R|R
VPEXTRD Ed,Vdq,Ib nil [evex m:3 p:1 l:0 w:0 0x16 /r ib] s:AVX512DQ, t:AVX512, l:t1s, e:E9NF, w:W|R|R, a:IWO64
VPEXTRQ Eq,Vdq,Ib nil [evex m:3 p:1 l:0 w:1 0x16 /r ib] s:AVX512DQ, t:AVX512, l:t1s, e:E9NF, w:W|R|R, a:IWO64
VEXTRACTPS Md,Vdq,Ib nil [evex m:3 p:1 l:0 w:i 0x17 /r:mem ib] s:AVX512F, t:AVX512, l:t1s, e:E9NF, w:W|R|R
VEXTRACTPS Ry,Vdq,Ib nil [evex m:3 p:1 l:0 w:i 0x17 /r:reg ib] s:AVX512F, t:AVX512, l:t1s, e:E9NF, w:W|R|R
VINSERTF32X4 Vu{K}{z},Hu,Wdq,Ib nil [evex m:3 p:1 l:x w:0 0x18 /r ib] s:AVX512F, t:AVX512, a:NOL0, l:t4, e:E6NF, w:W|R|R|R|R
@ -41,14 +43,16 @@ VPINSRB Vdq,Hdq,Mb,Ib nil [evex m:3 p:1 l:0 w:
VPINSRB Vdq,Hdq,Rd,Ib nil [evex m:3 p:1 l:0 w:i 0x20 /r:reg ib] s:AVX512BW, t:AVX512, l:t1s8, e:E9NF, w:W|R|R|R
VINSERTPS Vdq,Hdq,Md,Ib nil [evex m:3 p:1 l:0 w:i 0x21 /r:mem ib] s:AVX512F, t:AVX512, l:t1s, e:E9NF, w:W|R|R|R
VINSERTPS Vdq,Hdq,Udq,Ib nil [evex m:3 p:1 l:0 w:i 0x21 /r:reg ib] s:AVX512F, t:AVX512, l:t1s, e:E9NF, w:W|R|R|R
VPINSRD Vdq,Hdq,Ed,Ib nil [evex m:3 p:1 l:0 w:0 0x22 /r ib] s:AVX512DQ, t:AVX512, l:t1s, e:E9NF, w:W|R|R|R
VPINSRQ Vdq,Hdq,Eq,Ib nil [evex m:3 p:1 l:0 w:1 0x22 /r ib] s:AVX512DQ, t:AVX512, l:t1s, e:E9NF, w:W|R|R|R
VPINSRD Vdq,Hdq,Ed,Ib nil [evex m:3 p:1 l:0 w:0 0x22 /r ib] s:AVX512DQ, t:AVX512, l:t1s, e:E9NF, w:W|R|R|R, a:IWO64
VPINSRQ Vdq,Hdq,Eq,Ib nil [evex m:3 p:1 l:0 w:1 0x22 /r ib] s:AVX512DQ, t:AVX512, l:t1s, e:E9NF, w:W|R|R|R, a:IWO64
VSHUFF32X4 Vu{K}{z},Hu,Wu|B32,Ib nil [evex m:3 p:1 l:x w:0 0x23 /r ib] s:AVX512F, t:AVX512, a:NOL0, l:fv, e:E4NF, w:W|R|R|R|R
VSHUFF64X2 Vu{K}{z},Hu,Wu|B64,Ib nil [evex m:3 p:1 l:x w:1 0x23 /r ib] s:AVX512F, t:AVX512, a:NOL0, l:fv, e:E4NF, w:W|R|R|R|R
VPTERNLOGD Vn{K}{z},Hn,Wn|B32,Ib nil [evex m:3 p:1 l:x w:0 0x25 /r ib] s:AVX512F, t:LOGICAL, l:fv, e:E4, w:RW|R|R|R|R
VPTERNLOGQ Vn{K}{z},Hn,Wn|B64,Ib nil [evex m:3 p:1 l:x w:1 0x25 /r ib] s:AVX512F, t:LOGICAL, l:fv, e:E4, w:RW|R|R|R|R
VGETMANTPH Vn{K}{z},Wn|B16{sae},Ib nil [evex m:3 p:0 l:x w:0 0x26 /r ib] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R
VGETMANTPS Vn{K}{z},Wn|B32{sae},Ib nil [evex m:3 p:1 l:x w:0 0x26 /r ib] s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R
VGETMANTPD Vn{K}{z},Wn|B64{sae},Ib nil [evex m:3 p:1 l:x w:1 0x26 /r ib] s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R
VGETMANTSH Vdq{K}{z},Hdq,Wsh{sae},Ib nil [evex m:3 p:0 l:i w:0 0x27 /r ib] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R|R
VGETMANTSS Vdq{K}{z},Hdq,Wss{sae},Ib nil [evex m:3 p:1 l:i w:0 0x27 /r ib] s:AVX512F, t:AVX512, l:t1s, e:E2, w:W|R|R|R|R
VGETMANTSD Vdq{K}{z},Hdq,Wsd{sae},Ib nil [evex m:3 p:1 l:i w:1 0x27 /r ib] s:AVX512F, t:AVX512, l:t1s, e:E2, w:W|R|R|R|R
@ -81,14 +85,18 @@ VFIXUPIMMPS Vn{K}{z},Hn,Wn|B32{sae},Ib nil [evex m:3 p:1 l:x w:
VFIXUPIMMPD Vn{K}{z},Hn,Wn|B64{sae},Ib nil [evex m:3 p:1 l:x w:1 0x54 /r ib] s:AVX512F, t:AVX512, l:fv, e:E2, w:RW|R|R|R|R
VFIXUPIMMSS Vdq{K}{z},Hdq,Wss{sae},Ib nil [evex m:3 p:1 l:i w:0 0x55 /r ib] s:AVX512F, t:AVX512, l:t1s, e:E3, w:RW|R|R|R|R
VFIXUPIMMSD Vdq{K}{z},Hdq,Wsd{sae},Ib nil [evex m:3 p:1 l:i w:1 0x55 /r ib] s:AVX512F, t:AVX512, l:t1s, e:E3, w:RW|R|R|R|R
VREDUCEPH Vn{K}{z},Wn|B16{sae},Ib nil [evex m:3 p:0 l:x w:0 0x56 /r ib] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R
VREDUCEPS Vn{K}{z},Wn|B32{sae},Ib nil [evex m:3 p:1 l:x w:0 0x56 /r ib] s:AVX512DQ, t:AVX512, l:fv, e:E2, w:W|R|R|R
VREDUCEPD Vn{K}{z},Wn|B64{sae},Ib nil [evex m:3 p:1 l:x w:1 0x56 /r ib] s:AVX512DQ, t:AVX512, l:fv, e:E2, w:W|R|R|R
VREDUCESH Vdq{K}{z},Hdq,Wsh{sae},Ib nil [evex m:3 p:0 l:i w:0 0x57 /r ib] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R|R
VREDUCESS Vdq{K}{z},Hdq,Wss{sae},Ib nil [evex m:3 p:1 l:i w:0 0x57 /r ib] s:AVX512DQ, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R
VREDUCESD Vdq{K}{z},Hdq,Wsd{sae},Ib nil [evex m:3 p:1 l:i w:1 0x57 /r ib] s:AVX512DQ, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R
# 0x60 - 0x6F
VFPCLASSPH rKq{K},Wn|B16,Ib nil [evex m:3 p:0 l:x w:0 0x66 /r ib] s:AVX512FP16, t:AVX512FP16, l:fv, e:E4, w:W|R|R|R
VFPCLASSPS rKq{K},Wn|B32,Ib nil [evex m:3 p:1 l:x w:0 0x66 /r ib] s:AVX512DQ, t:AVX512, l:fv, e:E4, w:W|R|R|R
VFPCLASSPD rKq{K},Wn|B64,Ib nil [evex m:3 p:1 l:x w:1 0x66 /r ib] s:AVX512DQ, t:AVX512, l:fv, e:E4, w:W|R|R|R
VFPCLASSSH rKq{K},Wsh,Ib nil [evex m:3 p:0 l:i w:0 0x67 /r ib] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E10, w:W|R|R|R
VFPCLASSSS rKq{K},Wss,Ib nil [evex m:3 p:1 l:i w:0 0x67 /r ib] s:AVX512DQ, t:AVX512, l:t1s, e:E6, w:W|R|R|R
VFPCLASSSD rKq{K},Wsd,Ib nil [evex m:3 p:1 l:i w:1 0x67 /r ib] s:AVX512DQ, t:AVX512, l:t1s, e:E6, w:W|R|R|R
@ -100,7 +108,6 @@ VPSHRDW Vn{K}{z},Hn,Wn,Ib nil [evex m:3 p:1 l:x w:
VPSHRDD Vn{K}{z},Hn,Wn|B32,Ib nil [evex m:3 p:1 l:x w:0 0x73 /r ib] s:AVX512VBMI2, t:AVX512VBMI, l:fv, e:E4, w:RW|R|R|R|R
VPSHRDQ Vn{K}{z},Hn,Wn|B64,Ib nil [evex m:3 p:1 l:x w:1 0x73 /r ib] s:AVX512VBMI2, t:AVX512VBMI, l:fv, e:E4, w:RW|R|R|R|R
# 0x80 - 0x8F
# 0x90 - 0x9F
@ -110,6 +117,9 @@ VPSHRDQ Vn{K}{z},Hn,Wn|B64,Ib nil [evex m:3 p:1 l:x w:
# 0xB0 - 0xBF
# 0xC0 - 0xCF
VCMPPH rK{K},Hn,Wn|B16{sae},Ib nil [evex m:3 p:0 l:x w:0 0xC2 /r ib] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R|R
VCMPSH rK{K},Hn,Wsh{sae},Ib nil [evex m:3 p:2 l:i w:0 0xC2 /r ib] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R|R
VGF2P8AFFINEQB Vn{K}{z},Hn,Wn|B64,Ib nil [evex m:3 p:1 l:x w:1 0xCE /r ib] s:GFNI, t:GFNI, l:fv, e:E4NF, w:W|R|R|R|R
VGF2P8AFFINEINVQB Vn{K}{z},Hn,Wn|B64,Ib nil [evex m:3 p:1 l:x w:1 0xCF /r ib] s:GFNI, t:GFNI, l:fv, e:E4NF, w:W|R|R|R|R

65
isagenerator/instructions/table_evex5.dat Normal file
View File

@ -0,0 +1,65 @@
# Mnemonic Explicit Operands Implicit Encoding Flags, Prefixes, Set, Category, Class, RW map, Additional ops
#------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
# 0x10 - 0x1F
VMOVSH Vdq{K}{z},Wsh nil [evex m:5 p:2 l:i w:0 0x10 /r:mem] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E5, w:W|R|R
VMOVSH Vdq{K}{z},Hdq,Wsh nil [evex m:5 p:2 l:i w:0 0x10 /r:reg] s:AVX512FP16, t:AVX512FP16, e:E5, w:W|R|R|R
VMOVSH Wsh{K},Vdq nil [evex m:5 p:2 l:i w:0 0x11 /r:mem] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E5, w:W|R|R
VMOVSH Wsh{K}{z},Hdq,Vdq nil [evex m:5 p:2 l:i w:0 0x11 /r:reg] s:AVX512FP16, t:AVX512FP16, e:E5, w:W|R|R|R
VCVTPS2PHX Vh{K}{z},Wn|B32{er} nil [evex m:5 p:1 l:x w:0 0x1D /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R
VCVTSS2SH Vdq{K}{z},Hdq,Wss{er} nil [evex m:5 p:0 l:i w:0 0x1D /r] s:AVX512FP16, t:AVX512FP16, l:t1s, e:E3, w:W|R|R|R
# 0x20 - 0x2F
VCVTSI2SH Vdq,Hdq,Ey nil [evex m:5 p:2 l:i w:x 0x2A /r] s:AVX512FP16, t:AVX512FP16, l:t1s, e:E3NF, w:W|R|R, a:IWO64
VCVTTSH2SI Gy,Wsh{sae} nil [evex m:5 p:2 l:i w:x 0x2C /r] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3NF, w:W|R, a:IWO64
VCVTSH2SI Gy,Wsh{er} nil [evex m:5 p:2 l:i w:x 0x2D /r] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3NF, w:W|R, a:IWO64
VUCOMISH Vdq,Wsh{sae} Fv [evex m:5 p:0 l:i w:0 0x2E /r] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3NF, w:R|R|W, f:ZF=m|PF=m|CF=m|OF=0|SF=0|AF=0
VCOMISH Vdq,Wsh{sae} Fv [evex m:5 p:0 l:i w:0 0x2F /r] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3NF, w:R|R|W, f:ZF=m|PF=m|CF=m|OF=0|SF=0|AF=0
# 0x50 - 0x5F
VSQRTPH Vn{K}{z},Wn|B16{er} nil [evex m:5 p:0 l:x w:0 0x51 /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R
VSQRTSH Vdq{K}{z},Hdq,Wsh{er} nil [evex m:5 p:2 l:i w:0 0x51 /r] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R
VADDPH Vn{K}{z},Hn,Wn|B16{er} nil [evex m:5 p:0 l:x w:0 0x58 /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R
VADDSH Vdq{K}{z},Hdq,Wsh{er} nil [evex m:5 p:2 l:i w:0 0x58 /r] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R
VMULPH Vn{K}{z},Hn,Wn|B16{er} nil [evex m:5 p:0 l:x w:0 0x59 /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R
VMULSH Vdq{K}{z},Hdq,Wsh{er} nil [evex m:5 p:2 l:i w:0 0x59 /r] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R
VCVTPH2PD Vn{K}{z},Wf|B16{sae} nil [evex m:5 p:0 l:x w:0 0x5A /r] s:AVX512FP16, t:AVX512FP16, l:qv, e:E2, w:W|R|R
VCVTPD2PH Vdq{K}{z},Wn|B64{er} nil [evex m:5 p:1 l:x w:1 0x5A /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R
VCVTSH2SD Vdq{K}{z},Hdq,Wsh{sae} nil [evex m:5 p:2 l:i w:0 0x5A /r] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R
VCVTSD2SH Vdq{K}{z},Hdq,Wsd{er} nil [evex m:5 p:3 l:i w:1 0x5A /r] s:AVX512FP16, t:AVX512FP16, l:t1s, e:E3, w:W|R|R|R
VCVTDQ2PH Vh{K}{z},Wn|B32{er} nil [evex m:5 p:0 l:x w:0 0x5B /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R
VCVTQQ2PH Vdq{K}{z},Wn|B64{er} nil [evex m:5 p:0 l:x w:1 0x5B /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R
VCVTPH2DQ Vn{K}{z},Wh|B16{er} nil [evex m:5 p:1 l:x w:0 0x5B /r] s:AVX512FP16, t:AVX512FP16, l:hv, e:E2, w:W|R|R
VCVTTPH2DQ Vn{K}{z},Wh|B16{sae} nil [evex m:5 p:2 l:x w:0 0x5B /r] s:AVX512FP16, t:AVX512FP16, l:hv, e:E2, w:W|R|R
VSUBPH Vn{K}{z},Hn,Wn|B16{sae} nil [evex m:5 p:0 l:x w:0 0x5C /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R
VSUBSH Vdq{K}{z},Hdq,Wsh{sae} nil [evex m:5 p:2 l:i w:0 0x5C /r] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R
VMINPH Vn{K}{z},Hn,Wn|B16{sae} nil [evex m:5 p:0 l:x w:0 0x5D /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R
VMINSH Vdq{K}{z},Hdq,Wsh{sae} nil [evex m:5 p:2 l:i w:0 0x5D /r] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R
VDIVPH Vn{K}{z},Hn,Wn|B16{er} nil [evex m:5 p:0 l:x w:0 0x5E /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R
VDIVSH Vdq{K}{z},Hdq,Wsh{er} nil [evex m:5 p:2 l:i w:0 0x5E /r] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R
VMAXPH Vn{K}{z},Hn,Wn|B16{sae} nil [evex m:5 p:0 l:x w:0 0x5F /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R
VMAXSH Vdq{K}{z},Hdq,Wsh{sae} nil [evex m:5 p:2 l:i w:0 0x5F /r] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R
# 0x60 - 0x6F
VMOVW Vdq,Mw nil [evex m:5 p:1 l:0 w:i 0x6E /r:mem] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E9NF, w:W|R
VMOVW Vdq,Rd nil [evex m:5 p:1 l:0 w:i 0x6E /r:reg] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E9NF, w:W|R
# 0x70 - 0x7F
VCVTTPH2UDQ Vn{K}{z},Wh|B16{sae} nil [evex m:5 p:0 l:x w:0 0x78 /r] s:AVX512FP16, t:AVX512FP16, l:hv, e:E2, w:W|R|R
VCVTTPH2UQQ Vn{K}{z},Wf|B16{sae} nil [evex m:5 p:1 l:x w:0 0x78 /r] s:AVX512FP16, t:AVX512FP16, l:qv, e:E2, w:W|R|R
VCVTTSH2USI Gy,Wsh{sae} nil [evex m:5 p:2 l:i w:0 0x78 /r] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3NF, w:W|R, a:IWO64
VCVTPH2UDQ Vn{K}{z},Wh|B16{er} nil [evex m:5 p:0 l:x w:0 0x79 /r] s:AVX512FP16, t:AVX512FP16, l:hv, e:E2, w:W|R|R
VCVTPH2UQQ Vn{K}{z},Wf|B16{er} nil [evex m:5 p:1 l:x w:0 0x79 /r] s:AVX512FP16, t:AVX512FP16, l:qv, e:E2, w:W|R|R
VCVTSH2USI Gy,Wsh{er} nil [evex m:5 p:2 l:i w:x 0x79 /r] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3NF, w:W|R, a:IWO64
VCVTUDQ2PH Vh{K}{z},Wn|B32{er} nil [evex m:5 p:3 l:x w:0 0x7A /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R
VCVTUQQ2PH Vf{K}{z},Wn|B64{er} nil [evex m:5 p:3 l:x w:1 0x7A /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R
VCVTTPH2QQ Vn{K}{z},Wf|B16{sae} nil [evex m:5 p:1 l:x w:0 0x7A /r] s:AVX512FP16, t:AVX512FP16, l:qv, e:E2, w:W|R|R
VCVTPH2QQ Vn{K}{z},Wf|B16{er} nil [evex m:5 p:1 l:x w:0 0x7B /r] s:AVX512FP16, t:AVX512FP16, l:qv, e:E2, w:W|R|R
VCVTUSI2SH Vdq,Hdq,Ey{er} nil [evex m:5 p:2 l:i w:x 0x7B /r] s:AVX512FP16, t:AVX512FP16, l:t1s, e:E3NF, w:W|R|R, a:IWO64
VCVTTPH2UW Vn{K}{z},Wn|B16{sae} nil [evex m:5 p:0 l:x w:0 0x7C /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R
VCVTTPH2W Vn{K}{z},Wn|B16{sae} nil [evex m:5 p:1 l:x w:0 0x7C /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R
VCVTPH2UW Vn{K}{z},Wn|B16{er} nil [evex m:5 p:0 l:x w:0 0x7D /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R
VCVTPH2W Vn{K}{z},Wn|B16{er} nil [evex m:5 p:1 l:x w:0 0x7D /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R
VCVTW2PH Vn{K}{z},Wn|B16{er} nil [evex m:5 p:2 l:x w:0 0x7D /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R
VCVTUW2PH Vn{K}{z},Wn|B16{er} nil [evex m:5 p:3 l:x w:0 0x7D /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R
VMOVW Mw,Vdq nil [evex m:5 p:1 l:0 w:i 0x7E /r:mem] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E9NF, w:W|R
VMOVW Rd,Vdq nil [evex m:5 p:1 l:0 w:i 0x7E /r:reg] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E9NF, w:W|R

65
isagenerator/instructions/table_evex6.dat Normal file
View File

@ -0,0 +1,65 @@
# Mnemonic Explicit Operands Implicit Encoding Flags, Prefixes, Set, Category, Class, RW map, Additional ops
#------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
# 0x10 - 0x1F
VCVTSH2SS Vdq{K}{z},Hdq,Wsh{sae} nil [evex m:6 p:0 l:i w:0 0x13 /r] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R
VCVTPH2PSX Vn{K}{z},Wh|B16{sae} nil [evex m:6 p:1 l:x w:0 0x13 /r] s:AVX512FP16, t:AVX512FP16, l:hv, e:E2, w:W|R|R
# 0x20 - 0x2F
VSCALEFPH Vn{K}{z},Hn,Wn|B16{er} nil [evex m:6 p:1 l:x w:0 0x2C /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R
VSCALEFSH Vdq{K}{z},Hdq,Wsh{er} nil [evex m:6 p:1 l:i w:0 0x2D /r] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R
# 0x40 - 0x4F
VGETEXPPH Vn{K}{z},Wn|B16{sae} nil [evex m:6 p:1 l:x w:0 0x42 /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R
VGETEXPSH Vdq{K}{z},Hdq,Wsh{sae} nil [evex m:6 p:1 l:i w:0 0x43 /r] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R
VRCPPH Vn{K}{z},Wn|B16 nil [evex m:6 p:1 l:x w:0 0x4C /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E4, w:W|R|R
VRCPSH Vdq{K}{z},Hdq,Wsh nil [evex m:6 p:1 l:i w:0 0x4D /r] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E10, w:W|R|R|R
VRSQRTPH Vn{K}{z},Wn|B16 nil [evex m:6 p:1 l:x w:0 0x4E /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E4, w:W|R|R
VRSQRTSH Vdq{K}{z},Hdq,Wsh nil [evex m:6 p:1 l:i w:0 0x4F /r] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E10, w:W|R|R|R
# 0x50 - 0x5F
VFMADDCPH Vn{K}{z},Hn,Wn|B32{er} nil [evex m:6 p:2 l:x w:0 0x56 /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E4S, w:RW|R|R|R
VFCMADDCPH Vn{K}{z},Hn,Wn|B32{er} nil [evex m:6 p:3 l:x w:0 0x56 /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E4S, w:RW|R|R|R
VFMADDCSH Vdq{K}{z},Hdq,Wd{er} nil [evex m:6 p:2 l:i w:0 0x57 /r] s:AVX512FP16, t:AVX512FP16, l:t1s, e:E10S, w:RW|R|R|R
VFCMADDCSH Vdq{K}{z},Hdq,Wd{er} nil [evex m:6 p:3 l:i w:0 0x57 /r] s:AVX512FP16, t:AVX512FP16, l:t1s, e:E10S, w:RW|R|R|R
# 0x90 - 0x9F
VFMADDSUB132PH Vn{K}{z},Hn,Wn|B16{er} nil [evex m:6 p:1 l:x w:0 0x96 /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
VFMSUBADD132PH Vn{K}{z},Hn,Wn|B16{er} nil [evex m:6 p:1 l:x w:0 0x97 /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
VFMADD132PH Vn{K}{z},Hn,Wn|B16{er} nil [evex m:6 p:1 l:x w:0 0x98 /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
VFMADD132SH Vdq{K}{z},Hdq,Wsh{er} nil [evex m:6 p:1 l:i w:0 0x99 /r] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R
VFMSUB132PH Vn{K}{z},Hn,Wn|B16{er} nil [evex m:6 p:1 l:x w:0 0x9A /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
VFMSUB132SH Vdq{K}{z},Hdq,Wsh{er} nil [evex m:6 p:1 l:i w:0 0x9B /r] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R
VFNMADD132PH Vn{K}{z},Hn,Wn|B16{er} nil [evex m:6 p:1 l:x w:0 0x9C /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
VFNMADD132SH Vdq{K}{z},Hdq,Wsh{er} nil [evex m:6 p:1 l:i w:0 0x9D /r] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R
VFNMSUB132PH Vn{K}{z},Hn,Wn|B16{er} nil [evex m:6 p:1 l:x w:0 0x9E /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
VFNMSUB132SH Vdq{K}{z},Hdq,Wsh{er} nil [evex m:6 p:1 l:i w:0 0x9F /r] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R
# 0xA0 - 0xAF
VFMADDSUB213PH Vn{K}{z},Hn,Wn|B16{er} nil [evex m:6 p:1 l:x w:0 0xA6 /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
VFMSUBADD213PH Vn{K}{z},Hn,Wn|B16{er} nil [evex m:6 p:1 l:x w:0 0xA7 /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
VFMADD213PH Vn{K}{z},Hn,Wn|B16{er} nil [evex m:6 p:1 l:x w:0 0xA8 /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
VFMADD213SH Vdq{K}{z},Hdq,Wsh{er} nil [evex m:6 p:1 l:i w:0 0xA9 /r] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R
VFMSUB213PH Vn{K}{z},Hn,Wn|B16{er} nil [evex m:6 p:1 l:x w:0 0xAA /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
VFMSUB213SH Vdq{K}{z},Hdq,Wsh{er} nil [evex m:6 p:1 l:i w:0 0xAB /r] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R
VFNMADD213PH Vn{K}{z},Hn,Wn|B16{er} nil [evex m:6 p:1 l:x w:0 0xAC /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
VFNMADD213SH Vdq{K}{z},Hdq,Wsh{er} nil [evex m:6 p:1 l:i w:0 0xAD /r] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R
VFNMSUB213PH Vn{K}{z},Hn,Wn|B16{er} nil [evex m:6 p:1 l:x w:0 0xAE /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
VFNMSUB213SH Vdq{K}{z},Hdq,Wsh{er} nil [evex m:6 p:1 l:i w:0 0xAF /r] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R
# 0xB0 - 0xBF
VFMADDSUB231PH Vn{K}{z},Hn,Wn|B16{er} nil [evex m:6 p:1 l:x w:0 0xB6 /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
VFMSUBADD231PH Vn{K}{z},Hn,Wn|B16{er} nil [evex m:6 p:1 l:x w:0 0xB7 /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
VFMADD231PH Vn{K}{z},Hn,Wn|B16{er} nil [evex m:6 p:1 l:x w:0 0xB8 /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
VFMADD231SH Vdq{K}{z},Hdq,Wsh{er} nil [evex m:6 p:1 l:i w:0 0xB9 /r] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R
VFMSUB231PH Vn{K}{z},Hn,Wn|B16{er} nil [evex m:6 p:1 l:x w:0 0xBA /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
VFMSUB231SH Vdq{K}{z},Hdq,Wsh{er} nil [evex m:6 p:1 l:i w:0 0xBB /r] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R
VFNMADD231PH Vn{K}{z},Hn,Wn|B16{er} nil [evex m:6 p:1 l:x w:0 0xBC /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
VFNMADD231SH Vdq{K}{z},Hdq,Wsh{er} nil [evex m:6 p:1 l:i w:0 0xBD /r] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R
VFNMSUB231PH Vn{K}{z},Hn,Wn|B16{er} nil [evex m:6 p:1 l:x w:0 0xBE /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
VFNMSUB231SH Vdq{K}{z},Hdq,Wsh{er} nil [evex m:6 p:1 l:i w:0 0xBF /r] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R
# 0xD0 - 0xD7
VFMULCPH Vn{K}{z},Hn,Wn|B32{er} nil [evex m:6 p:2 l:x w:0 0xD6 /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E4S, w:W|R|R|R
VFCMULCPH Vn{K}{z},Hn,Wn|B32{er} nil [evex m:6 p:3 l:x w:0 0xD6 /r] s:AVX512FP16, t:AVX512FP16, l:fv, e:E4S, w:W|R|R|R
VFMULCSH Vdq{K}{z},Hdq,Wd{er} nil [evex m:6 p:2 l:i w:0 0xD7 /r] s:AVX512FP16, t:AVX512FP16, l:t1s, e:E10S, w:W|R|R|R
VFCMULCSH Vdq{K}{z},Hdq,Wd{er} nil [evex m:6 p:3 l:i w:0 0xD7 /r] s:AVX512FP16, t:AVX512FP16, l:t1s, e:E10S, w:W|R|R|R

20
isagenerator/instructions/table_vex1.dat
View File

@ -39,14 +39,14 @@ VMOVAPS Vx,Wx nil [vex m:1 p:0 l:x w:i
VMOVAPD Vx,Wx nil [vex m:1 p:1 l:x w:i 0x28 /r] s:AVX, t:DATAXFER, w:W|R, e:1
VMOVAPS Wx,Vx nil [vex m:1 p:0 l:x w:i 0x29 /r] s:AVX, t:DATAXFER, w:W|R, e:1
VMOVAPD Wx,Vx nil [vex m:1 p:1 l:x w:i 0x29 /r] s:AVX, t:DATAXFER, w:W|R, e:1
VCVTSI2SS Vss,Hss,Ey nil [vex m:1 p:2 l:i w:x 0x2A /r] s:AVX, t:CONVERT, w:W|R|R, e:3
VCVTSI2SD Vsd,Hsd,Ey nil [vex m:1 p:3 l:i w:x 0x2A /r] s:AVX, t:CONVERT, w:W|R|R, e:3
VCVTSI2SS Vss,Hss,Ey nil [vex m:1 p:2 l:i w:x 0x2A /r] s:AVX, t:CONVERT, w:W|R|R, e:3, a:IWO64
VCVTSI2SD Vsd,Hsd,Ey nil [vex m:1 p:3 l:i w:x 0x2A /r] s:AVX, t:CONVERT, w:W|R|R, e:3, a:IWO64
VMOVNTPS Mx,Vx nil [vex m:1 p:0 l:x w:i 0x2B /r:mem] s:AVX, t:AVX, w:W|R, e:1
VMOVNTPD Mx,Vx nil [vex m:1 p:1 l:x w:i 0x2B /r:mem] s:AVX, t:AVX, w:W|R, e:1
VCVTTSS2SI Gy,Wss nil [vex m:1 p:2 l:i w:x 0x2C /r] s:AVX, t:CONVERT, w:W|R, e:3
VCVTTSD2SI Gy,Wsd nil [vex m:1 p:3 l:i w:x 0x2C /r] s:AVX, t:CONVERT, w:W|R, e:3
VCVTSS2SI Gy,Wss nil [vex m:1 p:2 l:i w:x 0x2D /r] s:AVX, t:CONVERT, w:W|R, e:3
VCVTSD2SI Gy,Wsd nil [vex m:1 p:3 l:i w:x 0x2D /r] s:AVX, t:CONVERT, w:W|R, e:3
VCVTTSS2SI Gy,Wss nil [vex m:1 p:2 l:i w:x 0x2C /r] s:AVX, t:CONVERT, w:W|R, e:3, a:IWO64
VCVTTSD2SI Gy,Wsd nil [vex m:1 p:3 l:i w:x 0x2C /r] s:AVX, t:CONVERT, w:W|R, e:3, a:IWO64
VCVTSS2SI Gy,Wss nil [vex m:1 p:2 l:i w:x 0x2D /r] s:AVX, t:CONVERT, w:W|R, e:3, a:IWO64
VCVTSD2SI Gy,Wsd nil [vex m:1 p:3 l:i w:x 0x2D /r] s:AVX, t:CONVERT, w:W|R, e:3, a:IWO64
VUCOMISS Vss,Wss Fv [vex m:1 p:0 l:i w:i 0x2E /r] s:AVX, t:AVX, w:R|R|W, f:COMIS, e:3
VUCOMISD Vsd,Wsd Fv [vex m:1 p:1 l:i w:i 0x2E /r] s:AVX, t:AVX, w:R|R|W, f:COMIS, e:3
VCOMISS Vss,Wss Fv [vex m:1 p:0 l:i w:i 0x2F /r] s:AVX, t:AVX, w:R|R|W, f:COMIS, e:3
@ -187,8 +187,8 @@ VPUNPCKHDQ Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i
VPACKSSDW Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0x6B /r] s:AVX, t:AVX, w:W|R|R, e:4
VPUNPCKLQDQ Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0x6C /r] s:AVX, t:AVX, w:W|R|R, e:4
VPUNPCKHQDQ Vx,Hx,Wx nil [vex m:1 p:1 l:x w:i 0x6D /r] s:AVX, t:AVX, w:W|R|R, e:4
VMOVD Vdq,Ey nil [vex m:1 p:1 l:0 w:0 0x6E /r] s:AVX, t:DATAXFER, w:W|R, e:5
VMOVQ Vdq,Ey nil [vex m:1 p:1 l:0 w:1 0x6E /r] s:AVX, t:DATAXFER, w:W|R, e:5
VMOVD Vdq,Ey nil [vex m:1 p:1 l:0 w:0 0x6E /r] s:AVX, t:DATAXFER, w:W|R, e:5, a:IWO64
VMOVQ Vdq,Ey nil [vex m:1 p:1 l:0 w:1 0x6E /r] s:AVX, t:DATAXFER, w:W|R, e:5, a:IWO64
VMOVDQA Vx,Wx nil [vex m:1 p:1 l:x w:i 0x6F /r] s:AVX, t:DATAXFER, w:W|R, e:1
VMOVDQU Vx,Wx nil [vex m:1 p:2 l:x w:i 0x6F /r] s:AVX, t:DATAXFER, w:W|R, e:4
@ -207,8 +207,8 @@ VHADDPD Vpd,Hpd,Wpd nil [vex m:1 p:1 l:x w:i
VHADDPS Vps,Hps,Wps nil [vex m:1 p:3 l:x w:i 0x7C /r] s:AVX, t:AVX, w:W|R|R, e:2
VHSUBPD Vpd,Hpd,Wpd nil [vex m:1 p:1 l:x w:i 0x7D /r] s:AVX, t:AVX, w:W|R|R, e:2
VHSUBPS Vps,Hps,Wps nil [vex m:1 p:3 l:x w:i 0x7D /r] s:AVX, t:AVX, w:W|R|R, e:2
VMOVD Ey,Vd nil [vex m:1 p:1 l:0 w:0 0x7E /r] s:AVX, t:DATAXFER, w:W|R, e:5
VMOVQ Ey,Vq nil [vex m:1 p:1 l:0 w:1 0x7E /r] s:AVX, t:DATAXFER, w:W|R, e:5
VMOVD Ey,Vd nil [vex m:1 p:1 l:0 w:0 0x7E /r] s:AVX, t:DATAXFER, w:W|R, e:5, a:IWO64
VMOVQ Ey,Vq nil [vex m:1 p:1 l:0 w:1 0x7E /r] s:AVX, t:DATAXFER, w:W|R, e:5, a:IWO64
VMOVQ Vdq,Wq nil [vex m:1 p:2 l:0 w:i 0x7E /r] s:AVX, t:DATAXFER, w:W|R, e:5
VMOVDQA Wx,Vx nil [vex m:1 p:1 l:x w:i 0x7F /r] s:AVX, t:DATAXFER, w:W|R, e:1
VMOVDQU Wx,Vx nil [vex m:1 p:2 l:x w:i 0x7F /r] s:AVX, t:DATAXFER, w:W|R, e:4

8
isagenerator/instructions/table_vex3.dat
View File

@ -21,8 +21,8 @@ VPEXTRB Mb,Vdq,Ib nil [vex m:3 p:1 l:0 w:i
VPEXTRB Rd,Vdq,Ib nil [vex m:3 p:1 l:0 w:i 0x14 /r:reg ib] s:AVX, t:AVX, w:W|R|R, e:5
VPEXTRW Mw,Vdq,Ib nil [vex m:3 p:1 l:0 w:i 0x15 /r:mem ib] s:AVX, t:AVX, w:W|R|R, e:5
VPEXTRW Rd,Vdq,Ib nil [vex m:3 p:1 l:0 w:i 0x15 /r:reg ib] s:AVX, t:AVX, w:W|R|R, e:5
VPEXTRD Ey,Vdq,Ib nil [vex m:3 p:1 l:0 w:0 0x16 /r ib] s:AVX, t:AVX, w:W|R|R, e:5
VPEXTRQ Ey,Vdq,Ib nil [vex m:3 p:1 l:0 w:1 0x16 /r ib] s:AVX, t:AVX, w:W|R|R, e:5
VPEXTRD Ey,Vdq,Ib nil [vex m:3 p:1 l:0 w:0 0x16 /r ib] s:AVX, t:AVX, w:W|R|R, e:5, a:IWO64
VPEXTRQ Ey,Vdq,Ib nil [vex m:3 p:1 l:0 w:1 0x16 /r ib] s:AVX, t:AVX, w:W|R|R, e:5, a:IWO64
VEXTRACTPS Md,Vdq,Ib nil [vex m:3 p:1 l:0 w:i 0x17 /r:mem ib] s:AVX, t:AVX, w:W|R|R, e:5
VEXTRACTPS Ry,Vdq,Ib nil [vex m:3 p:1 l:0 w:i 0x17 /r:reg ib] s:AVX, t:AVX, w:W|R|R, e:5
VINSERTF128 Vqq,Hqq,Wdq,Ib nil [vex m:3 p:1 l:1 w:0 0x18 /r ib] s:AVX, t:AVX, w:W|R|R|R, e:6
@ -35,8 +35,8 @@ VPINSRB Vdq,Hdq,Mb,Ib nil [vex m:3 p:1 l:0 w:i
VPINSRB Vdq,Hdq,Rd,Ib nil [vex m:3 p:1 l:0 w:i 0x20 /r:reg ib] s:AVX, t:AVX, w:W|R|R|R, e:5
VINSERTPS Vdq,Hdq,Md,Ib nil [vex m:3 p:1 l:0 w:i 0x21 /r:mem ib] s:AVX, t:AVX, w:W|R|R|R, e:5
VINSERTPS Vdq,Hdq,Udq,Ib nil [vex m:3 p:1 l:0 w:i 0x21 /r:reg ib] s:AVX, t:AVX, w:W|R|R|R, e:5
VPINSRD Vdq,Hdq,Ey,Ib nil [vex m:3 p:1 l:0 w:0 0x22 /r ib] s:AVX, t:AVX, w:W|R|R|R, e:5
VPINSRQ Vdq,Hdq,Ey,Ib nil [vex m:3 p:1 l:0 w:1 0x22 /r ib] s:AVX, t:AVX, w:W|R|R|R, e:5
VPINSRD Vdq,Hdq,Ey,Ib nil [vex m:3 p:1 l:0 w:0 0x22 /r ib] s:AVX, t:AVX, w:W|R|R|R, e:5, a:IWO64
VPINSRQ Vdq,Hdq,Ey,Ib nil [vex m:3 p:1 l:0 w:1 0x22 /r ib] s:AVX, t:AVX, w:W|R|R|R, e:5, a:IWO64
# 0x30 - 0x3F
KSHIFTRW rKw,mKw,Ib nil [vex m:3 p:1 l:0 w:1 0x30 /r:reg ib] s:AVX512F, t:KMASK, c:KSHIFTR, w:W|R|R, e:K20

2
isagenerator/isagenerator.vcxproj
View File

@ -151,6 +151,8 @@
<None Include="instructions\table_evex1.dat" />
<None Include="instructions\table_evex2.dat" />
<None Include="instructions\table_evex3.dat" />
<None Include="instructions\table_evex5.dat" />
<None Include="instructions\table_evex6.dat" />
<None Include="instructions\table_fpu.dat" />
<None Include="instructions\table_vex1.dat" />
<None Include="instructions\table_vex2.dat" />

6
isagenerator/isagenerator.vcxproj.filters
View File

@ -75,6 +75,12 @@
<None Include="instructions\table_xop.dat">
<Filter>data</Filter>
</None>
<None Include="instructions\table_evex5.dat">
<Filter>data</Filter>
</None>
<None Include="instructions\table_evex6.dat">
<Filter>data</Filter>
</None>
</ItemGroup>
<ItemGroup>
<Text Include="instructions\help.txt">

2
pybddisasm/setup.py
View File

@ -12,7 +12,7 @@ from setuptools import find_packages, setup, Command, Extension, Distribution
from codecs import open
VERSION = (0, 1, 3)
LIBRARY_VERSION = (1, 32, 5)
LIBRARY_VERSION = (1, 33, 0)
LIBRARY_INSTRUX_SIZE = 864
packages = ['pybddisasm']