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bddisasm
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- Add support for AVX512-FP16 instructions, as per https://software.intel.com/content/www/us/en/develop/download/intel-avx512-fp16-architecture-specification.html
- Bug fix: zeroing with no masking is not supported, so return an error if we encounter such encodings
- Bug fix: ignore VEX/EVEX.W field outside 64 bit mode for some instructions
- Several other minor fixes and improvements
pull/52/head v1.33.0
Andrei Vlad LUTAS 2 years ago
parent 5b8b67c596
commit 76d92e73c2
86 changed files with 520640 additions and 151099 deletions
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341
bddisasm/bddisasm.c
Unescape View File

@ -619,7 +619,7 @@ NdFetchEvex(
return ND_STATUS_EVEX_WITH_PREFIX;
}
// Do the opcode independent checks. Opcode dependent checks are done when decoding each
// Do the opcode independent checks. Opcode dependent checks are done when decoding each instruction.
if (Instrux->Evex.zero != 0 || Instrux->Evex.one != 1 || Instrux->Evex.m == 0)
{
return ND_STATUS_INVALID_ENCODING;
@ -1242,25 +1242,32 @@ NdGetCompDispSize(
uint32_t MemSize
)
{
static const uint8_t fvszLut[2][2][4] =
{
{ { 16, 32, 64, 0 }, { 4, 4, 4, 0 }, },
{ { 16, 32, 64, 0 }, { 8, 8, 8, 0 }, },
};
static const uint8_t hvszLut[2][4] = { { 8, 16, 32, 0 }, { 4, 4, 4, 0 }, };
static const uint8_t fvszLut[4] = { 16, 32, 64, 0 };
static const uint8_t hvszLut[4] = { 8, 16, 32, 0 };
static const uint8_t qvszLut[4] = { 4, 8, 16, 0 };
static const uint8_t dupszLut[4] = { 8, 32, 64, 0 };
static const uint8_t fvmszLut[4] = { 16, 32, 64, 0 };
static const uint8_t hvmszLut[4] = { 8, 16, 32, 0 };
static const uint8_t qvmszLut[4] = { 4, 8, 16, 0 };
static const uint8_t ovmszLut[4] = { 2, 4, 8, 0 };
if (Instrux->HasBroadcast)
{
// If the instruction uses broadcast, then compressed displacement will use the size of the element as scale:
// - 2 when broadcasting 16 bit
// - 4 when broadcasting 32 bit
// - 8 when broadcasting 64 bit
return (uint8_t)MemSize;
}
switch (Instrux->TupleType)
{
case ND_TUPLE_FV:
return fvszLut[Instrux->Exs.w][Instrux->Exs.bm][Instrux->Exs.l];
return fvszLut[Instrux->Exs.l];
case ND_TUPLE_HV:
return hvszLut[Instrux->Exs.bm][Instrux->Exs.l];
return hvszLut[Instrux->Exs.l];
case ND_TUPLE_QV:
return qvszLut[Instrux->Exs.l];
case ND_TUPLE_DUP:
return dupszLut[Instrux->Exs.l];
case ND_TUPLE_FVM:
@ -1601,7 +1608,8 @@ NdParseOperand(
case ND_OPS_pd:
case ND_OPS_ps:
// packed double or packed single precision values.
case ND_OPS_ph:
// packed double or packed single or packed FP16 values.
{
static const uint8_t szLut[3] = { ND_SIZE_128BIT, ND_SIZE_256BIT, ND_SIZE_512BIT };
@ -1609,14 +1617,19 @@ NdParseOperand(
}
break;
case ND_OPS_sd:
// Scalar double.
size = ND_SIZE_64BIT;
break;
case ND_OPS_ss:
// Scalar single.
size = ND_SIZE_32BIT;
break;
case ND_OPS_sd:
// Scalar double.
size = ND_SIZE_64BIT;
case ND_OPS_sh:
// Scalar FP16.
size = ND_SIZE_16BIT;
break;
case ND_OPS_mib:
@ -2315,11 +2328,6 @@ NdParseOperand(
case ND_OPT_G:
// General purpose register encoded in modrm.reg.
if (Instrux->Exs.rp == 1)
{
return ND_STATUS_INVALID_ENCODING;
}
operand->Type = ND_OP_REG;
operand->Info.Register.Type = ND_REG_GPR;
operand->Info.Register.Size = (ND_REG_SIZE)size;
@ -2712,48 +2720,47 @@ memory:
// sibmem requires SIB to be present.
if (!Instrux->HasSib)
{
return ND_STATUS_INVALID_ENCODING;
return ND_STATUS_SIBMEM_WITHOUT_SIB;
}
operand->Info.Memory.IsSibMem = true;
}
if (Instrux->HasEvex)
// If we have broadcast, the operand size is fixed to either 16, 32 or 64 bit, depending on bcast size.
// Therefore, we will override the rawSize with either 16, 32 or 64 bits. Note that bcstSize will save the
// total size of the access, and it will be used to compute the number of broadcasted elements:
// bcstSize / rawSize.
if (Instrux->HasBroadcast)
{
// Handle compressed displacement, if any. Note that most EVEX instructions with 8 bit displacement
// use compressed displacement addressing.
if ((Instrux->HasDisp) && (ND_SIZE_8BIT == Instrux->DispLength))
{
Instrux->HasCompDisp = true;
operand->Info.Memory.HasBroadcast = true;
operand->Info.Memory.HasCompDisp = true;
operand->Info.Memory.CompDispSize = NdGetCompDispSize(Instrux, operand->Size);
if (opd & ND_OPD_B32)
{
size = ND_SIZE_32BIT;
}
// If we have broadcast, the operand size is fixed to either 32 bit, either 64 bit, depending on bcast size.
// Therefore, we will override the rawSize with either 32 or 64 bits. Note that bcstSize will save the total
// size of the access, and it will be used to compute the number of broadcasted elements: bcstSize / rawSize.
if ((Instrux->Exs.bm) && (opd & (ND_OPD_B32 | ND_OPD_B64)))
else if (opd & ND_OPD_B64)
{
size = ND_SIZE_64BIT;
}
else if (opd & ND_OPD_B16)
{
Instrux->HasBroadcast = true;
operand->Info.Memory.HasBroadcast = true;
size = ND_SIZE_16BIT;
}
else
{
size = width ? ND_SIZE_64BIT : ND_SIZE_32BIT;
}
if (opd & ND_OPD_B32)
{
size = ND_SIZE_32BIT;
}
else if (opd & ND_OPD_B64)
{
size = ND_SIZE_64BIT;
}
else
{
size = width ? ND_SIZE_64BIT : ND_SIZE_32BIT;
}
// Override operand size.
operand->Size = operand->RawSize = size;
}
// Override operand size.
operand->Size = operand->RawSize = size;
}
// Handle compressed displacement, if any. Note that most EVEX instructions with 8 bit displacement
// use compressed displacement addressing.
if (Instrux->HasCompDisp)
{
operand->Info.Memory.HasCompDisp = true;
operand->Info.Memory.CompDispSize = NdGetCompDispSize(Instrux, operand->Size);
}
// MIB, if any. Used by some MPX instructions.
@ -3122,23 +3129,26 @@ memory:
{
// Check for mask register. Mask if present only if the operand supports masking and if the
// mask register is not k0 (which implies "no masking").
if ((opd & ND_OPD_MASK) && (Instrux->Exs.k != 0))
if ((opd & ND_OPD_MASK) && (Instrux->HasMask))
{
operand->Decorator.HasMask = true;
operand->Decorator.Mask.Msk = (uint8_t)Instrux->Exs.k;
Instrux->HasMask = true;
}
// Check for zeroing. The operand must support zeroing and the z bit inside vex3 must be set. Note that
// Check for zeroing. The operand must support zeroing and the z bit inside evex3 must be set. Note that
// zeroing is allowed only for register destinations, and NOT for memory.
if ((opd & ND_OPD_Z) && (Instrux->Exs.z) && (operand->Type != ND_OP_MEM))
if ((opd & ND_OPD_Z) && (Instrux->HasZero))
{
if (operand->Type == ND_OP_MEM)
{
return ND_STATUS_ZEROING_ON_MEMORY;
}
operand->Decorator.HasZero = true;
Instrux->HasZero = true;
}
// Check for broadcast again. We've already filled the broadcast size before parsing the op size.
if (((opd & ND_OPD_B32) || (opd & ND_OPD_B64)) && (Instrux->Exs.bm) && (Instrux->ModRm.mod != 3))
if ((opd & ND_OPD_BCAST) && (Instrux->HasBroadcast))
{
operand->Decorator.HasBroadcast = true;
operand->Decorator.Broadcast.Size = (uint8_t)operand->Size;
@ -3554,6 +3564,10 @@ NdFindInstruction(
pTable = (const ND_TABLE *)pTable->Table[Instrux->Exs.w];
break;
case ND_ILUT_VEX_WI:
pTable = (const ND_TABLE *)pTable->Table[Instrux->DefCode == ND_CODE_64 ? Instrux->Exs.w : 0];
break;
default:
status = ND_STATUS_INTERNAL_ERROR;
stop = true;
@ -3637,11 +3651,13 @@ NdGetVectorLength(
INSTRUX *Instrux
)
{
if (Instrux->HasEvex && Instrux->Exs.bm && (Instrux->ModRm.mod == 3) &&
(ND_ER_SUPPORT(Instrux) || ND_SAE_SUPPORT(Instrux) || !!(Instrux->Attributes & ND_FLAG_IER)))
if (Instrux->HasEr || Instrux->HasSae || Instrux->HasIgnEr)
{
// Embedded rounding present, force the vector length to 512.
if ((Instrux->TupleType == ND_TUPLE_T1S) || (Instrux->TupleType == ND_TUPLE_T1F))
// Embedded rounding or SAE present, force the vector length to 512 or scalar.
if ((Instrux->TupleType == ND_TUPLE_T1S) ||
(Instrux->TupleType == ND_TUPLE_T1S8) ||
(Instrux->TupleType == ND_TUPLE_T1S16) ||
(Instrux->TupleType == ND_TUPLE_T1F))
{
Instrux->VecMode = Instrux->EfVecMode = ND_VECM_128;
}
@ -3653,7 +3669,7 @@ NdGetVectorLength(
return ND_STATUS_SUCCESS;
}
// Decode VEX vector length. Also take into consideration the "ignore L" flag.
// Decode EVEX vector length. Also take into consideration the "ignore L" flag.
switch (Instrux->Exs.l)
{
case 0:
@ -3669,7 +3685,13 @@ NdGetVectorLength(
Instrux->EfVecMode = (Instrux->Attributes & ND_FLAG_LIG) ? ND_VECM_128 : ND_VECM_512;
break;
default:
return ND_STATUS_INVALID_INSTRUX;
return ND_STATUS_BAD_EVEX_LL;
}
// Some instructions don't support 128 bit vectors.
if ((ND_VECM_128 == Instrux->EfVecMode) && (0 != (Instrux->Attributes & ND_FLAG_NOL0)))
{
return ND_STATUS_INVALID_ENCODING;
}
return ND_STATUS_SUCCESS;
@ -3718,6 +3740,12 @@ NdGetEffectiveOpMode(
static const uint8_t szLut[3] = { ND_SIZE_16BIT, ND_SIZE_32BIT, ND_SIZE_64BIT };
bool width, f64, d64, has66;
if ((ND_CODE_64 != Instrux->DefCode) && !!(Instrux->Attributes & ND_FLAG_IWO64))
{
// Some instructions ignore VEX/EVEX.W field outside 64 bit mode, and treat it as 0.
Instrux->Exs.w = 0;
}
// Extract the flags.
width = (0 != Instrux->Exs.w) && !(Instrux->Attributes & ND_FLAG_WIG);
// In 64 bit mode, the operand is forced to 64 bit. Size-changing prefixes are ignored.
@ -3755,6 +3783,108 @@ NdGetEffectiveOpMode(
}
//
// NdPostProcessEvex
//
static NDSTATUS
NdPostProcessEvex(
INSTRUX *Instrux
)
{
// Handle embedded broadcast/rounding-control.
if (Instrux->Exs.bm == 1)
{
if (Instrux->ModRm.mod == 3)
{
// reg form for the instruction, check for ER or SAE support.
if (Instrux->ValidDecorators.Er)
{
Instrux->HasEr = 1;
Instrux->HasSae = 1;
Instrux->RoundingMode = (uint8_t)Instrux->Exs.l;
}
else if (Instrux->ValidDecorators.Sae)
{
Instrux->HasSae = 1;
}
else if (!!(Instrux->Attributes & ND_FLAG_IER))
{
// The encoding behaves as if embedded rounding is enabled, but it is in fact ignored.
Instrux->HasIgnEr = 1;
}
else
{
return ND_STATUS_ER_SAE_NOT_SUPPORTED;
}
}
else
{
// mem form for the instruction, check for broadcast.
if (Instrux->ValidDecorators.Broadcast)
{
Instrux->HasBroadcast = 1;
}
else
{
return ND_STATUS_BROADCAST_NOT_SUPPORTED;
}
}
}
// Handle masking.
if (Instrux->Exs.k != 0)
{
if (Instrux->ValidDecorators.Mask)
{
Instrux->HasMask = 1;
}
else
{
return ND_STATUS_MASK_NOT_SUPPORTED;
}
}
else
{
if (!!(Instrux->Attributes & ND_FLAG_MMASK))
{
return ND_STATUS_MASK_REQUIRED;
}
}
// Handle zeroing.
if (Instrux->Exs.z != 0)
{
if (Instrux->ValidDecorators.Zero)
{
// Zeroing restrictions:
// - valid with register only;
// - valid only if masking is also used;
if (Instrux->HasMask)
{
Instrux->HasZero = 1;
}
else
{
return ND_STATUS_ZEROING_NO_MASK;
}
}
else
{
return ND_STATUS_ZEROING_NOT_SUPPORTED;
}
}
// EVEX instructions with 8 bit displacement use compressed displacement addressing, where the displacement
// is scaled according to the data type accessed by the instruction.
if (Instrux->HasDisp && Instrux->DispLength == 1)
{
Instrux->HasCompDisp = true;
}
return ND_STATUS_SUCCESS;
}
//
// NdValidateInstruction
//
@ -3797,12 +3927,6 @@ NdValidateInstruction(
return ND_STATUS_BAD_EVEX_V_PRIME;
}
// Some instructions don't support 128 bit vectors.
if ((ND_VECM_128 == Instrux->EfVecMode) && (0 != (Instrux->Attributes & ND_FLAG_NOL0)))
{
return ND_STATUS_INVALID_ENCODING;
}
// VSIB instructions have a restriction: the same vector register can't be used by more than one operand.
// The exception is SCATTER*, which can use the VSIB reg as two sources.
if (ND_HAS_VSIB(Instrux) && Instrux->Category != ND_CAT_SCATTER)
@ -3839,7 +3963,7 @@ NdValidateInstruction(
Instrux->Operands[0].Info.Register.Reg == Instrux->Operands[2].Info.Register.Reg ||
Instrux->Operands[1].Info.Register.Reg == Instrux->Operands[2].Info.Register.Reg)
{
return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION;
return ND_STATUS_INVALID_TILE_REGS;
}
}
else
@ -3852,50 +3976,29 @@ NdValidateInstruction(
}
}
if (Instrux->HasEvex)
// Handle EVEX exception class.
if (Instrux->ExceptionClass == ND_EXC_EVEX)
{
// Instructions that don't support masking must have EVEX.aaa = 0.
if (!ND_MASK_SUPPORT(Instrux) && (0 != Instrux->Exs.k))
// If E4* or E10* exception class is used (check out AVX512-FP16 instructions), an additional #UD case
// exists: if the destination register is equal to either of the source registers.
if (Instrux->ExceptionType == ND_EXT_E4S || Instrux->ExceptionType == ND_EXT_E10S)
{
return ND_STATUS_MASK_NOT_SUPPORTED;
}
// Note that operand 0 is the destination, operand 1 is the mask, operand 2 is first source, operand
// 3 is the second source.
// Some instructions have mandatory masking, and using k0 as a mask triggers #UD.
if ((Instrux->Attributes & ND_FLAG_MMASK) && (0 == Instrux->Exs.k))
{
return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION;
}
// EVEX.z must be 0 if:
// - zeroing is not supported by the instruction.
// - zeroing is supported, but the destination is memory.
// If zeroing is supported and the mask is 0, then zeroing is ignored.
if (0 != Instrux->Exs.z)
{
if (!ND_ZERO_SUPPORT(Instrux))
if (Instrux->Operands[0].Type == ND_OP_REG && Instrux->Operands[2].Type == ND_OP_REG &&
Instrux->Operands[0].Info.Register.Reg == Instrux->Operands[2].Info.Register.Reg)
{
return ND_STATUS_ZEROING_NOT_SUPPORTED;
return ND_STATUS_INVALID_DEST_REGS;
}
if (Instrux->Operands[0].Type == ND_OP_MEM)
if (Instrux->Operands[0].Type == ND_OP_REG && Instrux->Operands[3].Type == ND_OP_REG &&
Instrux->Operands[0].Info.Register.Reg == Instrux->Operands[3].Info.Register.Reg)
{
return ND_STATUS_ZEROING_ON_MEMORY;
return ND_STATUS_INVALID_DEST_REGS;
}
}
// EVEX.b must be 0 if SAE/ER is not used, but can be ignored if the ignore embedded rounding flag is set.
if (Instrux->Exs.bm && (Instrux->ModRm.mod == 3) &&
!ND_SAE_SUPPORT(Instrux) && !ND_ER_SUPPORT(Instrux) &&
!(Instrux->Attributes & ND_FLAG_IER))
{
return ND_STATUS_ER_SAE_NOT_SUPPORTED;
}
// EVEX.b must be 0 if broadcast is not supported.
if (Instrux->Exs.bm && (Instrux->ModRm.mod != 3) && !ND_BROADCAST_SUPPORT(Instrux))
{
return ND_STATUS_BROADCAST_NOT_SUPPORTED;
}
}
}
@ -4062,6 +4165,18 @@ NdDecodeWithContext(
return status;
}
if (Instrux->HasEvex)
{
// Post-process EVEX encoded instructions. This does two thing:
// - check and fill in decorator info;
// - generate error for invalid broadcast/rounding, mask or zeroing bits.
status = NdPostProcessEvex(Instrux);
if (!ND_SUCCESS(status))
{
return status;
}
}
if (ND_HAS_VECTOR(Instrux))
{
// Get vector length.
@ -4084,24 +4199,6 @@ NdDecodeWithContext(
Instrux->Condition = Instrux->Predicate = Instrux->PrimaryOpCode & 0xF;
}
if (0 != pIns->ValidDecorators)
{
// Check for suppress all exceptions.
if ((Instrux->ValidDecorators.Sae) && (Instrux->Exs.bm) && (Instrux->ModRm.mod == 3))
{
Instrux->HasSae = true;
}
// Check for embedded rounding. This is available only in reg-reg encodings. Also, if embedded
// rounding is used, the vector length is forced to 512 bit, as the
if ((Instrux->ValidDecorators.Er) && (Instrux->Exs.bm) && (Instrux->ModRm.mod == 3))
{
Instrux->HasEr = true;
Instrux->HasSae = true;
Instrux->RoundingMode = (uint8_t)Instrux->Exs.l;
}
}
Instrux->ExpOperandsCount = ND_EXP_OPS_CNT(pIns->OpsCount);
Instrux->OperandsCount = Instrux->ExpOperandsCount + ND_IMP_OPS_CNT(pIns->OpsCount);

7267
bddisasm/include/instructions.h
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File diff suppressed because it is too large Load Diff

219
bddisasm/include/mnemonics.h
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@ -1,7 +1,7 @@
#ifndef MNEMONICS_H
#define MNEMONICS_H
const char *gMnemonics[1589] =
const char *gMnemonics[1695] =
{
"AAA", "AAD", "AAM", "AAS", "ADC", "ADCX", "ADD", "ADDPD", "ADDPS",
"ADDSD", "ADDSS", "ADDSUBPD", "ADDSUBPS", "ADOX", "AESDEC", "AESDEC128KL",
@ -126,87 +126,105 @@ const char *gMnemonics[1589] =
"TILEZERO", "TLBSYNC", "TPAUSE", "TZCNT", "TZMSK", "UCOMISD",
"UCOMISS", "UD0", "UD1", "UD2", "UIRET", "UMONITOR", "UMWAIT",
"UNPCKHPD", "UNPCKHPS", "UNPCKLPD", "UNPCKLPS", "V4FMADDPS",
"V4FMADDSS", "V4FNMADDPS", "V4FNMADDSS", "VADDPD", "VADDPS",
"VADDSD", "VADDSS", "VADDSUBPD", "VADDSUBPS", "VAESDEC", "VAESDECLAST",
"VAESENC", "VAESENCLAST", "VAESIMC", "VAESKEYGENASSIST", "VALIGND",
"VALIGNQ", "VANDNPD", "VANDNPS", "VANDPD", "VANDPS", "VBLENDMPD",
"VBLENDMPS", "VBLENDPD", "VBLENDPS", "VBLENDVPD", "VBLENDVPS",
"VBROADCASTF128", "VBROADCASTF32X2", "VBROADCASTF32X4", "VBROADCASTF32X8",
"VBROADCASTF64X2", "VBROADCASTF64X4", "VBROADCASTI128", "VBROADCASTI32X2",
"VBROADCASTI32X4", "VBROADCASTI32X8", "VBROADCASTI64X2", "VBROADCASTI64X4",
"VBROADCASTSD", "VBROADCASTSS", "VCMPPD", "VCMPPS", "VCMPSD",
"VCMPSS", "VCOMISD", "VCOMISS", "VCOMPRESSPD", "VCOMPRESSPS",
"VCVTDQ2PD", "VCVTDQ2PS", "VCVTNE2PS2BF16", "VCVTNEPS2BF16",
"VCVTPD2DQ", "VCVTPD2PS", "VCVTPD2QQ", "VCVTPD2UDQ", "VCVTPD2UQQ",
"VCVTPH2PS", "VCVTPS2DQ", "VCVTPS2PD", "VCVTPS2PH", "VCVTPS2QQ",
"VCVTPS2UDQ", "VCVTPS2UQQ", "VCVTQQ2PD", "VCVTQQ2PS", "VCVTSD2SI",
"VCVTSD2SS", "VCVTSD2USI", "VCVTSI2SD", "VCVTSI2SS", "VCVTSS2SD",
"VCVTSS2SI", "VCVTSS2USI", "VCVTTPD2DQ", "VCVTTPD2QQ", "VCVTTPD2UDQ",
"VCVTTPD2UQQ", "VCVTTPS2DQ", "VCVTTPS2QQ", "VCVTTPS2UDQ", "VCVTTPS2UQQ",
"VCVTTSD2SI", "VCVTTSD2USI", "VCVTTSS2SI", "VCVTTSS2USI", "VCVTUDQ2PD",
"VCVTUDQ2PS", "VCVTUQQ2PD", "VCVTUQQ2PS", "VCVTUSI2SD", "VCVTUSI2SS",
"VDBPSADBW", "VDIVPD", "VDIVPS", "VDIVSD", "VDIVSS", "VDPBF16PS",
"VDPPD", "VDPPS", "VERR", "VERW", "VEXP2PD", "VEXP2PS", "VEXPANDPD",
"VEXPANDPS", "VEXTRACTF128", "VEXTRACTF32X4", "VEXTRACTF32X8",
"VEXTRACTF64X2", "VEXTRACTF64X4", "VEXTRACTI128", "VEXTRACTI32X4",
"VEXTRACTI32X8", "VEXTRACTI64X2", "VEXTRACTI64X4", "VEXTRACTPS",
"VFIXUPIMMPD", "VFIXUPIMMPS", "VFIXUPIMMSD", "VFIXUPIMMSS", "VFMADD132PD",
"VFMADD132PS", "VFMADD132SD", "VFMADD132SS", "VFMADD213PD", "VFMADD213PS",
"VFMADD213SD", "VFMADD213SS", "VFMADD231PD", "VFMADD231PS", "VFMADD231SD",
"VFMADD231SS", "VFMADDPD", "VFMADDPS", "VFMADDSD", "VFMADDSS",
"VFMADDSUB132PD", "VFMADDSUB132PS", "VFMADDSUB213PD", "VFMADDSUB213PS",
"VFMADDSUB231PD", "VFMADDSUB231PS", "VFMADDSUBPD", "VFMADDSUBPS",
"VFMSUB132PD", "VFMSUB132PS", "VFMSUB132SD", "VFMSUB132SS", "VFMSUB213PD",
"VFMSUB213PS", "VFMSUB213SD", "VFMSUB213SS", "VFMSUB231PD", "VFMSUB231PS",
"VFMSUB231SD", "VFMSUB231SS", "VFMSUBADD132PD", "VFMSUBADD132PS",
"VFMSUBADD213PD", "VFMSUBADD213PS", "VFMSUBADD231PD", "VFMSUBADD231PS",
"VFMSUBADDPD", "VFMSUBADDPS", "VFMSUBPD", "VFMSUBPS", "VFMSUBSD",
"VFMSUBSS", "VFNMADD132PD", "VFNMADD132PS", "VFNMADD132SD", "VFNMADD132SS",
"VFNMADD213PD", "VFNMADD213PS", "VFNMADD213SD", "VFNMADD213SS",
"VFNMADD231PD", "VFNMADD231PS", "VFNMADD231SD", "VFNMADD231SS",
"VFNMADDPD", "VFNMADDPS", "VFNMADDSD", "VFNMADDSS", "VFNMSUB132PD",
"VFNMSUB132PS", "VFNMSUB132SD", "VFNMSUB132SS", "VFNMSUB213PD",
"VFNMSUB213PS", "VFNMSUB213SD", "VFNMSUB213SS", "VFNMSUB231PD",
"VFNMSUB231PS", "VFNMSUB231SD", "VFNMSUB231SS", "VFNMSUBPD",
"VFNMSUBPS", "VFNMSUBSD", "VFNMSUBSS", "VFPCLASSPD", "VFPCLASSPS",
"VFPCLASSSD", "VFPCLASSSS", "VFRCZPD", "VFRCZPS", "VFRCZSD",
"V4FMADDSS", "V4FNMADDPS", "V4FNMADDSS", "VADDPD", "VADDPH",
"VADDPS", "VADDSD", "VADDSH", "VADDSS", "VADDSUBPD", "VADDSUBPS",
"VAESDEC", "VAESDECLAST", "VAESENC", "VAESENCLAST", "VAESIMC",
"VAESKEYGENASSIST", "VALIGND", "VALIGNQ", "VANDNPD", "VANDNPS",
"VANDPD", "VANDPS", "VBLENDMPD", "VBLENDMPS", "VBLENDPD", "VBLENDPS",
"VBLENDVPD", "VBLENDVPS", "VBROADCASTF128", "VBROADCASTF32X2",
"VBROADCASTF32X4", "VBROADCASTF32X8", "VBROADCASTF64X2", "VBROADCASTF64X4",
"VBROADCASTI128", "VBROADCASTI32X2", "VBROADCASTI32X4", "VBROADCASTI32X8",
"VBROADCASTI64X2", "VBROADCASTI64X4", "VBROADCASTSD", "VBROADCASTSS",
"VCMPPD", "VCMPPH", "VCMPPS", "VCMPSD", "VCMPSH", "VCMPSS", "VCOMISD",
"VCOMISH", "VCOMISS", "VCOMPRESSPD", "VCOMPRESSPS", "VCVTDQ2PD",
"VCVTDQ2PH", "VCVTDQ2PS", "VCVTNE2PS2BF16", "VCVTNEPS2BF16",
"VCVTPD2DQ", "VCVTPD2PH", "VCVTPD2PS", "VCVTPD2QQ", "VCVTPD2UDQ",
"VCVTPD2UQQ", "VCVTPH2DQ", "VCVTPH2PD", "VCVTPH2PS", "VCVTPH2PSX",
"VCVTPH2QQ", "VCVTPH2UDQ", "VCVTPH2UQQ", "VCVTPH2UW", "VCVTPH2W",
"VCVTPS2DQ", "VCVTPS2PD", "VCVTPS2PH", "VCVTPS2PHX", "VCVTPS2QQ",
"VCVTPS2UDQ", "VCVTPS2UQQ", "VCVTQQ2PD", "VCVTQQ2PH", "VCVTQQ2PS",
"VCVTSD2SH", "VCVTSD2SI", "VCVTSD2SS", "VCVTSD2USI", "VCVTSH2SD",
"VCVTSH2SI", "VCVTSH2SS", "VCVTSH2USI", "VCVTSI2SD", "VCVTSI2SH",
"VCVTSI2SS", "VCVTSS2SD", "VCVTSS2SH", "VCVTSS2SI", "VCVTSS2USI",
"VCVTTPD2DQ", "VCVTTPD2QQ", "VCVTTPD2UDQ", "VCVTTPD2UQQ", "VCVTTPH2DQ",
"VCVTTPH2QQ", "VCVTTPH2UDQ", "VCVTTPH2UQQ", "VCVTTPH2UW", "VCVTTPH2W",
"VCVTTPS2DQ", "VCVTTPS2QQ", "VCVTTPS2UDQ", "VCVTTPS2UQQ", "VCVTTSD2SI",
"VCVTTSD2USI", "VCVTTSH2SI", "VCVTTSH2USI", "VCVTTSS2SI", "VCVTTSS2USI",
"VCVTUDQ2PD", "VCVTUDQ2PH", "VCVTUDQ2PS", "VCVTUQQ2PD", "VCVTUQQ2PH",
"VCVTUQQ2PS", "VCVTUSI2SD", "VCVTUSI2SH", "VCVTUSI2SS", "VCVTUW2PH",
"VCVTW2PH", "VDBPSADBW", "VDIVPD", "VDIVPH", "VDIVPS", "VDIVSD",
"VDIVSH", "VDIVSS", "VDPBF16PS", "VDPPD", "VDPPS", "VERR", "VERW",
"VEXP2PD", "VEXP2PS", "VEXPANDPD", "VEXPANDPS", "VEXTRACTF128",
"VEXTRACTF32X4", "VEXTRACTF32X8", "VEXTRACTF64X2", "VEXTRACTF64X4",
"VEXTRACTI128", "VEXTRACTI32X4", "VEXTRACTI32X8", "VEXTRACTI64X2",
"VEXTRACTI64X4", "VEXTRACTPS", "VFCMADDCPH", "VFCMADDCSH", "VFCMULCPH",
"VFCMULCSH", "VFIXUPIMMPD", "VFIXUPIMMPS", "VFIXUPIMMSD", "VFIXUPIMMSS",
"VFMADD132PD", "VFMADD132PH", "VFMADD132PS", "VFMADD132SD", "VFMADD132SH",
"VFMADD132SS", "VFMADD213PD", "VFMADD213PH", "VFMADD213PS", "VFMADD213SD",
"VFMADD213SH", "VFMADD213SS", "VFMADD231PD", "VFMADD231PH", "VFMADD231PS",
"VFMADD231SD", "VFMADD231SH", "VFMADD231SS", "VFMADDCPH", "VFMADDCSH",
"VFMADDPD", "VFMADDPS", "VFMADDSD", "VFMADDSS", "VFMADDSUB132PD",
"VFMADDSUB132PH", "VFMADDSUB132PS", "VFMADDSUB213PD", "VFMADDSUB213PH",
"VFMADDSUB213PS", "VFMADDSUB231PD", "VFMADDSUB231PH", "VFMADDSUB231PS",
"VFMADDSUBPD", "VFMADDSUBPS", "VFMSUB132PD", "VFMSUB132PH", "VFMSUB132PS",
"VFMSUB132SD", "VFMSUB132SH", "VFMSUB132SS", "VFMSUB213PD", "VFMSUB213PH",
"VFMSUB213PS", "VFMSUB213SD", "VFMSUB213SH", "VFMSUB213SS", "VFMSUB231PD",
"VFMSUB231PH", "VFMSUB231PS", "VFMSUB231SD", "VFMSUB231SH", "VFMSUB231SS",
"VFMSUBADD132PD", "VFMSUBADD132PH", "VFMSUBADD132PS", "VFMSUBADD213PD",
"VFMSUBADD213PH", "VFMSUBADD213PS", "VFMSUBADD231PD", "VFMSUBADD231PH",
"VFMSUBADD231PS", "VFMSUBADDPD", "VFMSUBADDPS", "VFMSUBPD", "VFMSUBPS",
"VFMSUBSD", "VFMSUBSS", "VFMULCPH", "VFMULCSH", "VFNMADD132PD",
"VFNMADD132PH", "VFNMADD132PS", "VFNMADD132SD", "VFNMADD132SH",
"VFNMADD132SS", "VFNMADD213PD", "VFNMADD213PH", "VFNMADD213PS",
"VFNMADD213SD", "VFNMADD213SH", "VFNMADD213SS", "VFNMADD231PD",
"VFNMADD231PH", "VFNMADD231PS", "VFNMADD231SD", "VFNMADD231SH",
"VFNMADD231SS", "VFNMADDPD", "VFNMADDPS", "VFNMADDSD", "VFNMADDSS",
"VFNMSUB132PD", "VFNMSUB132PH", "VFNMSUB132PS", "VFNMSUB132SD",
"VFNMSUB132SH", "VFNMSUB132SS", "VFNMSUB213PD", "VFNMSUB213PH",
"VFNMSUB213PS", "VFNMSUB213SD", "VFNMSUB213SH", "VFNMSUB213SS",
"VFNMSUB231PD", "VFNMSUB231PH", "VFNMSUB231PS", "VFNMSUB231SD",
"VFNMSUB231SH", "VFNMSUB231SS", "VFNMSUBPD", "VFNMSUBPS", "VFNMSUBSD",
"VFNMSUBSS", "VFPCLASSPD", "VFPCLASSPH", "VFPCLASSPS", "VFPCLASSSD",
"VFPCLASSSH", "VFPCLASSSS", "VFRCZPD", "VFRCZPS", "VFRCZSD",
"VFRCZSS", "VGATHERDPD", "VGATHERDPS", "VGATHERPF0DPD", "VGATHERPF0DPS",
"VGATHERPF0QPD", "VGATHERPF0QPS", "VGATHERPF1DPD", "VGATHERPF1DPS",
"VGATHERPF1QPD", "VGATHERPF1QPS", "VGATHERQPD", "VGATHERQPS",
"VGETEXPPD", "VGETEXPPS", "VGETEXPSD", "VGETEXPSS", "VGETMANTPD",
"VGETMANTPS", "VGETMANTSD", "VGETMANTSS", "VGF2P8AFFINEINVQB",
"VGF2P8AFFINEQB", "VGF2P8MULB", "VHADDPD", "VHADDPS", "VHSUBPD",
"VHSUBPS", "VINSERTF128", "VINSERTF32X4", "VINSERTF32X8", "VINSERTF64X2",
"VINSERTF64X4", "VINSERTI128", "VINSERTI32X4", "VINSERTI32X8",
"VINSERTI64X2", "VINSERTI64X4", "VINSERTPS", "VLDDQU", "VLDMXCSR",
"VMASKMOVDQU", "VMASKMOVPD", "VMASKMOVPS", "VMAXPD", "VMAXPS",
"VMAXSD", "VMAXSS", "VMCALL", "VMCLEAR", "VMFUNC", "VMGEXIT",
"VMINPD", "VMINPS", "VMINSD", "VMINSS", "VMLAUNCH", "VMLOAD",
"VMMCALL", "VMOVAPD", "VMOVAPS", "VMOVD", "VMOVDDUP", "VMOVDQA",
"VMOVDQA32", "VMOVDQA64", "VMOVDQU", "VMOVDQU16", "VMOVDQU32",
"VMOVDQU64", "VMOVDQU8", "VMOVHLPS", "VMOVHPD", "VMOVHPS", "VMOVLHPS",
"VMOVLPD", "VMOVLPS", "VMOVMSKPD", "VMOVMSKPS", "VMOVNTDQ", "VMOVNTDQA",
"VMOVNTPD", "VMOVNTPS", "VMOVQ", "VMOVSD", "VMOVSHDUP", "VMOVSLDUP",
"VMOVSS", "VMOVUPD", "VMOVUPS", "VMPSADBW", "VMPTRLD", "VMPTRST",
"VMREAD", "VMRESUME", "VMRUN", "VMSAVE", "VMULPD", "VMULPS",
"VMULSD", "VMULSS", "VMWRITE", "VMXOFF", "VMXON", "VORPD", "VORPS",
"VP2INTERSECTD", "VP2INTERSECTQ", "VP4DPWSSD", "VP4DPWSSDS",
"VPABSB", "VPABSD", "VPABSQ", "VPABSW", "VPACKSSDW", "VPACKSSWB",
"VPACKUSDW", "VPACKUSWB", "VPADDB", "VPADDD", "VPADDQ", "VPADDSB",
"VPADDSW", "VPADDUSB", "VPADDUSW", "VPADDW", "VPALIGNR", "VPAND",
"VPANDD", "VPANDN", "VPANDND", "VPANDNQ", "VPANDQ", "VPAVGB",
"VPAVGW", "VPBLENDD", "VPBLENDMB", "VPBLENDMD", "VPBLENDMQ",
"VPBLENDMW", "VPBLENDVB", "VPBLENDW", "VPBROADCASTB", "VPBROADCASTD",
"VPBROADCASTMB2Q", "VPBROADCASTMW2D", "VPBROADCASTQ", "VPBROADCASTW",
"VPCLMULQDQ", "VPCMOV", "VPCMPB", "VPCMPD", "VPCMPEQB", "VPCMPEQD",
"VPCMPEQQ", "VPCMPEQW", "VPCMPESTRI", "VPCMPESTRM", "VPCMPGTB",
"VPCMPGTD", "VPCMPGTQ", "VPCMPGTW", "VPCMPISTRI", "VPCMPISTRM",
"VPCMPQ", "VPCMPUB", "VPCMPUD", "VPCMPUQ", "VPCMPUW", "VPCMPW",
"VPCOMB", "VPCOMD", "VPCOMPRESSB", "VPCOMPRESSD", "VPCOMPRESSQ",
"VPCOMPRESSW", "VPCOMQ", "VPCOMUB", "VPCOMUD", "VPCOMUQ", "VPCOMUW",
"VPCOMW", "VPCONFLICTD", "VPCONFLICTQ", "VPDPBUSD", "VPDPBUSDS",
"VPDPWSSD", "VPDPWSSDS", "VPERM2F128", "VPERM2I128", "VPERMB",
"VPERMD", "VPERMI2B", "VPERMI2D", "VPERMI2PD", "VPERMI2PS", "VPERMI2Q",
"VGETEXPPD", "VGETEXPPH", "VGETEXPPS", "VGETEXPSD", "VGETEXPSH",
"VGETEXPSS", "VGETMANTPD", "VGETMANTPH", "VGETMANTPS", "VGETMANTSD",
"VGETMANTSH", "VGETMANTSS", "VGF2P8AFFINEINVQB", "VGF2P8AFFINEQB",
"VGF2P8MULB", "VHADDPD", "VHADDPS", "VHSUBPD", "VHSUBPS", "VINSERTF128",
"VINSERTF32X4", "VINSERTF32X8", "VINSERTF64X2", "VINSERTF64X4",
"VINSERTI128", "VINSERTI32X4", "VINSERTI32X8", "VINSERTI64X2",
"VINSERTI64X4", "VINSERTPS", "VLDDQU", "VLDMXCSR", "VMASKMOVDQU",
"VMASKMOVPD", "VMASKMOVPS", "VMAXPD", "VMAXPH", "VMAXPS", "VMAXSD",
"VMAXSH", "VMAXSS", "VMCALL", "VMCLEAR", "VMFUNC", "VMGEXIT",
"VMINPD", "VMINPH", "VMINPS", "VMINSD", "VMINSH", "VMINSS", "VMLAUNCH",
"VMLOAD", "VMMCALL", "VMOVAPD", "VMOVAPS", "VMOVD", "VMOVDDUP",
"VMOVDQA", "VMOVDQA32", "VMOVDQA64", "VMOVDQU", "VMOVDQU16",
"VMOVDQU32", "VMOVDQU64", "VMOVDQU8", "VMOVHLPS", "VMOVHPD",
"VMOVHPS", "VMOVLHPS", "VMOVLPD", "VMOVLPS", "VMOVMSKPD", "VMOVMSKPS",
"VMOVNTDQ", "VMOVNTDQA", "VMOVNTPD", "VMOVNTPS", "VMOVQ", "VMOVSD",
"VMOVSH", "VMOVSHDUP", "VMOVSLDUP", "VMOVSS", "VMOVUPD", "VMOVUPS",
"VMOVW", "VMPSADBW", "VMPTRLD", "VMPTRST", "VMREAD", "VMRESUME",
"VMRUN", "VMSAVE", "VMULPD", "VMULPH", "VMULPS", "VMULSD", "VMULSH",
"VMULSS", "VMWRITE", "VMXOFF", "VMXON", "VORPD", "VORPS", "VP2INTERSECTD",
"VP2INTERSECTQ", "VP4DPWSSD", "VP4DPWSSDS", "VPABSB", "VPABSD",
"VPABSQ", "VPABSW", "VPACKSSDW", "VPACKSSWB", "VPACKUSDW", "VPACKUSWB",
"VPADDB", "VPADDD", "VPADDQ", "VPADDSB", "VPADDSW", "VPADDUSB",
"VPADDUSW", "VPADDW", "VPALIGNR", "VPAND", "VPANDD", "VPANDN",
"VPANDND", "VPANDNQ", "VPANDQ", "VPAVGB", "VPAVGW", "VPBLENDD",
"VPBLENDMB", "VPBLENDMD", "VPBLENDMQ", "VPBLENDMW", "VPBLENDVB",
"VPBLENDW", "VPBROADCASTB", "VPBROADCASTD", "VPBROADCASTMB2Q",
"VPBROADCASTMW2D", "VPBROADCASTQ", "VPBROADCASTW", "VPCLMULQDQ",
"VPCMOV", "VPCMPB", "VPCMPD", "VPCMPEQB", "VPCMPEQD", "VPCMPEQQ",
"VPCMPEQW", "VPCMPESTRI", "VPCMPESTRM", "VPCMPGTB", "VPCMPGTD",
"VPCMPGTQ", "VPCMPGTW", "VPCMPISTRI", "VPCMPISTRM", "VPCMPQ",
"VPCMPUB", "VPCMPUD", "VPCMPUQ", "VPCMPUW", "VPCMPW", "VPCOMB",
"VPCOMD", "VPCOMPRESSB", "VPCOMPRESSD", "VPCOMPRESSQ", "VPCOMPRESSW",
"VPCOMQ", "VPCOMUB", "VPCOMUD", "VPCOMUQ", "VPCOMUW", "VPCOMW",
"VPCONFLICTD", "VPCONFLICTQ", "VPDPBUSD", "VPDPBUSDS", "VPDPWSSD",
"VPDPWSSDS", "VPERM2F128", "VPERM2I128", "VPERMB", "VPERMD",
"VPERMI2B", "VPERMI2D", "VPERMI2PD", "VPERMI2PS", "VPERMI2Q",
"VPERMI2W", "VPERMIL2PD", "VPERMIL2PS", "VPERMILPD", "VPERMILPS",
"VPERMPD", "VPERMPS", "VPERMQ", "VPERMT2B", "VPERMT2D", "VPERMT2PD",
"VPERMT2PS", "VPERMT2Q", "VPERMT2W", "VPERMW", "VPEXPANDB", "VPEXPANDD",
@ -251,28 +269,31 @@ const char *gMnemonics[1589] =
"VPUNPCKHQDQ", "VPUNPCKHWD", "VPUNPCKLBW", "VPUNPCKLDQ", "VPUNPCKLQDQ",
"VPUNPCKLWD", "VPXOR", "VPXORD", "VPXORQ", "VRANGEPD", "VRANGEPS",
"VRANGESD", "VRANGESS", "VRCP14PD", "VRCP14PS", "VRCP14SD", "VRCP14SS",
"VRCP28PD", "VRCP28PS", "VRCP28SD", "VRCP28SS", "VRCPPS", "VRCPSS",
"VREDUCEPD", "VREDUCEPS", "VREDUCESD", "VREDUCESS", "VRNDSCALEPD",
"VRNDSCALEPS", "VRNDSCALESD", "VRNDSCALESS", "VROUNDPD", "VROUNDPS",
"VRCP28PD", "VRCP28PS", "VRCP28SD", "VRCP28SS", "VRCPPH", "VRCPPS",
"VRCPSH", "VRCPSS", "VREDUCEPD", "VREDUCEPH", "VREDUCEPS", "VREDUCESD",
"VREDUCESH", "VREDUCESS", "VRNDSCALEPD", "VRNDSCALEPH", "VRNDSCALEPS",
"VRNDSCALESD", "VRNDSCALESH", "VRNDSCALESS", "VROUNDPD", "VROUNDPS",
"VROUNDSD", "VROUNDSS", "VRSQRT14PD", "VRSQRT14PS", "VRSQRT14SD",
"VRSQRT14SS", "VRSQRT28PD", "VRSQRT28PS", "VRSQRT28SD", "VRSQRT28SS",
"VRSQRTPS", "VRSQRTSS", "VSCALEFPD", "VSCALEFPS", "VSCALEFSD",
"VSCALEFSS", "VSCATTERDPD", "VSCATTERDPS", "VSCATTERPF0DPD",
"VSCATTERPF0DPS", "VSCATTERPF0QPD", "VSCATTERPF0QPS", "VSCATTERPF1DPD",
"VSCATTERPF1DPS", "VSCATTERPF1QPD", "VSCATTERPF1QPS", "VSCATTERQPD",
"VSCATTERQPS", "VSHUFF32X4", "VSHUFF64X2", "VSHUFI32X4", "VSHUFI64X2",
"VSHUFPD", "VSHUFPS", "VSQRTPD", "VSQRTPS", "VSQRTSD", "VSQRTSS",
"VSTMXCSR", "VSUBPD", "VSUBPS", "VSUBSD", "VSUBSS", "VTESTPD",
"VTESTPS", "VUCOMISD", "VUCOMISS", "VUNPCKHPD", "VUNPCKHPS",
"VUNPCKLPD", "VUNPCKLPS", "VXORPD", "VXORPS", "VZEROALL", "VZEROUPPER",
"WAIT", "WBINVD", "WBNOINVD", "WRFSBASE", "WRGSBASE", "WRMSR",
"WRPKRU", "WRSHR", "WRSSD", "WRSSQ", "WRUSSD", "WRUSSQ", "XABORT",
"XADD", "XBEGIN", "XCHG", "XCRYPTCBC", "XCRYPTCFB", "XCRYPTCTR",
"XCRYPTECB", "XCRYPTOFB", "XEND", "XGETBV", "XLATB", "XOR", "XORPD",
"XORPS", "XRESLDTRK", "XRSTOR", "XRSTOR64", "XRSTORS", "XRSTORS64",
"XSAVE", "XSAVE64", "XSAVEC", "XSAVEC64", "XSAVEOPT", "XSAVEOPT64",
"XSAVES", "XSAVES64", "XSETBV", "XSHA1", "XSHA256", "XSTORE",
"XSUSLDTRK", "XTEST",
"VRSQRTPH", "VRSQRTPS", "VRSQRTSH", "VRSQRTSS", "VSCALEFPD",
"VSCALEFPH", "VSCALEFPS", "VSCALEFSD", "VSCALEFSH", "VSCALEFSS",
"VSCATTERDPD", "VSCATTERDPS", "VSCATTERPF0DPD", "VSCATTERPF0DPS",
"VSCATTERPF0QPD", "VSCATTERPF0QPS", "VSCATTERPF1DPD", "VSCATTERPF1DPS",
"VSCATTERPF1QPD", "VSCATTERPF1QPS", "VSCATTERQPD", "VSCATTERQPS",
"VSHUFF32X4", "VSHUFF64X2", "VSHUFI32X4", "VSHUFI64X2", "VSHUFPD",
"VSHUFPS", "VSQRTPD", "VSQRTPH", "VSQRTPS", "VSQRTSD", "VSQRTSH",
"VSQRTSS", "VSTMXCSR", "VSUBPD", "VSUBPH", "VSUBPS", "VSUBSD",
"VSUBSH", "VSUBSS", "VTESTPD", "VTESTPS", "VUCOMISD", "VUCOMISH",
"VUCOMISS", "VUNPCKHPD", "VUNPCKHPS", "VUNPCKLPD", "VUNPCKLPS",
"VXORPD", "VXORPS", "VZEROALL", "VZEROUPPER", "WAIT", "WBINVD",
"WBNOINVD", "WRFSBASE", "WRGSBASE", "WRMSR", "WRPKRU", "WRSHR",
"WRSSD", "WRSSQ", "WRUSSD", "WRUSSQ", "XABORT", "XADD", "XBEGIN",
"XCHG", "XCRYPTCBC", "XCRYPTCFB", "XCRYPTCTR", "XCRYPTECB", "XCRYPTOFB",
"XEND", "XGETBV", "XLATB", "XOR", "XORPD", "XORPS", "XRESLDTRK",
"XRSTOR", "XRSTOR64", "XRSTORS", "XRSTORS64", "XSAVE", "XSAVE64",
"XSAVEC", "XSAVEC64", "XSAVEOPT", "XSAVEOPT64", "XSAVES", "XSAVES64",
"XSETBV", "XSHA1", "XSHA256", "XSTORE", "XSUSLDTRK", "XTEST",
};

5
bddisasm/include/nd_crt.h
Unescape View File

@ -12,8 +12,7 @@
#endif
#if defined(_MSC_VER)
typedef char * va_list;
#include <vadefs.h>
# ifndef _ADDRESSOF
# ifdef __cplusplus
@ -27,8 +26,6 @@ typedef char * va_list;
# if defined(AMD64) || defined(WIN64)
extern void __cdecl __va_start(__out va_list *, ...); // is this exported by VC compiler?
# define _crt_va_start(ap, x) ( __va_start(&ap, x) )
# define _crt_va_arg(ap, t) ( ( sizeof(t) > sizeof(QWORD) || ( sizeof(t) & (sizeof(t) - 1) ) != 0 ) \
? **(t **)( ( ap += sizeof(QWORD) ) - sizeof(QWORD) ) \

5552
bddisasm/include/table_evex.h
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File diff suppressed because it is too large Load Diff

178
bddisasm/include/table_root.h
Unescape View File

@ -106,7 +106,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_80_05_leaf =
const ND_TABLE_INSTRUCTION gRootTable_root_80_06_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2563]
(const void *)&gInstructions[2675]
};
const ND_TABLE_MODRM_REG gRootTable_root_80_modrmreg =
@ -169,7 +169,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_81_05_leaf =
const ND_TABLE_INSTRUCTION gRootTable_root_81_06_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2564]
(const void *)&gInstructions[2676]
};
const ND_TABLE_MODRM_REG gRootTable_root_81_modrmreg =
@ -232,7 +232,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_82_05_leaf =
const ND_TABLE_INSTRUCTION gRootTable_root_82_06_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2565]
(const void *)&gInstructions[2677]
};
const ND_TABLE_MODRM_REG gRootTable_root_82_modrmreg =
@ -295,7 +295,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_83_05_leaf =
const ND_TABLE_INSTRUCTION gRootTable_root_83_06_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2566]
(const void *)&gInstructions[2678]
};
const ND_TABLE_MODRM_REG gRootTable_root_83_modrmreg =
@ -328,13 +328,13 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f6_mem_F3_leaf =
const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f6_mem_NP_None_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2531]
(const void *)&gInstructions[2643]
};
const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f6_mem_NP_rexw_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2532]
(const void *)&gInstructions[2644]
};
const ND_TABLE_AUXILIARY gRootTable_root_0f_38_f6_mem_NP_auxiliary =
@ -2079,13 +2079,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_cb_mprefix =
const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f5_mem_66_None_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2533]
(const void *)&gInstructions[2645]
};
const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f5_mem_66_rexw_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2534]
(const void *)&gInstructions[2646]
};
const ND_TABLE_AUXILIARY gRootTable_root_0f_38_f5_mem_66_auxiliary =
@ -3969,25 +3969,25 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_04_leaf =
const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_01_F3_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[1765]
(const void *)&gInstructions[1850]
};
const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_01_F2_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[1766]
(const void *)&gInstructions[1851]
};
const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_01_None_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[1777]
(const void *)&gInstructions[1864]
};
const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_01_66_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[1778]
(const void *)&gInstructions[1865]
};
const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_03_01_mprefix =
@ -4004,19 +4004,19 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_03_01_mprefix =
const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_02_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[1776]
(const void *)&gInstructions[1863]
};
const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_00_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[1883]
(const void *)&gInstructions[1978]
};
const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_03_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[1884]
(const void *)&gInstructions[1979]
};
const ND_TABLE_MODRM_RM gRootTable_root_0f_01_reg_03_modrmrm =
@ -4089,7 +4089,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_00_F3_leaf =
const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_00_F2_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2587]
(const void *)&gInstructions[2699]
};
const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_00_mprefix =
@ -4112,7 +4112,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_07_F3_leaf =
const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_07_NP_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2529]
(const void *)&gInstructions[2641]
};
const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_07_mprefix =
@ -4163,7 +4163,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_04_mprefix =
const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_01_F2_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2569]
(const void *)&gInstructions[2681]
};
const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_01_mprefix =
@ -4349,7 +4349,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_07_mprefix =
const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_02_04_NP_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[1764]
(const void *)&gInstructions[1849]
};
const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_04_mprefix =
@ -4366,7 +4366,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_04_mprefix =
const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_02_05_NP_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2554]
(const void *)&gInstructions[2666]
};
const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_05_mprefix =
@ -4383,7 +4383,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_05_mprefix =
const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_02_00_NP_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2555]
(const void *)&gInstructions[2667]
};
const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_00_mprefix =
@ -4400,7 +4400,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_00_mprefix =
const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_02_01_NP_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2582]
(const void *)&gInstructions[2694]
};
const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_01_mprefix =
@ -4417,7 +4417,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_01_mprefix =
const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_02_06_NP_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2588]
(const void *)&gInstructions[2700]
};
const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_06_mprefix =
@ -4483,7 +4483,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_05_mprefix =
const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_01_NP_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[1762]
(const void *)&gInstructions[1847]
};
const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_01_mprefix =
@ -4500,7 +4500,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_01_mprefix =
const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_02_NP_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[1775]
(const void *)&gInstructions[1862]
};
const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_02_mprefix =
@ -4517,7 +4517,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_02_mprefix =
const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_03_NP_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[1882]
(const void *)&gInstructions[1977]
};
const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_03_mprefix =
@ -4534,7 +4534,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_03_mprefix =
const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_04_NP_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[1894]
(const void *)&gInstructions[1991]
};
const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_04_mprefix =
@ -4892,13 +4892,13 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_06_66_leaf =
const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_06_NP_None_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2578]
(const void *)&gInstructions[2690]
};
const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_06_NP_rexw_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2579]
(const void *)&gInstructions[2691]
};
const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_mem_06_NP_auxiliary =
@ -5023,13 +5023,13 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_04_F3_leaf =
const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_04_NP_None_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2574]
(const void *)&gInstructions[2686]
};
const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_04_NP_rexw_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2575]
(const void *)&gInstructions[2687]
};
const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_mem_04_NP_auxiliary =
@ -5076,13 +5076,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_03_mprefix =
const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_05_NP_None_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2570]
(const void *)&gInstructions[2682]
};
const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_05_NP_rexw_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2571]
(const void *)&gInstructions[2683]
};
const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_mem_05_NP_auxiliary =
@ -5298,7 +5298,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_07_mprefix =
const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_02_F3_64_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2526]
(const void *)&gInstructions[2638]
};
const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_reg_02_F3_auxiliary =
@ -5328,7 +5328,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_02_mprefix =
const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_03_F3_64_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2527]
(const void *)&gInstructions[2639]
};
const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_reg_03_F3_auxiliary =
@ -5556,19 +5556,19 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_c7_mem_01_auxiliary =
const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_06_66_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[1763]
(const void *)&gInstructions[1848]
};
const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_06_NP_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[1879]
(const void *)&gInstructions[1974]
};
const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_06_F3_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[1895]
(const void *)&gInstructions[1992]
};
const ND_TABLE_MPREFIX gRootTable_root_0f_c7_mem_06_mprefix =
@ -5585,7 +5585,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_c7_mem_06_mprefix =
const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_07_NP_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[1880]
(const void *)&gInstructions[1975]
};
const ND_TABLE_MPREFIX gRootTable_root_0f_c7_mem_07_mprefix =
@ -5602,13 +5602,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_c7_mem_07_mprefix =
const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_03_NP_None_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2572]
(const void *)&gInstructions[2684]
};
const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_03_NP_rexw_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2573]
(const void *)&gInstructions[2685]
};
const ND_TABLE_AUXILIARY gRootTable_root_0f_c7_mem_03_NP_auxiliary =
@ -5638,13 +5638,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_c7_mem_03_mprefix =
const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_04_NP_None_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2576]
(const void *)&gInstructions[2688]
};
const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_04_NP_rexw_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2577]
(const void *)&gInstructions[2689]
};
const ND_TABLE_AUXILIARY gRootTable_root_0f_c7_mem_04_NP_auxiliary =
@ -5674,13 +5674,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_c7_mem_04_mprefix =
const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_05_NP_None_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2580]
(const void *)&gInstructions[2692]
};
const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_05_NP_rexw_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2581]
(const void *)&gInstructions[2693]
};