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Added support for new Intel AVX 10.2 instructions.

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Added support for AMD RMPREAD instruction.
Improved EVEX decoding, including the new U bit.
Fixed ENTER & LEAVE operands.
This commit is contained in:
Andrei Vlad LUTAS 2024-09-16 12:23:54 +03:00
parent c877b5007f
commit 767bf2e5c0
28 changed files with 21696 additions and 18228 deletions
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229
bddisasm/bdx86_decoder.c
View File

@ -151,11 +151,11 @@ NdFetchXop(
Instrux->Xop.Xop[2] = Code[Offset + 2];
Instrux->Exs.w = Instrux->Xop.w;
Instrux->Exs.r = ~Instrux->Xop.r;
Instrux->Exs.x = ~Instrux->Xop.x;
Instrux->Exs.b = ~Instrux->Xop.b;
Instrux->Exs.r = (ND_UINT32)~Instrux->Xop.r;
Instrux->Exs.x = (ND_UINT32)~Instrux->Xop.x;
Instrux->Exs.b = (ND_UINT32)~Instrux->Xop.b;
Instrux->Exs.l = Instrux->Xop.l;
Instrux->Exs.v = ~Instrux->Xop.v;
Instrux->Exs.v = (ND_UINT32)~Instrux->Xop.v;
Instrux->Exs.m = Instrux->Xop.m;
Instrux->Exs.p = Instrux->Xop.p;
@ -226,8 +226,8 @@ NdFetchVex2(
Instrux->Vex2.Vex[1] = Code[Offset + 1];
Instrux->Exs.m = 1; // For VEX2 instructions, always use the second table.
Instrux->Exs.r = ~Instrux->Vex2.r;
Instrux->Exs.v = ~Instrux->Vex2.v;
Instrux->Exs.r = (ND_UINT32)~Instrux->Vex2.r;
Instrux->Exs.v = (ND_UINT32)~Instrux->Vex2.v;
Instrux->Exs.l = Instrux->Vex2.l;
Instrux->Exs.p = Instrux->Vex2.p;
@ -282,12 +282,12 @@ NdFetchVex3(
Instrux->Vex3.Vex[1] = Code[Offset + 1];
Instrux->Vex3.Vex[2] = Code[Offset + 2];
Instrux->Exs.r = ~Instrux->Vex3.r;
Instrux->Exs.x = ~Instrux->Vex3.x;
Instrux->Exs.b = ~Instrux->Vex3.b;
Instrux->Exs.r = (ND_UINT32)~Instrux->Vex3.r;
Instrux->Exs.x = (ND_UINT32)~Instrux->Vex3.x;
Instrux->Exs.b = (ND_UINT32)~Instrux->Vex3.b;
Instrux->Exs.m = Instrux->Vex3.m;
Instrux->Exs.w = Instrux->Vex3.w;
Instrux->Exs.v = ~Instrux->Vex3.v;
Instrux->Exs.v = (ND_UINT32)~Instrux->Vex3.v;
Instrux->Exs.l = Instrux->Vex3.l;
Instrux->Exs.p = Instrux->Vex3.p;
@ -363,29 +363,29 @@ NdFetchEvex(
return ND_STATUS_INVALID_ENCODING;
}
// APX not enabled, legacy EVEX prefix.
if (!(Instrux->FeatMode & ND_FEAT_APX))
// Check map. Maps 4 & 7 are allowed only if APX is enabled.
if (Instrux->Evex.m == 4 || Instrux->Evex.m == 7)
{
// Map > 3 is for APX instructions. B4 must be 0, and X4 must be 1 if APX is not enabled.
if (Instrux->Evex.m > 3 || Instrux->Evex.b4 != 0 || Instrux->Evex.x4 != 1)
if (!(Instrux->FeatMode & ND_FEAT_APX))
{
return ND_STATUS_INVALID_ENCODING;
}
}
// Fill in the generic extension bits. We initially optimistically fill in all possible values.
// Once we determine the opcode and, subsequently, the EVEX extension mode, we will do further
// validations, and reset unused fields to 0.
Instrux->Exs.r = ~Instrux->Evex.r;
Instrux->Exs.x = ~Instrux->Evex.x;
Instrux->Exs.b = ~Instrux->Evex.b;
Instrux->Exs.rp = ~Instrux->Evex.rp;
Instrux->Exs.r = (ND_UINT32)~Instrux->Evex.r;
Instrux->Exs.x = (ND_UINT32)~Instrux->Evex.x;
Instrux->Exs.b = (ND_UINT32)~Instrux->Evex.b;
Instrux->Exs.rp = (ND_UINT32)~Instrux->Evex.rp;
Instrux->Exs.x4 = (ND_UINT32)~Instrux->Evex.u;
Instrux->Exs.b4 = Instrux->Evex.b4;
Instrux->Exs.x4 = ~Instrux->Evex.x4;
Instrux->Exs.m = Instrux->Evex.m;
Instrux->Exs.w = Instrux->Evex.w;
Instrux->Exs.v = ~Instrux->Evex.v;
Instrux->Exs.vp = ~Instrux->Evex.vp;
Instrux->Exs.v = (ND_UINT32)~Instrux->Evex.v;
Instrux->Exs.vp = (ND_UINT32)~Instrux->Evex.vp;
Instrux->Exs.p = Instrux->Evex.p;
Instrux->Exs.z = Instrux->Evex.z;
@ -393,7 +393,7 @@ NdFetchEvex(
Instrux->Exs.bm = Instrux->Evex.bm;
Instrux->Exs.k = Instrux->Evex.a;
// EVEX extensions.
// EVEX extensions. The fields are undefined if the encoding does not use them.
Instrux->Exs.nf = (Instrux->Evex.Evex[3] >> 2) & 1;
Instrux->Exs.nd = (Instrux->Evex.Evex[3] >> 4) & 1;
Instrux->Exs.sc = (Instrux->Evex.Evex[3] & 0xF);
@ -1333,10 +1333,17 @@ NdParseMemoryOperand3264(
Operand->Info.Memory.BaseSize = defsize;
Operand->Info.Memory.Base = (ND_UINT8)(Instrux->Exs.b << 3) | Instrux->Sib.base;
// If APX is present, extend the base.
if (Instrux->FeatMode & ND_FEAT_APX)
if (Instrux->Exs.b4 != 0)
{
Operand->Info.Memory.Base |= Instrux->Exs.b4 << 4;
// If APX is present, extend the base.
if (Instrux->FeatMode & ND_FEAT_APX)
{
Operand->Info.Memory.Base |= Instrux->Exs.b4 << 4;
}
else
{
return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION;
}
}
if ((Operand->Info.Memory.Base == NDR_RSP) || (Operand->Info.Memory.Base == NDR_RBP))
@ -1361,10 +1368,17 @@ NdParseMemoryOperand3264(
// Regular SIB, index RSP is ignored. Bit 4 of the 32-bit index register is given by the X4 field.
Operand->Info.Memory.Index = (ND_UINT8)(Instrux->Exs.x << 3) | Instrux->Sib.index;
// If APX is present, extend the index.
if (Instrux->FeatMode & ND_FEAT_APX)
if (Instrux->Exs.x4 != 0)
{
Operand->Info.Memory.Index |= Instrux->Exs.x4 << 4;
// If APX is present, extend the index.
if (Instrux->FeatMode & ND_FEAT_APX)
{
Operand->Info.Memory.Index |= Instrux->Exs.x4 << 4;
}
else
{
return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION;
}
}
if (Operand->Info.Memory.Index != NDR_RSP)
@ -1401,10 +1415,17 @@ NdParseMemoryOperand3264(
Operand->Info.Memory.BaseSize = defsize;
Operand->Info.Memory.Base = (ND_UINT8)(Instrux->Exs.b << 3) | Instrux->ModRm.rm;
// If APX is present, extend the base register.
if (Instrux->FeatMode & ND_FEAT_APX)
if (Instrux->Exs.b4 != 0)
{
Operand->Info.Memory.Base |= Instrux->Exs.b4 << 4;
// If APX is present, extend the base register.
if (Instrux->FeatMode & ND_FEAT_APX)
{
Operand->Info.Memory.Base |= Instrux->Exs.b4 << 4;
}
else
{
return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION;
}
}
if ((Operand->Info.Memory.Base == NDR_RSP) || (Operand->Info.Memory.Base == NDR_RBP))
@ -2378,13 +2399,7 @@ NdParseOperand(
operand->Encoding = ND_OPE_R;
operand->Info.Register.Type = ND_REG_CR;
operand->Info.Register.Size = (ND_REG_SIZE)size;
operand->Info.Register.Reg = (ND_UINT8)(Instrux->Exs.r << 3) | Instrux->ModRm.reg;
// If APX is present, use R4 as well.
if (Instrux->FeatMode & ND_FEAT_APX)
{
operand->Info.Register.Reg |= Instrux->Exs.rp << 4;
}
operand->Info.Register.Reg = (Instrux->Exs.rp << 4) | (Instrux->Exs.r << 3) | Instrux->ModRm.reg;
// On some AMD processors, the presence of the LOCK prefix before MOV to/from control registers allows accessing
// higher 8 control registers.
@ -2411,13 +2426,7 @@ NdParseOperand(
operand->Encoding = ND_OPE_R;
operand->Info.Register.Type = ND_REG_DR;
operand->Info.Register.Size = (ND_REG_SIZE)size;
operand->Info.Register.Reg = (ND_UINT8)(Instrux->Exs.r << 3) | Instrux->ModRm.reg;
// If APX is present, use R4 as well.
if (Instrux->FeatMode & ND_FEAT_APX)
{
operand->Info.Register.Reg |= Instrux->Exs.rp << 4;
}
operand->Info.Register.Reg = (Instrux->Exs.rp << 4) | (Instrux->Exs.r << 3) | Instrux->ModRm.reg;
// Only DR0-DR7 valid.
if (operand->Info.Register.Reg >= 8)
@ -2481,9 +2490,16 @@ NdParseOperand(
operand->Info.Register.Reg = (ND_UINT8)(Instrux->Exs.b << 3) | Instrux->ModRm.rm;
// If APX is present, use B4 as well.
if (Instrux->FeatMode & ND_FEAT_APX)
if (Instrux->Exs.b4 != 0)
{
operand->Info.Register.Reg |= Instrux->Exs.b4 << 4;
if (Instrux->FeatMode & ND_FEAT_APX)
{
operand->Info.Register.Reg |= Instrux->Exs.b4 << 4;
}
else
{
return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION;
}
}
operand->Info.Register.IsHigh8 = (operand->Info.Register.Size == 1) &&
@ -2560,10 +2576,17 @@ NdParseOperand(
operand->Info.Register.Size = (ND_REG_SIZE)size;
operand->Info.Register.Reg = (ND_UINT8)(Instrux->Exs.b << 3) | Instrux->ModRm.rm;
// If APX is present, use B4 as well.
if (Instrux->FeatMode & ND_FEAT_APX)
if (Instrux->Exs.b4 != 0)
{
operand->Info.Register.Reg |= Instrux->Exs.b4 << 4;
// If APX is present, use B4 as well.
if (Instrux->FeatMode & ND_FEAT_APX)
{
operand->Info.Register.Reg |= Instrux->Exs.b4 << 4;
}
else
{
return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION;
}
}
operand->Info.Register.IsHigh8 = (operand->Info.Register.Size == 1) &&
@ -2985,6 +3008,18 @@ memory:
operand->Info.Memory.Seg = NdGetSegOverride(Instrux, NDR_DS);
break;
case ND_OPT_pBP:
// [sBP], used implicitly by ENTER, when nesting level is > 1.
// Operand size bytes accessed from memory. Base reg size determined by stack address size attribute.
Instrux->MemoryAccess |= operand->Access.Access;
operand->Type = ND_OP_MEM;
operand->Info.Memory.HasBase = ND_TRUE;
operand->Info.Memory.BaseSize = 2 << Instrux->DefStack;
operand->Info.Memory.Base = NDR_RBP; // Always rBP.
operand->Info.Memory.HasSeg = ND_TRUE;
operand->Info.Memory.Seg = NDR_SS;
break;
case ND_OPT_SHS:
// Shadow stack access using the current SSP.
Instrux->MemoryAccess |= operand->Access.Access;
@ -3037,10 +3072,17 @@ memory:
operand->Info.Register.Size = (ND_REG_SIZE)size;
operand->Info.Register.Reg = (ND_UINT8)(Instrux->Exs.b << 3) | (Instrux->PrimaryOpCode & 0x7);
// If APX is present, extend the register.
if (Instrux->FeatMode & ND_FEAT_APX)
if (Instrux->Exs.b4 != 0)
{
operand->Info.Register.Reg |= Instrux->Exs.b4 << 4;
// If APX is present, extend the register.
if (Instrux->FeatMode & ND_FEAT_APX)
{
operand->Info.Register.Reg |= Instrux->Exs.b4 << 4;
}
else
{
return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION;
}
}
operand->Info.Register.IsHigh8 = (operand->Info.Register.Size == 1) &&
@ -3150,10 +3192,17 @@ memory:
operand->Info.Memory.HasBase = ND_TRUE;
operand->Info.Memory.Base = (ND_UINT8)((Instrux->Exs.r << 3) | Instrux->ModRm.reg);
// If APX is present, extend the base register.
if (Instrux->FeatMode & ND_FEAT_APX)
if (Instrux->Exs.rp != 0)
{
operand->Info.Memory.Base |= Instrux->Exs.rp << 4;
// If APX is present, extend the base register.
if (Instrux->FeatMode & ND_FEAT_APX)
{
operand->Info.Memory.Base |= Instrux->Exs.rp << 4;
}
else
{
return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION;
}
}
operand->Info.Memory.BaseSize = 2 << Instrux->AddrMode;
@ -3168,10 +3217,17 @@ memory:
operand->Info.Memory.HasBase = ND_TRUE;
operand->Info.Memory.Base = (ND_UINT8)((Instrux->Exs.b << 3) | Instrux->ModRm.rm);
// If APX is present, extend the base register.
if (Instrux->FeatMode & ND_FEAT_APX)
if (Instrux->Exs.b4 != 0)
{
operand->Info.Memory.Base |= Instrux->Exs.b4 << 4;
// If APX is present, extend the base register.
if (Instrux->FeatMode & ND_FEAT_APX)
{
operand->Info.Memory.Base |= Instrux->Exs.b4 << 4;
}
else
{
return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION;
}
}
operand->Info.Memory.BaseSize = 2 << Instrux->AddrMode;
@ -3188,20 +3244,11 @@ memory:
operand->Info.Register.Reg = Instrux->ModRm.reg;
// #UD if a tile register > 7 is encoded.
if (Instrux->Exs.r != 0)
if (Instrux->Exs.r != 0 || Instrux->Exs.rp != 0)
{
return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION;
}
// #UD of R4 is not 0.
if (Instrux->FeatMode & ND_FEAT_APX)
{
if (Instrux->Exs.rp != 0)
{
return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION;
}
}
break;
case ND_OPT_mT:
@ -3213,20 +3260,11 @@ memory:
operand->Info.Register.Reg = Instrux->ModRm.rm;
// #UD if a tile register > 7 is encoded.
if (Instrux->Exs.b != 0)
if (Instrux->Exs.b != 0 || Instrux->Exs.b4 != 0)
{
return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION;
}
// #UD of B4 is not 0.
if (Instrux->FeatMode & ND_FEAT_APX)
{
if (Instrux->Exs.b4 != 0)
{
return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION;
}
}
break;
case ND_OPT_vT:
@ -3238,20 +3276,11 @@ memory:
operand->Info.Register.Reg = Instrux->Exs.v;
// #UD if a tile register > 7 is encoded.
if (operand->Info.Register.Reg > 7)
if (operand->Info.Register.Reg > 7 || Instrux->Exs.vp != 0)
{
return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION;
}
// #UD of V4 is not 0.
if (Instrux->FeatMode & ND_FEAT_APX)
{
if (Instrux->Exs.vp != 0)
{
return ND_STATUS_INVALID_REGISTER_IN_INSTRUCTION;
}
}
break;
case ND_OPT_dfv:
@ -3278,7 +3307,7 @@ memory:
if (opb != 0)
{
operand->Info.Register.Count = opb;
operand->Info.Register.Reg &= ~(opb - 1);
operand->Info.Register.Reg &= (ND_UINT32)~(opb - 1);
operand->Info.Register.IsBlock = ND_TRUE;
}
else
@ -3894,10 +3923,18 @@ NdGetVectorLength(
(Instrux->TupleType == ND_TUPLE_T1S16) ||
(Instrux->TupleType == ND_TUPLE_T1F))
{
// Scalar instruction, vector length is 128 bits.
Instrux->VecMode = Instrux->EfVecMode = ND_VECM_128;
}
else if (Instrux->Evex.u == 0)
{
// AVX 10 allows SAE/ER for 256-bit vector length, if EVEX.U is 0.
// It is unclear whether the EVEX.U bit is ignored or reserved for scalar instructions.
Instrux->VecMode = Instrux->EfVecMode = ND_VECM_256;
}
else
{
// Legacy or AVX 10 instruction with U bit set, vector length is 512 bits.
Instrux->VecMode = Instrux->EfVecMode = ND_VECM_512;
}
@ -4055,6 +4092,12 @@ NdGetEvexFields(
// Validate the EVEX prefix, depending on the EVEX extension mode.
if (Instrux->EvexMode == ND_EVEXM_EVEX)
{
// EVEX.U field must be 1 if the Modrm.Mod is not reg-reg OR if EVEX.b is 0.
if (Instrux->Evex.u != 1 && (Instrux->ModRm.mod != 3 || Instrux->Exs.bm == 0))
{
return ND_STATUS_BAD_EVEX_U;
}
// Handle embedded broadcast/rounding-control.
if (Instrux->Exs.bm == 1)
{
@ -4173,6 +4216,12 @@ NdGetEvexFields(
return ND_STATUS_INVALID_EVEX_BYTE3;
}
// EVEX.U field must be 1 if mod is reg-reg.
if (Instrux->Evex.u != 1 && Instrux->ModRm.mod == 3)
{
return ND_STATUS_BAD_EVEX_U;
}
if (Instrux->ValidDecorators.Nd)
{
Instrux->HasNd = (ND_BOOL)Instrux->Exs.nd;

28635
bddisasm/include/bdx86_instructions.h
View File

File diff suppressed because it is too large Load Diff

236
bddisasm/include/bdx86_mnemonics.h
View File

@ -12,7 +12,7 @@
#ifndef BDDISASM_NO_MNEMONIC
const char *gMnemonics[1786] =
const char *gMnemonics[1868] =
{
"AAA", "AAD", "AADD", "AAM", "AAND", "AAS", "ADC", "ADCX", "ADD",
"ADDPD", "ADDPS", "ADDSD", "ADDSS", "ADDSUBPD", "ADDSUBPS", "ADOX",
@ -128,109 +128,125 @@ const char *gMnemonics[1786] =
"PXOR", "RCL", "RCPPS", "RCPSS", "RCR", "RDFSBASE", "RDGSBASE",
"RDMSR", "RDMSRLIST", "RDPID", "RDPKRU", "RDPMC", "RDPRU", "RDRAND",
"RDSEED", "RDSSPD", "RDSSPQ", "RDTSC", "RDTSCP", "RETF", "RETN",
"RMPADJUST", "RMPQUERY", "RMPUPDATE", "ROL", "ROR", "RORX", "ROUNDPD",
"ROUNDPS", "ROUNDSD", "ROUNDSS", "RSM", "RSQRTPS", "RSQRTSS",
"RSTORSSP", "SAHF", "SAL", "SALC", "SAR", "SARX", "SAVEPREVSSP",
"SBB", "SCASB", "SCASD", "SCASQ", "SCASW", "SEAMCALL", "SEAMOPS",
"SEAMRET", "SENDUIPI", "SERIALIZE", "SETBE", "SETC", "SETL",
"SETLE", "SETNBE", "SETNC", "SETNL", "SETNLE", "SETNO", "SETNP",
"SETNS", "SETNZ", "SETO", "SETP", "SETS", "SETSSBSY", "SETZ",
"SFENCE", "SGDT", "SHA1MSG1", "SHA1MSG2", "SHA1NEXTE", "SHA1RNDS4",
"SHA256MSG1", "SHA256MSG2", "SHA256RNDS2", "SHL", "SHLD", "SHLX",
"SHR", "SHRD", "SHRX", "SHUFPD", "SHUFPS", "SIDT", "SKINIT",
"SLDT", "SLWPCB", "SMSW", "SPFLT", "SQRTPD", "SQRTPS", "SQRTSD",
"SQRTSS", "STAC", "STC", "STD", "STGI", "STI", "STMXCSR", "STOSB",
"STOSD", "STOSQ", "STOSW", "STR", "STTILECFG", "STUI", "SUB",
"SUBPD", "SUBPS", "SUBSD", "SUBSS", "SWAPGS", "SYSCALL", "SYSENTER",
"SYSEXIT", "SYSRET", "T1MSKC", "TCMMIMFP16PS", "TCMMRLFP16PS",
"RMPADJUST", "RMPQUERY", "RMPREAD", "RMPUPDATE", "ROL", "ROR",
"RORX", "ROUNDPD", "ROUNDPS", "ROUNDSD", "ROUNDSS", "RSM", "RSQRTPS",
"RSQRTSS", "RSTORSSP", "SAHF", "SAL", "SALC", "SAR", "SARX",
"SAVEPREVSSP", "SBB", "SCASB", "SCASD", "SCASQ", "SCASW", "SEAMCALL",
"SEAMOPS", "SEAMRET", "SENDUIPI", "SERIALIZE", "SETBE", "SETC",
"SETL", "SETLE", "SETNBE", "SETNC", "SETNL", "SETNLE", "SETNO",
"SETNP", "SETNS", "SETNZ", "SETO", "SETP", "SETS", "SETSSBSY",
"SETZ", "SFENCE", "SGDT", "SHA1MSG1", "SHA1MSG2", "SHA1NEXTE",
"SHA1RNDS4", "SHA256MSG1", "SHA256MSG2", "SHA256RNDS2", "SHL",
"SHLD", "SHLX", "SHR", "SHRD", "SHRX", "SHUFPD", "SHUFPS", "SIDT",
"SKINIT", "SLDT", "SLWPCB", "SMSW", "SPFLT", "SQRTPD", "SQRTPS",
"SQRTSD", "SQRTSS", "STAC", "STC", "STD", "STGI", "STI", "STMXCSR",
"STOSB", "STOSD", "STOSQ", "STOSW", "STR", "STTILECFG", "STUI",
"SUB", "SUBPD", "SUBPS", "SUBSD", "SUBSS", "SWAPGS", "SYSCALL",
"SYSENTER", "SYSEXIT", "SYSRET", "T1MSKC", "TCMMIMFP16PS", "TCMMRLFP16PS",
"TDCALL", "TDPBF16PS", "TDPBSSD", "TDPBSUD", "TDPBUSD", "TDPBUUD",
"TDPFP16PS", "TEST", "TESTUI", "TILELOADD", "TILELOADDT1", "TILERELEASE",
"TILESTORED", "TILEZERO", "TLBSYNC", "TPAUSE", "TZCNT", "TZMSK",
"UCOMISD", "UCOMISS", "UD0", "UD1", "UD2", "UIRET", "UMONITOR",
"UMWAIT", "UNPCKHPD", "UNPCKHPS", "UNPCKLPD", "UNPCKLPS", "URDMSR",
"UWRMSR", "V4FMADDPS", "V4FMADDSS", "V4FNMADDPS", "V4FNMADDSS",
"VADDPD", "VADDPH", "VADDPS", "VADDSD", "VADDSH", "VADDSS", "VADDSUBPD",
"VADDSUBPS", "VAESDEC", "VAESDECLAST", "VAESENC", "VAESENCLAST",
"VAESIMC", "VAESKEYGENASSIST", "VALIGND", "VALIGNQ", "VANDNPD",
"VANDNPS", "VANDPD", "VANDPS", "VBCSTNEBF162PS", "VBCSTNESH2PS",
"VBLENDMPD", "VBLENDMPS", "VBLENDPD", "VBLENDPS", "VBLENDVPD",
"VBLENDVPS", "VBROADCASTF128", "VBROADCASTF32X2", "VBROADCASTF32X4",
"VBROADCASTF32X8", "VBROADCASTF64X2", "VBROADCASTF64X4", "VBROADCASTI128",
"VBROADCASTI32X2", "VBROADCASTI32X4", "VBROADCASTI32X8", "VBROADCASTI64X2",
"VBROADCASTI64X4", "VBROADCASTSD", "VBROADCASTSS", "VCMPPD",
"VCMPPH", "VCMPPS", "VCMPSD", "VCMPSH", "VCMPSS", "VCOMISD",
"VCOMISH", "VCOMISS", "VCOMPRESSPD", "VCOMPRESSPS", "VCVTDQ2PD",
"VCVTDQ2PH", "VCVTDQ2PS", "VCVTNE2PS2BF16", "VCVTNEEBF162PS",
"VCVTNEEPH2PS", "VCVTNEOBF162PS", "VCVTNEOPH2PS", "VCVTNEPS2BF16",
"VCVTPD2DQ", "VCVTPD2PH", "VCVTPD2PS", "VCVTPD2QQ", "VCVTPD2UDQ",
"VCVTPD2UQQ", "VCVTPH2DQ", "VCVTPH2PD", "VCVTPH2PS", "VCVTPH2PSX",
"VCVTPH2QQ", "VCVTPH2UDQ", "VCVTPH2UQQ", "VCVTPH2UW", "VCVTPH2W",
"VCVTPS2DQ", "VCVTPS2PD", "VCVTPS2PH", "VCVTPS2PHX", "VCVTPS2QQ",
"VCVTPS2UDQ", "VCVTPS2UQQ", "VCVTQQ2PD", "VCVTQQ2PH", "VCVTQQ2PS",
"VCVTSD2SH", "VCVTSD2SI", "VCVTSD2SS", "VCVTSD2USI", "VCVTSH2SD",
"VCVTSH2SI", "VCVTSH2SS", "VCVTSH2USI", "VCVTSI2SD", "VCVTSI2SH",
"VCVTSI2SS", "VCVTSS2SD", "VCVTSS2SH", "VCVTSS2SI", "VCVTSS2USI",
"VCVTTPD2DQ", "VCVTTPD2QQ", "VCVTTPD2UDQ", "VCVTTPD2UQQ", "VCVTTPH2DQ",
"VCVTTPH2QQ", "VCVTTPH2UDQ", "VCVTTPH2UQQ", "VCVTTPH2UW", "VCVTTPH2W",
"VCVTTPS2DQ", "VCVTTPS2QQ", "VCVTTPS2UDQ", "VCVTTPS2UQQ", "VCVTTSD2SI",
"VCVTTSD2USI", "VCVTTSH2SI", "VCVTTSH2USI", "VCVTTSS2SI", "VCVTTSS2USI",
"VCVTUDQ2PD", "VCVTUDQ2PH", "VCVTUDQ2PS", "VCVTUQQ2PD", "VCVTUQQ2PH",
"VCVTUQQ2PS", "VCVTUSI2SD", "VCVTUSI2SH", "VCVTUSI2SS", "VCVTUW2PH",
"VCVTW2PH", "VDBPSADBW", "VDIVPD", "VDIVPH", "VDIVPS", "VDIVSD",
"VDIVSH", "VDIVSS", "VDPBF16PS", "VDPPD", "VDPPS", "VERR", "VERW",
"VEXP2PD", "VEXP2PS", "VEXPANDPD", "VEXPANDPS", "VEXTRACTF128",
"VEXTRACTF32X4", "VEXTRACTF32X8", "VEXTRACTF64X2", "VEXTRACTF64X4",
"VEXTRACTI128", "VEXTRACTI32X4", "VEXTRACTI32X8", "VEXTRACTI64X2",
"VEXTRACTI64X4", "VEXTRACTPS", "VFCMADDCPH", "VFCMADDCSH", "VFCMULCPH",
"VFCMULCSH", "VFIXUPIMMPD", "VFIXUPIMMPS", "VFIXUPIMMSD", "VFIXUPIMMSS",
"VADDNEPBF16", "VADDPD", "VADDPH", "VADDPS", "VADDSD", "VADDSH",
"VADDSS", "VADDSUBPD", "VADDSUBPS", "VAESDEC", "VAESDECLAST",
"VAESENC", "VAESENCLAST", "VAESIMC", "VAESKEYGENASSIST", "VALIGND",
"VALIGNQ", "VANDNPD", "VANDNPS", "VANDPD", "VANDPS", "VBCSTNEBF162PS",
"VBCSTNESH2PS", "VBLENDMPD", "VBLENDMPS", "VBLENDPD", "VBLENDPS",
"VBLENDVPD", "VBLENDVPS", "VBROADCASTF128", "VBROADCASTF32X2",
"VBROADCASTF32X4", "VBROADCASTF32X8", "VBROADCASTF64X2", "VBROADCASTF64X4",
"VBROADCASTI128", "VBROADCASTI32X2", "VBROADCASTI32X4", "VBROADCASTI32X8",
"VBROADCASTI64X2", "VBROADCASTI64X4", "VBROADCASTSD", "VBROADCASTSS",
"VCMPPBF16", "VCMPPD", "VCMPPH", "VCMPPS", "VCMPSD", "VCMPSH",
"VCMPSS", "VCOMISD", "VCOMISH", "VCOMISS", "VCOMPRESSPD", "VCOMPRESSPS",
"VCOMSBF16", "VCOMXSD", "VCOMXSH", "VCOMXSS", "VCVT2PS2PHX",
"VCVTBIASPH2BF8", "VCVTBIASPH2BF8S", "VCVTBIASPH2HF8", "VCVTBIASPH2HF8S",
"VCVTDQ2PD", "VCVTDQ2PH", "VCVTDQ2PS", "VCVTHF82PH", "VCVTNE2PH2BF8",
"VCVTNE2PH2BF8S", "VCVTNE2PH2HF8", "VCVTNE2PH2HF8S", "VCVTNE2PS2BF16",
"VCVTNEBF162IBS", "VCVTNEBF162IUBS", "VCVTNEEBF162PS", "VCVTNEEPH2PS",
"VCVTNEOBF162PS", "VCVTNEOPH2PS", "VCVTNEPH2BF8", "VCVTNEPH2BF8S",
"VCVTNEPH2HF8", "VCVTNEPH2HF8S", "VCVTNEPS2BF16", "VCVTPD2DQ",
"VCVTPD2PH", "VCVTPD2PS", "VCVTPD2QQ", "VCVTPD2UDQ", "VCVTPD2UQQ",
"VCVTPH2DQ", "VCVTPH2IBS", "VCVTPH2IUBS", "VCVTPH2PD", "VCVTPH2PS",
"VCVTPH2PSX", "VCVTPH2QQ", "VCVTPH2UDQ", "VCVTPH2UQQ", "VCVTPH2UW",
"VCVTPH2W", "VCVTPS2DQ", "VCVTPS2IBS", "VCVTPS2IUBS", "VCVTPS2PD",
"VCVTPS2PH", "VCVTPS2PHX", "VCVTPS2QQ", "VCVTPS2UDQ", "VCVTPS2UQQ",
"VCVTQQ2PD", "VCVTQQ2PH", "VCVTQQ2PS", "VCVTSD2SH", "VCVTSD2SI",
"VCVTSD2SS", "VCVTSD2USI", "VCVTSH2SD", "VCVTSH2SI", "VCVTSH2SS",
"VCVTSH2USI", "VCVTSI2SD", "VCVTSI2SH", "VCVTSI2SS", "VCVTSS2SD",
"VCVTSS2SH", "VCVTSS2SI", "VCVTSS2USI", "VCVTTNEBF162IBS", "VCVTTNEBF162IUBS",
"VCVTTPD2DQ", "VCVTTPD2DQS", "VCVTTPD2QQ", "VCVTTPD2QQS", "VCVTTPD2UDQ",
"VCVTTPD2UDQS", "VCVTTPD2UQQ", "VCVTTPD2UQQS", "VCVTTPH2DQ",
"VCVTTPH2IBS", "VCVTTPH2IUBS", "VCVTTPH2QQ", "VCVTTPH2UDQ", "VCVTTPH2UQQ",
"VCVTTPH2UW", "VCVTTPH2W", "VCVTTPS2DQ", "VCVTTPS2DQS", "VCVTTPS2IBS",
"VCVTTPS2IUBS", "VCVTTPS2QQ", "VCVTTPS2QQS", "VCVTTPS2UDQ", "VCVTTPS2UDQS",
"VCVTTPS2UQQ", "VCVTTPS2UQQS", "VCVTTSD2SI", "VCVTTSD2SIS", "VCVTTSD2USI",
"VCVTTSD2USIS", "VCVTTSH2SI", "VCVTTSH2USI", "VCVTTSS2SI", "VCVTTSS2SIS",
"VCVTTSS2USI", "VCVTTSS2USIS", "VCVTUDQ2PD", "VCVTUDQ2PH", "VCVTUDQ2PS",
"VCVTUQQ2PD", "VCVTUQQ2PH", "VCVTUQQ2PS", "VCVTUSI2SD", "VCVTUSI2SH",
"VCVTUSI2SS", "VCVTUW2PH", "VCVTW2PH", "VDBPSADBW", "VDIVNEPBF16",
"VDIVPD", "VDIVPH", "VDIVPS", "VDIVSD", "VDIVSH", "VDIVSS", "VDPBF16PS",
"VDPPD", "VDPPHPS", "VDPPS", "VERR", "VERW", "VEXP2PD", "VEXP2PS",
"VEXPANDPD", "VEXPANDPS", "VEXTRACTF128", "VEXTRACTF32X4", "VEXTRACTF32X8",
"VEXTRACTF64X2", "VEXTRACTF64X4", "VEXTRACTI128", "VEXTRACTI32X4",
"VEXTRACTI32X8", "VEXTRACTI64X2", "VEXTRACTI64X4", "VEXTRACTPS",
"VFCMADDCPH", "VFCMADDCSH", "VFCMULCPH", "VFCMULCSH", "VFIXUPIMMPD",
"VFIXUPIMMPS", "VFIXUPIMMSD", "VFIXUPIMMSS", "VFMADD132NEPBF16",
"VFMADD132PD", "VFMADD132PH", "VFMADD132PS", "VFMADD132SD", "VFMADD132SH",
"VFMADD132SS", "VFMADD213PD", "VFMADD213PH", "VFMADD213PS", "VFMADD213SD",
"VFMADD213SH", "VFMADD213SS", "VFMADD231PD", "VFMADD231PH", "VFMADD231PS",
"VFMADD231SD", "VFMADD231SH", "VFMADD231SS", "VFMADDCPH", "VFMADDCSH",
"VFMADDPD", "VFMADDPS", "VFMADDSD", "VFMADDSS", "VFMADDSUB132PD",
"VFMADDSUB132PH", "VFMADDSUB132PS", "VFMADDSUB213PD", "VFMADDSUB213PH",
"VFMADDSUB213PS", "VFMADDSUB231PD", "VFMADDSUB231PH", "VFMADDSUB231PS",
"VFMADDSUBPD", "VFMADDSUBPS", "VFMSUB132PD", "VFMSUB132PH", "VFMSUB132PS",
"VFMSUB132SD", "VFMSUB132SH", "VFMSUB132SS", "VFMSUB213PD", "VFMSUB213PH",
"VFMSUB213PS", "VFMSUB213SD", "VFMSUB213SH", "VFMSUB213SS", "VFMSUB231PD",
"VFMSUB231PH", "VFMSUB231PS", "VFMSUB231SD", "VFMSUB231SH", "VFMSUB231SS",
"VFMSUBADD132PD", "VFMSUBADD132PH", "VFMSUBADD132PS", "VFMSUBADD213PD",
"VFMSUBADD213PH", "VFMSUBADD213PS", "VFMSUBADD231PD", "VFMSUBADD231PH",
"VFMSUBADD231PS", "VFMSUBADDPD", "VFMSUBADDPS", "VFMSUBPD", "VFMSUBPS",
"VFMSUBSD", "VFMSUBSS", "VFMULCPH", "VFMULCSH", "VFNMADD132PD",
"VFMADD132SS", "VFMADD213NEPBF16", "VFMADD213PD", "VFMADD213PH",
"VFMADD213PS", "VFMADD213SD", "VFMADD213SH", "VFMADD213SS", "VFMADD231NEPBF16",
"VFMADD231PD", "VFMADD231PH", "VFMADD231PS", "VFMADD231SD", "VFMADD231SH",
"VFMADD231SS", "VFMADDCPH", "VFMADDCSH", "VFMADDPD", "VFMADDPS",
"VFMADDSD", "VFMADDSS", "VFMADDSUB132PD", "VFMADDSUB132PH", "VFMADDSUB132PS",
"VFMADDSUB213PD", "VFMADDSUB213PH", "VFMADDSUB213PS", "VFMADDSUB231PD",
"VFMADDSUB231PH", "VFMADDSUB231PS", "VFMADDSUBPD", "VFMADDSUBPS",
"VFMSUB132NEPBF16", "VFMSUB132PD", "VFMSUB132PH", "VFMSUB132PS",
"VFMSUB132SD", "VFMSUB132SH", "VFMSUB132SS", "VFMSUB213NEPBF16",
"VFMSUB213PD", "VFMSUB213PH", "VFMSUB213PS", "VFMSUB213SD", "VFMSUB213SH",
"VFMSUB213SS", "VFMSUB231NEPBF16", "VFMSUB231PD", "VFMSUB231PH",
"VFMSUB231PS", "VFMSUB231SD", "VFMSUB231SH", "VFMSUB231SS", "VFMSUBADD132PD",
"VFMSUBADD132PH", "VFMSUBADD132PS", "VFMSUBADD213PD", "VFMSUBADD213PH",
"VFMSUBADD213PS", "VFMSUBADD231PD", "VFMSUBADD231PH", "VFMSUBADD231PS",
"VFMSUBADDPD", "VFMSUBADDPS", "VFMSUBPD", "VFMSUBPS", "VFMSUBSD",
"VFMSUBSS", "VFMULCPH", "VFMULCSH", "VFNMADD132NEPBF16", "VFNMADD132PD",
"VFNMADD132PH", "VFNMADD132PS", "VFNMADD132SD", "VFNMADD132SH",
"VFNMADD132SS", "VFNMADD213PD", "VFNMADD213PH", "VFNMADD213PS",
"VFNMADD213SD", "VFNMADD213SH", "VFNMADD213SS", "VFNMADD231PD",
"VFNMADD231PH", "VFNMADD231PS", "VFNMADD231SD", "VFNMADD231SH",
"VFNMADD231SS", "VFNMADDPD", "VFNMADDPS", "VFNMADDSD", "VFNMADDSS",
"VFNMSUB132PD", "VFNMSUB132PH", "VFNMSUB132PS", "VFNMSUB132SD",
"VFNMSUB132SH", "VFNMSUB132SS", "VFNMSUB213PD", "VFNMSUB213PH",
"VFNMADD132SS", "VFNMADD213NEPBF16", "VFNMADD213PD", "VFNMADD213PH",
"VFNMADD213PS", "VFNMADD213SD", "VFNMADD213SH", "VFNMADD213SS",
"VFNMADD231NEPBF16", "VFNMADD231PD", "VFNMADD231PH", "VFNMADD231PS",
"VFNMADD231SD", "VFNMADD231SH", "VFNMADD231SS", "VFNMADDPD",
"VFNMADDPS", "VFNMADDSD", "VFNMADDSS", "VFNMSUB132NEPBF16", "VFNMSUB132PD",
"VFNMSUB132PH", "VFNMSUB132PS", "VFNMSUB132SD", "VFNMSUB132SH",
"VFNMSUB132SS", "VFNMSUB213NEPBF16", "VFNMSUB213PD", "VFNMSUB213PH",
"VFNMSUB213PS", "VFNMSUB213SD", "VFNMSUB213SH", "VFNMSUB213SS",
"VFNMSUB231PD", "VFNMSUB231PH", "VFNMSUB231PS", "VFNMSUB231SD",
"VFNMSUB231SH", "VFNMSUB231SS", "VFNMSUBPD", "VFNMSUBPS", "VFNMSUBSD",
"VFNMSUBSS", "VFPCLASSPD", "VFPCLASSPH", "VFPCLASSPS", "VFPCLASSSD",
"VFPCLASSSH", "VFPCLASSSS", "VFRCZPD", "VFRCZPS", "VFRCZSD",
"VFRCZSS", "VGATHERDPD", "VGATHERDPS", "VGATHERPF0DPD", "VGATHERPF0DPS",
"VGATHERPF0QPD", "VGATHERPF0QPS", "VGATHERPF1DPD", "VGATHERPF1DPS",
"VGATHERPF1QPD", "VGATHERPF1QPS", "VGATHERQPD", "VGATHERQPS",
"VGETEXPPD", "VGETEXPPH", "VGETEXPPS", "VGETEXPSD", "VGETEXPSH",
"VGETEXPSS", "VGETMANTPD", "VGETMANTPH", "VGETMANTPS", "VGETMANTSD",
"VGETMANTSH", "VGETMANTSS", "VGF2P8AFFINEINVQB", "VGF2P8AFFINEQB",
"VGF2P8MULB", "VHADDPD", "VHADDPS", "VHSUBPD", "VHSUBPS", "VINSERTF128",
"VINSERTF32X4", "VINSERTF32X8", "VINSERTF64X2", "VINSERTF64X4",
"VINSERTI128", "VINSERTI32X4", "VINSERTI32X8", "VINSERTI64X2",
"VINSERTI64X4", "VINSERTPS", "VLDDQU", "VLDMXCSR", "VMASKMOVDQU",
"VMASKMOVPD", "VMASKMOVPS", "VMAXPD", "VMAXPH", "VMAXPS", "VMAXSD",
"VFNMSUB231NEPBF16", "VFNMSUB231PD", "VFNMSUB231PH", "VFNMSUB231PS",
"VFNMSUB231SD", "VFNMSUB231SH", "VFNMSUB231SS", "VFNMSUBPD",
"VFNMSUBPS", "VFNMSUBSD", "VFNMSUBSS", "VFPCLASSPBF16", "VFPCLASSPD",
"VFPCLASSPH", "VFPCLASSPS", "VFPCLASSSD", "VFPCLASSSH", "VFPCLASSSS",
"VFRCZPD", "VFRCZPS", "VFRCZSD", "VFRCZSS", "VGATHERDPD", "VGATHERDPS",
"VGATHERPF0DPD", "VGATHERPF0DPS", "VGATHERPF0QPD", "VGATHERPF0QPS",
"VGATHERPF1DPD", "VGATHERPF1DPS", "VGATHERPF1QPD", "VGATHERPF1QPS",
"VGATHERQPD", "VGATHERQPS", "VGETEXPPBF16", "VGETEXPPD", "VGETEXPPH",
"VGETEXPPS", "VGETEXPSD", "VGETEXPSH", "VGETEXPSS", "VGETMANTPBF16",
"VGETMANTPD", "VGETMANTPH", "VGETMANTPS", "VGETMANTSD", "VGETMANTSH",
"VGETMANTSS", "VGF2P8AFFINEINVQB", "VGF2P8AFFINEQB", "VGF2P8MULB",
"VHADDPD", "VHADDPS", "VHSUBPD", "VHSUBPS", "VINSERTF128", "VINSERTF32X4",
"VINSERTF32X8", "VINSERTF64X2", "VINSERTF64X4", "VINSERTI128",
"VINSERTI32X4", "VINSERTI32X8", "VINSERTI64X2", "VINSERTI64X4",
"VINSERTPS", "VLDDQU", "VLDMXCSR", "VMASKMOVDQU", "VMASKMOVPD",
"VMASKMOVPS", "VMAXPBF16", "VMAXPD", "VMAXPH", "VMAXPS", "VMAXSD",
"VMAXSH", "VMAXSS", "VMCALL", "VMCLEAR", "VMFUNC", "VMGEXIT",
"VMINPD", "VMINPH", "VMINPS", "VMINSD", "VMINSH", "VMINSS", "VMLAUNCH",
"VMLOAD", "VMMCALL", "VMOVAPD", "VMOVAPS", "VMOVD", "VMOVDDUP",
"VMOVDQA", "VMOVDQA32", "VMOVDQA64", "VMOVDQU", "VMOVDQU16",
"VMOVDQU32", "VMOVDQU64", "VMOVDQU8", "VMOVHLPS", "VMOVHPD",
"VMOVHPS", "VMOVLHPS", "VMOVLPD", "VMOVLPS", "VMOVMSKPD", "VMOVMSKPS",
"VMOVNTDQ", "VMOVNTDQA", "VMOVNTPD", "VMOVNTPS", "VMOVQ", "VMOVSD",
"VMOVSH", "VMOVSHDUP", "VMOVSLDUP", "VMOVSS", "VMOVUPD", "VMOVUPS",
"VMOVW", "VMPSADBW", "VMPTRLD", "VMPTRST", "VMREAD", "VMRESUME",
"VMRUN", "VMSAVE", "VMULPD", "VMULPH", "VMULPS", "VMULSD", "VMULSH",
"VMINMAXNEPBF16", "VMINMAXPD", "VMINMAXPH", "VMINMAXPS", "VMINMAXSD",
"VMINMAXSH", "VMINMAXSS", "VMINPBF16", "VMINPD", "VMINPH", "VMINPS",
"VMINSD", "VMINSH", "VMINSS", "VMLAUNCH", "VMLOAD", "VMMCALL",
"VMOVAPD", "VMOVAPS", "VMOVD", "VMOVDDUP", "VMOVDQA", "VMOVDQA32",
"VMOVDQA64", "VMOVDQU", "VMOVDQU16", "VMOVDQU32", "VMOVDQU64",
"VMOVDQU8", "VMOVHLPS", "VMOVHPD", "VMOVHPS", "VMOVLHPS", "VMOVLPD",
"VMOVLPS", "VMOVMSKPD", "VMOVMSKPS", "VMOVNTDQ", "VMOVNTDQA",
"VMOVNTPD", "VMOVNTPS", "VMOVQ", "VMOVSD", "VMOVSH", "VMOVSHDUP",
"VMOVSLDUP", "VMOVSS", "VMOVUPD", "VMOVUPS", "VMOVW", "VMPSADBW",
"VMPTRLD", "VMPTRST", "VMREAD", "VMRESUME", "VMRUN", "VMSAVE",
"VMULNEPBF16", "VMULPD", "VMULPH", "VMULPS", "VMULSD", "VMULSH",
"VMULSS", "VMWRITE", "VMXOFF", "VMXON", "VORPD", "VORPS", "VP2INTERSECTD",
"VP2INTERSECTQ", "VP4DPWSSD", "VP4DPWSSDS", "VPABSB", "VPABSD",
"VPABSQ", "VPABSW", "VPACKSSDW", "VPACKSSWB", "VPACKUSDW", "VPACKUSWB",
@ -296,27 +312,29 @@ const char *gMnemonics[1786] =
"VPUNPCKLBW", "VPUNPCKLDQ", "VPUNPCKLQDQ", "VPUNPCKLWD", "VPXOR",
"VPXORD", "VPXORQ", "VRANGEPD", "VRANGEPS", "VRANGESD", "VRANGESS",
"VRCP14PD", "VRCP14PS", "VRCP14SD", "VRCP14SS", "VRCP28PD", "VRCP28PS",
"VRCP28SD", "VRCP28SS", "VRCPPH", "VRCPPS", "VRCPSH", "VRCPSS",
"VREDUCEPD", "VREDUCEPH", "VREDUCEPS", "VREDUCESD", "VREDUCESH",
"VREDUCESS", "VRNDSCALEPD", "VRNDSCALEPH", "VRNDSCALEPS", "VRNDSCALESD",
"VRNDSCALESH", "VRNDSCALESS", "VROUNDPD", "VROUNDPS", "VROUNDSD",
"VROUNDSS", "VRSQRT14PD", "VRSQRT14PS", "VRSQRT14SD", "VRSQRT14SS",
"VRSQRT28PD", "VRSQRT28PS", "VRSQRT28SD", "VRSQRT28SS", "VRSQRTPH",
"VRSQRTPS", "VRSQRTSH", "VRSQRTSS", "VSCALEFPD", "VSCALEFPH",
"VRCP28SD", "VRCP28SS", "VRCPPBF16", "VRCPPH", "VRCPPS", "VRCPSH",
"VRCPSS", "VREDUCENEPBF16", "VREDUCEPD", "VREDUCEPH", "VREDUCEPS",
"VREDUCESD", "VREDUCESH", "VREDUCESS", "VRNDSCALENEPBF16", "VRNDSCALEPD",
"VRNDSCALEPH", "VRNDSCALEPS", "VRNDSCALESD", "VRNDSCALESH", "VRNDSCALESS",
"VROUNDPD", "VROUNDPS", "VROUNDSD", "VROUNDSS", "VRSQRT14PD",
"VRSQRT14PS", "VRSQRT14SD", "VRSQRT14SS", "VRSQRT28PD", "VRSQRT28PS",
"VRSQRT28SD", "VRSQRT28SS", "VRSQRTPBF16", "VRSQRTPH", "VRSQRTPS",
"VRSQRTSH", "VRSQRTSS", "VSCALEFPBF16", "VSCALEFPD", "VSCALEFPH",
"VSCALEFPS", "VSCALEFSD", "VSCALEFSH", "VSCALEFSS", "VSCATTERDPD",
"VSCATTERDPS", "VSCATTERPF0DPD", "VSCATTERPF0DPS", "VSCATTERPF0QPD",
"VSCATTERPF0QPS", "VSCATTERPF1DPD", "VSCATTERPF1DPS", "VSCATTERPF1QPD",
"VSCATTERPF1QPS", "VSCATTERQPD", "VSCATTERQPS", "VSHA512MSG1",
"VSHA512MSG2", "VSHA512RNDS2", "VSHUFF32X4", "VSHUFF64X2", "VSHUFI32X4",
"VSHUFI64X2", "VSHUFPD", "VSHUFPS", "VSM3MSG1", "VSM3MSG2", "VSM3RNDS2",
"VSM4KEY4", "VSM4RNDS4", "VSQRTPD", "VSQRTPH", "VSQRTPS", "VSQRTSD",
"VSQRTSH", "VSQRTSS", "VSTMXCSR", "VSUBPD", "VSUBPH", "VSUBPS",
"VSUBSD", "VSUBSH", "VSUBSS", "VTESTPD", "VTESTPS", "VUCOMISD",
"VUCOMISH", "VUCOMISS", "VUNPCKHPD", "VUNPCKHPS", "VUNPCKLPD",
"VUNPCKLPS", "VXORPD", "VXORPS", "VZEROALL", "VZEROUPPER", "WAIT",
"WBINVD", "WBNOINVD", "WRFSBASE", "WRGSBASE", "WRMSR", "WRMSRLIST",
"WRMSRNS", "WRPKRU", "WRSSD", "WRSSQ", "WRUSSD", "WRUSSQ", "XABORT",
"XADD", "XBEGIN", "XCHG", "XEND", "XGETBV", "XLATB", "XOR", "XORPD",
"VSM4KEY4", "VSM4RNDS4", "VSQRTNEPBF16", "VSQRTPD", "VSQRTPH",
"VSQRTPS", "VSQRTSD", "VSQRTSH", "VSQRTSS", "VSTMXCSR", "VSUBNEPBF16",
"VSUBPD", "VSUBPH", "VSUBPS", "VSUBSD", "VSUBSH", "VSUBSS", "VTESTPD",
"VTESTPS", "VUCOMISD", "VUCOMISH", "VUCOMISS", "VUCOMXSD", "VUCOMXSH",
"VUCOMXSS", "VUNPCKHPD", "VUNPCKHPS", "VUNPCKLPD", "VUNPCKLPS",
"VXORPD", "VXORPS", "VZEROALL", "VZEROUPPER", "WAIT", "WBINVD",
"WBNOINVD", "WRFSBASE", "WRGSBASE", "WRMSR", "WRMSRLIST", "WRMSRNS",
"WRPKRU", "WRSSD", "WRSSQ", "WRUSSD", "WRUSSQ", "XABORT", "XADD",
"XBEGIN", "XCHG", "XEND", "XGETBV", "XLATB", "XOR", "XORPD",
"XORPS", "XRESLDTRK", "XRSTOR", "XRSTOR64", "XRSTORS", "XRSTORS64",
"XSAVE", "XSAVE64", "XSAVEC", "XSAVEC64", "XSAVEOPT", "XSAVEOPT64",
"XSAVES", "XSAVES64", "XSETBV", "XSUSLDTRK", "XTEST",

6444
bddisasm/include/bdx86_table_evex.h
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2652
bddisasm/include/bdx86_table_root.h
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File diff suppressed because it is too large Load Diff

1218
bddisasm/include/bdx86_table_vex.h
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File diff suppressed because it is too large Load Diff

170
bddisasm/include/bdx86_table_xop.h
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@ -13,13 +13,13 @@
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_0a_opcode_12_modrmreg_01_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 1347] // LWPVAL By,Ed,Id
(const void *)&gInstructions[ 1337] // LWPVAL By,Ed,Id
};
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_0a_opcode_12_modrmreg_00_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 1346] // LWPINS By,Ed,Id
(const void *)&gInstructions[ 1336] // LWPINS By,Ed,Id
};
const ND_TABLE_MODRM_REG gXopMap_mmmmm_0a_opcode_12_modrmreg =
@ -40,7 +40,7 @@ const ND_TABLE_MODRM_REG gXopMap_mmmmm_0a_opcode_12_modrmreg =
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_0a_opcode_10_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 197] // BEXTR Gy,Ey,Id
(const void *)&gInstructions[ 189] // BEXTR Gy,Ey,Id
};
const ND_TABLE_OPCODE gXopMap_mmmmm_0a_opcode =
@ -309,103 +309,103 @@ const ND_TABLE_OPCODE gXopMap_mmmmm_0a_opcode =
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_e3_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 3527] // VPHSUBDQ Vdq,Wdq
(const void *)&gInstructions[ 3599] // VPHSUBDQ Vdq,Wdq
};
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_e2_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 3530] // VPHSUBWD Vdq,Wdq
(const void *)&gInstructions[ 3602] // VPHSUBWD Vdq,Wdq
};
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_e1_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 3525] // VPHSUBBW Vdq,Wdq
(const void *)&gInstructions[ 3597] // VPHSUBBW Vdq,Wdq
};
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_db_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 3518] // VPHADDUDQ Vdq,Wdq
(const void *)&gInstructions[ 3590] // VPHADDUDQ Vdq,Wdq
};
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_d7_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 3520] // VPHADDUWQ Vdq,Wdq
(const void *)&gInstructions[ 3592] // VPHADDUWQ Vdq,Wdq
};
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_d6_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 3519] // VPHADDUWD Vdq,Wdq
(const void *)&gInstructions[ 3591] // VPHADDUWD Vdq,Wdq
};
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_d3_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 3516] // VPHADDUBQ Vdq,Wdq
(const void *)&gInstructions[ 3588] // VPHADDUBQ Vdq,Wdq
};
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_d2_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 3515] // VPHADDUBD Vdq,Wdq
(const void *)&gInstructions[ 3587] // VPHADDUBD Vdq,Wdq
};
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_d1_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 3517] // VPHADDUBW Vdq,Wdq
(const void *)&gInstructions[ 3589] // VPHADDUBW Vdq,Wdq
};
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_cb_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 3513] // VPHADDDQ Vdq,Wdq
(const void *)&gInstructions[ 3585] // VPHADDDQ Vdq,Wdq
};
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_c7_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 3523] // VPHADDWQ Vdq,Wdq
(const void *)&gInstructions[ 3595] // VPHADDWQ Vdq,Wdq
};
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_c6_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 3522] // VPHADDWD Vdq,Wdq
(const void *)&gInstructions[ 3594] // VPHADDWD Vdq,Wdq
};
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_c3_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 3510] // VPHADDBQ Vdq,Wdq
(const void *)&gInstructions[ 3582] // VPHADDBQ Vdq,Wdq
};
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_c2_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 3509] // VPHADDBD Vdq,Wdq
(const void *)&gInstructions[ 3581] // VPHADDBD Vdq,Wdq
};
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_c1_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 3511] // VPHADDBW Vdq,Wdq
(const void *)&gInstructions[ 3583] // VPHADDBW Vdq,Wdq
};
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_9b_w_01_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 3716] // VPSHAQ Vdq,Hdq,Wdq
(const void *)&gInstructions[ 3788] // VPSHAQ Vdq,Hdq,Wdq
};
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_9b_w_00_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 3715] // VPSHAQ Vdq,Wdq,Hdq
(const void *)&gInstructions[ 3787] // VPSHAQ Vdq,Wdq,Hdq
};
const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_9b_w =
@ -420,13 +420,13 @@ const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_9b_w =
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_9a_w_01_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 3714] // VPSHAD Vdq,Hdq,Wdq
(const void *)&gInstructions[ 3786] // VPSHAD Vdq,Hdq,Wdq
};
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_9a_w_00_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 3713] // VPSHAD Vdq,Wdq,Hdq
(const void *)&gInstructions[ 3785] // VPSHAD Vdq,Wdq,Hdq
};
const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_9a_w =
@ -441,13 +441,13 @@ const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_9a_w =
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_99_w_01_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 3718] // VPSHAW Vdq,Hdq,Wdq
(const void *)&gInstructions[ 3790] // VPSHAW Vdq,Hdq,Wdq
};
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_99_w_00_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 3717] // VPSHAW Vdq,Wdq,Hdq
(const void *)&gInstructions[ 3789] // VPSHAW Vdq,Wdq,Hdq
};
const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_99_w =
@ -462,13 +462,13 @@ const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_99_w =
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_98_w_01_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 3712] // VPSHAB Vdq,Hdq,Wdq
(const void *)&gInstructions[ 3784] // VPSHAB Vdq,Hdq,Wdq
};
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_98_w_00_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 3711] // VPSHAB Vdq,Wdq,Hdq
(const void *)&gInstructions[ 3783] // VPSHAB Vdq,Wdq,Hdq
};
const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_98_w =
@ -483,13 +483,13 @@ const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_98_w =
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_97_w_01_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 3731] // VPSHLQ Vdq,Hdq,Wdq
(const void *)&gInstructions[ 3803] // VPSHLQ Vdq,Hdq,Wdq
};
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_97_w_00_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 3730] // VPSHLQ Vdq,Wdq,Hdq
(const void *)&gInstructions[ 3802] // VPSHLQ Vdq,Wdq,Hdq
};
const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_97_w =
@ -504,13 +504,13 @@ const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_97_w =
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_96_w_01_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 3722] // VPSHLB Vdq,Hdq,Wdq
(const void *)&gInstructions[ 3794] // VPSHLB Vdq,Hdq,Wdq
};
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_96_w_00_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 3723] // VPSHLD Vdq,Wdq,Hdq
(const void *)&gInstructions[ 3795] // VPSHLD Vdq,Wdq,Hdq
};
const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_96_w =
@ -525,13 +525,13 @@ const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_96_w =
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_95_w_01_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 3721] // VPSHLB Vdq,Hdq,Wdq
(const void *)&gInstructions[ 3793] // VPSHLB Vdq,Hdq,Wdq
};
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_95_w_00_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 3732] // VPSHLW Vdq,Wdq,Hdq
(const void *)&gInstructions[ 3804] // VPSHLW Vdq,Wdq,Hdq
};
const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_95_w =
@ -546,13 +546,13 @@ const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_95_w =
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_94_w_01_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 3720] // VPSHLB Vdq,Hdq,Wdq
(const void *)&gInstructions[ 3792] // VPSHLB Vdq,Hdq,Wdq
};
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_94_w_00_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 3719] // VPSHLB Vdq,Wdq,Hdq
(const void *)&gInstructions[ 3791] // VPSHLB Vdq,Wdq,Hdq
};
const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_94_w =
@ -567,13 +567,13 @@ const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_94_w =
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_93_w_01_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 3701] // VPROTQ Vdq,Hdq,Wdq
(const void *)&gInstructions[ 3773] // VPROTQ Vdq,Hdq,Wdq
};
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_93_w_00_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 3700] // VPROTQ Vdq,Wdq,Hdq
(const void *)&gInstructions[ 3772] // VPROTQ Vdq,Wdq,Hdq
};
const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_93_w =
@ -588,13 +588,13 @@ const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_93_w =
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_92_w_01_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 3698] // VPROTD Vdq,Hdq,Wdq
(const void *)&gInstructions[ 3770] // VPROTD Vdq,Hdq,Wdq
};
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_92_w_00_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 3697] // VPROTD Vdq,Wdq,Hdq
(const void *)&gInstructions[ 3769] // VPROTD Vdq,Wdq,Hdq
};
const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_92_w =
@ -609,13 +609,13 @@ const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_92_w =
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_91_w_01_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 3704] // VPROTW Vdq,Hdq,Wdq
(const void *)&gInstructions[ 3776] // VPROTW Vdq,Hdq,Wdq
};
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_91_w_00_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 3703] // VPROTW Vdq,Wdq,Hdq
(const void *)&gInstructions[ 3775] // VPROTW Vdq,Wdq,Hdq
};
const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_91_w =
@ -630,13 +630,13 @@ const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_91_w =
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_90_w_01_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 3695] // VPROTB Vdq,Hdq,Wdq
(const void *)&gInstructions[ 3767] // VPROTB Vdq,Hdq,Wdq
};
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_90_w_00_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 3694] // VPROTB Vdq,Wdq,Hdq
(const void *)&gInstructions[ 3766] // VPROTB Vdq,Wdq,Hdq
};
const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_90_w =
@ -651,31 +651,31 @@ const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_90_w =
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_83_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 3084] // VFRCZSD Vdq,Wsd
(const void *)&gInstructions[ 3127] // VFRCZSD Vdq,Wsd
};
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_82_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 3085] // VFRCZSS Vdq,Wss
(const void *)&gInstructions[ 3128] // VFRCZSS Vdq,Wss
};
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_81_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 3082] // VFRCZPD Vx,Wx
(const void *)&gInstructions[ 3125] // VFRCZPD Vx,Wx
};
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_80_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 3083] // VFRCZPS Vx,Wx
(const void *)&gInstructions[ 3126] // VFRCZPS Vx,Wx
};
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_12_modrmreg_01_modrmmod_01_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 2512] // SLWPCB Ry
(const void *)&gInstructions[ 2496] // SLWPCB Ry
};
const ND_TABLE_MODRM_MOD gXopMap_mmmmm_09_opcode_12_modrmreg_01_modrmmod =
@ -690,7 +690,7 @@ const ND_TABLE_MODRM_MOD gXopMap_mmmmm_09_opcode_12_modrmreg_01_modrmmod =
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_12_modrmreg_00_modrmmod_01_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 1328] // LLWPCB Ry
(const void *)&gInstructions[ 1318] // LLWPCB Ry
};
const ND_TABLE_MODRM_MOD gXopMap_mmmmm_09_opcode_12_modrmreg_00_modrmmod =
@ -720,13 +720,13 @@ const ND_TABLE_MODRM_REG gXopMap_mmmmm_09_opcode_12_modrmreg =
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_02_modrmreg_06_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 199] // BLCI By,Ey
(const void *)&gInstructions[ 191] // BLCI By,Ey
};
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_02_modrmreg_01_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 201] // BLCMSK By,Ey
(const void *)&gInstructions[ 193] // BLCMSK By,Ey
};
const ND_TABLE_MODRM_REG gXopMap_mmmmm_09_opcode_02_modrmreg =
@ -747,43 +747,43 @@ const ND_TABLE_MODRM_REG gXopMap_mmmmm_09_opcode_02_modrmreg =
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_01_modrmreg_07_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 2602] // T1MSKC By,Ey
(const void *)&gInstructions[ 2586] // T1MSKC By,Ey
};
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_01_modrmreg_06_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 211] // BLSIC By,Ey
(const void *)&gInstructions[ 203] // BLSIC By,Ey
};
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_01_modrmreg_05_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 200] // BLCIC By,Ey
(const void *)&gInstructions[ 192] // BLCIC By,Ey
};
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_01_modrmreg_04_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 2636] // TZMSK By,Ey
(const void *)&gInstructions[ 2620] // TZMSK By,Ey
};
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_01_modrmreg_03_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 202] // BLCS By,Ey
(const void *)&gInstructions[ 194] // BLCS By,Ey
};
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_01_modrmreg_02_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 207] // BLSFILL By,Ey
(const void *)&gInstructions[ 199] // BLSFILL By,Ey
};
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_01_modrmreg_01_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 198] // BLCFILL By,Ey
(const void *)&gInstructions[ 190] // BLCFILL By,Ey
};
const ND_TABLE_MODRM_REG gXopMap_mmmmm_09_opcode_01_modrmreg =
@ -1067,97 +1067,97 @@ const ND_TABLE_OPCODE gXopMap_mmmmm_09_opcode =
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_ef_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 3414] // VPCOMUQ Vdq,Hdq,Wdq,Ib
(const void *)&gInstructions[ 3474] // VPCOMUQ Vdq,Hdq,Wdq,Ib
};
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_ee_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 3413] // VPCOMUD Vdq,Hdq,Wdq,Ib
(const void *)&gInstructions[ 3473] // VPCOMUD Vdq,Hdq,Wdq,Ib
};
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_ed_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 3415] // VPCOMUW Vdq,Hdq,Wdq,Ib
(const void *)&gInstructions[ 3475] // VPCOMUW Vdq,Hdq,Wdq,Ib
};
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_ec_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 3412] // VPCOMUB Vdq,Hdq,Wdq,Ib
(const void *)&gInstructions[ 3472] // VPCOMUB Vdq,Hdq,Wdq,Ib
};
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_cf_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 3411] // VPCOMQ Vdq,Hdq,Wdq,Ib
(const void *)&gInstructions[ 3471] // VPCOMQ Vdq,Hdq,Wdq,Ib
};
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_ce_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 3406] // VPCOMD Vdq,Hdq,Wdq,Ib
(const void *)&gInstructions[ 3466] // VPCOMD Vdq,Hdq,Wdq,Ib
};
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_cd_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 3416] // VPCOMW Vdq,Hdq,Wdq,Ib
(const void *)&gInstructions[ 3476] // VPCOMW Vdq,Hdq,Wdq,Ib
};
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_cc_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 3405] // VPCOMB Vdq,Hdq,Wdq,Ib
(const void *)&gInstructions[ 3465] // VPCOMB Vdq,Hdq,Wdq,Ib
};
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_c3_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 3699] // VPROTQ Vdq,Wdq,Ib
(const void *)&gInstructions[ 3771] // VPROTQ Vdq,Wdq,Ib
};
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_c2_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 3696] // VPROTD Vdq,Wdq,Ib
(const void *)&gInstructions[ 3768] // VPROTD Vdq,Wdq,Ib
};
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_c1_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 3702] // VPROTW Vdq,Wdq,Ib
(const void *)&gInstructions[ 3774] // VPROTW Vdq,Wdq,Ib
};
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_c0_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 3693] // VPROTB Vdq,Wdq,Ib
(const void *)&gInstructions[ 3765] // VPROTB Vdq,Wdq,Ib
};
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_b6_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 3556] // VPMADCSWD Vdq,Hdq,Wdq,Ldq
(const void *)&gInstructions[ 3628] // VPMADCSWD Vdq,Hdq,Wdq,Ldq
};
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_a6_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 3555] // VPMADCSSWD Vdq,Hdq,Wdq,Ldq
(const void *)&gInstructions[ 3627] // VPMADCSSWD Vdq,Hdq,Wdq,Ldq
};
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_a3_w_01_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 3684] // VPPERM Vx,Hx,Lx,Wx
(const void *)&gInstructions[ 3756] // VPPERM Vx,Hx,Lx,Wx
};
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_a3_w_00_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 3683] // VPPERM Vx,Hx,Wx,Lx
(const void *)&gInstructions[ 3755] // VPPERM Vx,Hx,Wx,Lx
};
const ND_TABLE_EX_W gXopMap_mmmmm_08_opcode_a3_w =
@ -1172,13 +1172,13 @@ const ND_TABLE_EX_W gXopMap_mmmmm_08_opcode_a3_w =
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_a2_w_01_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 3376] // VPCMOV Vx,Hx,Lx,Wx
(const void *)&gInstructions[ 3436] // VPCMOV Vx,Hx,Lx,Wx
};
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_a2_w_00_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 3375] // VPCMOV Vx,Hx,Wx,Lx
(const void *)&gInstructions[ 3435] // VPCMOV Vx,Hx,Wx,Lx
};
const ND_TABLE_EX_W gXopMap_mmmmm_08_opcode_a2_w =
@ -1193,61 +1193,61 @@ const ND_TABLE_EX_W gXopMap_mmmmm_08_opcode_a2_w =
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_9f_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 3546] // VPMACSDQH Vdq,Hdq,Wdq,Ldq
(const void *)&gInstructions[ 3618] // VPMACSDQH Vdq,Hdq,Wdq,Ldq
};
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_9e_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 3545] // VPMACSDD Vdq,Hdq,Wdq,Ldq
(const void *)&gInstructions[ 3617] // VPMACSDD Vdq,Hdq,Wdq,Ldq
};
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_97_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 3547] // VPMACSDQL Vdq,Hdq,Wdq,Ldq
(const void *)&gInstructions[ 3619] // VPMACSDQL Vdq,Hdq,Wdq,Ldq
};
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_96_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 3553] // VPMACSWD Vdq,Hdq,Wdq,Ldq
(const void *)&gInstructions[ 3625] // VPMACSWD Vdq,Hdq,Wdq,Ldq
};
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_95_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 3554] // VPMACSWW Vdq,Hdq,Wdq,Ldq
(const void *)&gInstructions[ 3626] // VPMACSWW Vdq,Hdq,Wdq,Ldq
};
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_8f_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 3549] // VPMACSSDQH Vdq,Hdq,Wdq,Ldq
(const void *)&gInstructions[ 3621] // VPMACSSDQH Vdq,Hdq,Wdq,Ldq
};
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_8e_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 3548] // VPMACSSDD Vdq,Hdq,Wdq,Ldq
(const void *)&gInstructions[ 3620] // VPMACSSDD Vdq,Hdq,Wdq,Ldq
};
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_87_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 3550] // VPMACSSDQL Vdq,Hdq,Wdq,Ldq
(const void *)&gInstructions[ 3622] // VPMACSSDQL Vdq,Hdq,Wdq,Ldq
};
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_86_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 3551] // VPMACSSWD Vdq,Hdq,Wdq,Ldq
(const void *)&gInstructions[ 3623] // VPMACSSWD Vdq,Hdq,Wdq,Ldq
};
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_85_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[ 3552] // VPMACSSWW Vdq,Hdq,Wdq,Ldq
(const void *)&gInstructions[ 3624] // VPMACSSWW Vdq,Hdq,Wdq,Ldq
};
const ND_TABLE_OPCODE gXopMap_mmmmm_08_opcode =

1
bddisasm/include/bdx86_tabledefs.h
View File

@ -459,6 +459,7 @@ typedef enum _ND_OPERAND_TYPE_SPEC
ND_OPT_pCX, // [rCX]
ND_OPT_pBXAL, // [rBX + AL]
ND_OPT_pDI, // [rDI]
ND_OPT_pBP, // [rBP]
ND_OPT_SHS, // Shadow stack.
ND_OPT_SHSP, // Shadow stack pointed by the SSP.
ND_OPT_SHS0, // Shadow stack pointed by the SSP.

20
bdshemu/bdshemu.c
View File

@ -63,9 +63,6 @@ shemu_memcpy(
ND_SIZET Size
)
{
void *start = Dest;
ND_UINT32 index = 0;
if (ND_NULL == Dest)
{
return ND_NULL;
@ -76,14 +73,12 @@ shemu_memcpy(
return ND_NULL;
}
while (Size--)
for (ND_SIZET index = 0; index < Size; index++)
{
*(char *)Dest = *((char *)Source + index);
Dest = (char *)Dest + 1;
index++;
((char *)Dest)[index] = ((const char *)Source)[index];
}
return start;
return Dest;
}
@ -206,7 +201,8 @@ ShemuIsShellcodePtr(
)
{
return (Gla >= Context->ShellcodeBase && Gla < Context->ShellcodeBase + Context->ShellcodeSize &&
Gla + Size > Context->ShellcodeBase && Gla + Size <= Context->ShellcodeBase + Context->ShellcodeSize);
Gla + Size > Context->ShellcodeBase && Gla + Size <= Context->ShellcodeBase + Context->ShellcodeSize &&
Size <= Context->ShellcodeSize);
}
@ -221,7 +217,8 @@ ShemuIsStackPtr(
)
{
return (Gla >= Context->StackBase && Gla < Context->StackBase + Context->StackSize &&
Gla + Size > Context->StackBase && Gla + Size <= Context->StackBase + Context->StackSize);
Gla + Size > Context->StackBase && Gla + Size <= Context->StackBase + Context->StackSize &&
Size <= Context->StackSize);
}
@ -236,7 +233,8 @@ ShemuIsIcachePtr(
)
{
return (Gla >= Context->Icache.Address && Gla < Context->Icache.Address + Context->Icache.Size &&
Gla + Size > Context->Icache.Address && Gla + Size <= Context->Icache.Address + Context->Icache.Size);
Gla + Size > Context->Icache.Address && Gla + Size <= Context->Icache.Address + Context->Icache.Size &&
Size <= Context->Icache.Size);
}

20
bdshemu/bdshemu_x86.c
View File

@ -2240,7 +2240,7 @@ ShemuX86Emulate(
}
else
{
ND_SINT64 val = ND_SIGN_EX(dst.Size, dst.Value.Qwords[0]);
ND_SINT64 val = (ND_SINT64)ND_SIGN_EX(dst.Size, dst.Value.Qwords[0]);
val = val >> src.Value.Qwords[0];
res.Value.Qwords[0] = (ND_UINT64)val;
}
@ -2761,7 +2761,7 @@ check_far_branch:
}
else
{
res.Value.Words[0] = (ND_SINT8)dst.Value.Bytes[0] * (ND_SINT8)src.Value.Bytes[0];
res.Value.Words[0] = (ND_UINT16)((ND_SINT8)dst.Value.Bytes[0] * (ND_SINT8)src.Value.Bytes[0]);
}
}
else if (dst.Size == 2)
@ -2772,7 +2772,7 @@ check_far_branch:
}
else
{
res.Value.Dwords[0] = (ND_SINT16)dst.Value.Words[0] * (ND_SINT16)src.Value.Words[0];
res.Value.Dwords[0] = (ND_UINT32)((ND_SINT16)dst.Value.Words[0] * (ND_SINT16)src.Value.Words[0]);
}
}
else if (dst.Size == 4)
@ -2783,7 +2783,7 @@ check_far_branch:
}
else
{
res.Value.Qwords[0] = (ND_SINT64)(ND_SINT32)dst.Value.Dwords[0] * (ND_SINT64)(ND_SINT32)src.Value.Dwords[0];
res.Value.Qwords[0] = (ND_UINT64)((ND_SINT64)(ND_SINT32)dst.Value.Dwords[0] * (ND_SINT64)(ND_SINT32)src.Value.Dwords[0]);
}
}
else
@ -2916,8 +2916,8 @@ check_far_branch:
break;
}
res.Value.Bytes[0] = (ND_SINT8)((ND_SINT16)divident / (ND_SINT8)src.Value.Bytes[0]);
res.Value.Bytes[1] = (ND_SINT8)((ND_SINT16)divident % (ND_SINT8)src.Value.Bytes[0]);
res.Value.Bytes[0] = (ND_UINT8)(ND_SINT8)((ND_SINT16)divident / (ND_SINT8)src.Value.Bytes[0]);
res.Value.Bytes[1] = (ND_UINT8)(ND_SINT8)((ND_SINT16)divident % (ND_SINT8)src.Value.Bytes[0]);
}
// Result in AX (AL - quotient, AH - reminder).
@ -2949,8 +2949,8 @@ check_far_branch:
break;
}
res.Value.Words[0] = (ND_SINT16)((ND_SINT32)divident / (ND_SINT16)src.Value.Words[0]);
res.Value.Words[1] = (ND_SINT16)((ND_SINT32)divident % (ND_SINT16)src.Value.Words[0]);
res.Value.Words[0] = (ND_UINT16)(ND_SINT16)((ND_SINT32)divident / (ND_SINT16)src.Value.Words[0]);
res.Value.Words[1] = (ND_UINT16)(ND_SINT16)((ND_SINT32)divident % (ND_SINT16)src.Value.Words[0]);
}
ShemuX86SetGprValue(Context, NDR_DX, 2, res.Value.Words[1], ND_FALSE);
@ -2982,8 +2982,8 @@ check_far_branch:
break;
}
res.Value.Dwords[0] = (ND_SINT32)((ND_SINT64)divident / (ND_SINT32)src.Value.Dwords[0]);
res.Value.Dwords[1] = (ND_SINT32)((ND_SINT64)divident % (ND_SINT32)src.Value.Dwords[0]);
res.Value.Dwords[0] = (ND_UINT32)(ND_SINT32)((ND_SINT64)divident / (ND_SINT32)src.Value.Dwords[0]);
res.Value.Dwords[1] = (ND_UINT32)(ND_SINT32)((ND_SINT64)divident % (ND_SINT32)src.Value.Dwords[0]);
}
ShemuX86SetGprValue(Context, NDR_EDX, 4, res.Value.Dwords[1], ND_FALSE);

2
bindings/pybddisasm/setup.py
View File

@ -12,7 +12,7 @@ from setuptools import find_packages, setup, Command, Extension, Distribution
from codecs import open
VERSION = (0, 3, 0)
LIBRARY_VERSION = (2, 1, 5)
LIBRARY_VERSION = (2, 2, 0)
DIR_INCLUDE = '../../inc'
here = os.path.abspath(os.path.dirname(__file__))

8
disasmtool/disasmtool.c
View File

@ -192,6 +192,7 @@ set_to_string(
case ND_SET_AMXTILE: return "AMX-TILE";
case ND_SET_AMXCOMPLEX: return "AMX-COMPLEX";
case ND_SET_AVX: return "AVX";
case ND_SET_AVX102: return "AVX10_2";
case ND_SET_AVX2: return "AVX2";
case ND_SET_AVX2GATHER: return "AVX2GATHER";
case ND_SET_AVX5124FMAPS: return "AVX5124FMAPS";
@ -332,6 +333,13 @@ category_to_string(
case ND_CAT_AMX: return "AMX";
case ND_CAT_APX: return "APX";
case ND_CAT_AVX: return "AVX";
case ND_CAT_AVX10BF16: return "AVX10BF16";
case ND_CAT_AVX10CMPSFP: return "AVX10CMPSFP";
case ND_CAT_AVX10CONVERT: return "AVX10CONVERT";
case ND_CAT_AVX10INT: return "AVX10INT";
case ND_CAT_AVX10MINMAX: return "AVX10MINMAX";
case ND_CAT_AVX10PARTCOPY: return "AVX10PARTCOPY";
case ND_CAT_AVX10SCONVERT: return "AVX10SCONVERT";
case ND_CAT_AVX2: return "AVX2";
case ND_CAT_AVX2GATHER: return "AVX2GATHER";
case ND_CAT_AVX512: return "AVX512";

1
inc/bddisasm_status.h
View File

@ -49,6 +49,7 @@ typedef ND_UINT32 NDSTATUS;
#define ND_STATUS_INVALID_TILE_REGS 0x80000043 // Tile registers are not unique.
#define ND_STATUS_INVALID_DEST_REGS 0x80000044 // Destination register is not unique (used as src).
#define ND_STATUS_INVALID_EVEX_BYTE3 0x80000045 // EVEX payload byte 3 is invalid.
#define ND_STATUS_BAD_EVEX_U 0x80000046 // EVEX.U field is invalid.
// Not encoding specific.

4
inc/bddisasm_version.h
View File

@ -6,8 +6,8 @@
#define BDDISASM_VERSION_H
#define DISASM_VERSION_MAJOR 2
#define DISASM_VERSION_MINOR 1
#define DISASM_VERSION_REVISION 5
#define DISASM_VERSION_MINOR 2
#define DISASM_VERSION_REVISION 0
#define SHEMU_VERSION_MAJOR DISASM_VERSION_MAJOR
#define SHEMU_VERSION_MINOR DISASM_VERSION_MINOR

90
inc/bdx86_constants.h
View File

@ -646,6 +646,7 @@ typedef enum _ND_INS_CLASS
ND_INS_RETN,
ND_INS_RMPADJUST,
ND_INS_RMPQUERY,
ND_INS_RMPREAD,
ND_INS_RMPUPDATE,
ND_INS_ROL,
ND_INS_ROR,
@ -760,6 +761,7 @@ typedef enum _ND_INS_CLASS
ND_INS_V4FMADDSS,
ND_INS_V4FNMADDPS,
ND_INS_V4FNMADDSS,
ND_INS_VADDNEPBF16,
ND_INS_VADDPD,
ND_INS_VADDPH,
ND_INS_VADDPS,
@ -802,6 +804,7 @@ typedef enum _ND_INS_CLASS
ND_INS_VBROADCASTI64X4,
ND_INS_VBROADCASTSD,
ND_INS_VBROADCASTSS,
ND_INS_VCMPPBF16,
ND_INS_VCMPPD,
ND_INS_VCMPPH,
ND_INS_VCMPPS,
@ -813,14 +816,34 @@ typedef enum _ND_INS_CLASS
ND_INS_VCOMISS,
ND_INS_VCOMPRESSPD,
ND_INS_VCOMPRESSPS,
ND_INS_VCOMSBF16,
ND_INS_VCOMXSD,
ND_INS_VCOMXSH,
ND_INS_VCOMXSS,
ND_INS_VCVT2PS2PHX,
ND_INS_VCVTBIASPH2BF8,
ND_INS_VCVTBIASPH2BF8S,
ND_INS_VCVTBIASPH2HF8,
ND_INS_VCVTBIASPH2HF8S,
ND_INS_VCVTDQ2PD,
ND_INS_VCVTDQ2PH,
ND_INS_VCVTDQ2PS,
ND_INS_VCVTHF82PH,
ND_INS_VCVTNE2PH2BF8,
ND_INS_VCVTNE2PH2BF8S,
ND_INS_VCVTNE2PH2HF8,
ND_INS_VCVTNE2PH2HF8S,
ND_INS_VCVTNE2PS2BF16,
ND_INS_VCVTNEBF162IBS,
ND_INS_VCVTNEBF162IUBS,
ND_INS_VCVTNEEBF162PS,
ND_INS_VCVTNEEPH2PS,
ND_INS_VCVTNEOBF162PS,
ND_INS_VCVTNEOPH2PS,
ND_INS_VCVTNEPH2BF8,
ND_INS_VCVTNEPH2BF8S,
ND_INS_VCVTNEPH2HF8,
ND_INS_VCVTNEPH2HF8S,
ND_INS_VCVTNEPS2BF16,
ND_INS_VCVTPD2DQ,
ND_INS_VCVTPD2PH,
@ -829,6 +852,8 @@ typedef enum _ND_INS_CLASS
ND_INS_VCVTPD2UDQ,
ND_INS_VCVTPD2UQQ,
ND_INS_VCVTPH2DQ,
ND_INS_VCVTPH2IBS,
ND_INS_VCVTPH2IUBS,
ND_INS_VCVTPH2PD,
ND_INS_VCVTPH2PS,
ND_INS_VCVTPH2PSX,
@ -838,6 +863,8 @@ typedef enum _ND_INS_CLASS
ND_INS_VCVTPH2UW,
ND_INS_VCVTPH2W,
ND_INS_VCVTPS2DQ,
ND_INS_VCVTPS2IBS,
ND_INS_VCVTPS2IUBS,
ND_INS_VCVTPS2PD,
ND_INS_VCVTPS2PH,
ND_INS_VCVTPS2PHX,
@ -862,26 +889,44 @@ typedef enum _ND_INS_CLASS
ND_INS_VCVTSS2SH,
ND_INS_VCVTSS2SI,
ND_INS_VCVTSS2USI,
ND_INS_VCVTTNEBF162IBS,
ND_INS_VCVTTNEBF162IUBS,
ND_INS_VCVTTPD2DQ,
ND_INS_VCVTTPD2DQS,
ND_INS_VCVTTPD2QQ,
ND_INS_VCVTTPD2QQS,
ND_INS_VCVTTPD2UDQ,
ND_INS_VCVTTPD2UDQS,
ND_INS_VCVTTPD2UQQ,
ND_INS_VCVTTPD2UQQS,
ND_INS_VCVTTPH2DQ,
ND_INS_VCVTTPH2IBS,
ND_INS_VCVTTPH2IUBS,
ND_INS_VCVTTPH2QQ,
ND_INS_VCVTTPH2UDQ,
ND_INS_VCVTTPH2UQQ,
ND_INS_VCVTTPH2UW,
ND_INS_VCVTTPH2W,
ND_INS_VCVTTPS2DQ,
ND_INS_VCVTTPS2DQS,
ND_INS_VCVTTPS2IBS,
ND_INS_VCVTTPS2IUBS,
ND_INS_VCVTTPS2QQ,
ND_INS_VCVTTPS2QQS,
ND_INS_VCVTTPS2UDQ,
ND_INS_VCVTTPS2UDQS,
ND_INS_VCVTTPS2UQQ,
ND_INS_VCVTTPS2UQQS,
ND_INS_VCVTTSD2SI,
ND_INS_VCVTTSD2SIS,
ND_INS_VCVTTSD2USI,
ND_INS_VCVTTSD2USIS,
ND_INS_VCVTTSH2SI,
ND_INS_VCVTTSH2USI,
ND_INS_VCVTTSS2SI,
ND_INS_VCVTTSS2SIS,
ND_INS_VCVTTSS2USI,
ND_INS_VCVTTSS2USIS,
ND_INS_VCVTUDQ2PD,
ND_INS_VCVTUDQ2PH,
ND_INS_VCVTUDQ2PS,
@ -894,6 +939,7 @@ typedef enum _ND_INS_CLASS
ND_INS_VCVTUW2PH,
ND_INS_VCVTW2PH,
ND_INS_VDBPSADBW,
ND_INS_VDIVNEPBF16,
ND_INS_VDIVPD,
ND_INS_VDIVPH,
ND_INS_VDIVPS,
@ -902,6 +948,7 @@ typedef enum _ND_INS_CLASS
ND_INS_VDIVSS,
ND_INS_VDPBF16PS,
ND_INS_VDPPD,
ND_INS_VDPPHPS,
ND_INS_VDPPS,
ND_INS_VERR,
ND_INS_VERW,
@ -928,18 +975,21 @@ typedef enum _ND_INS_CLASS
ND_INS_VFIXUPIMMPS,
ND_INS_VFIXUPIMMSD,
ND_INS_VFIXUPIMMSS,
ND_INS_VFMADD132NEPBF16,
ND_INS_VFMADD132PD,
ND_INS_VFMADD132PH,
ND_INS_VFMADD132PS,
ND_INS_VFMADD132SD,
ND_INS_VFMADD132SH,
ND_INS_VFMADD132SS,
ND_INS_VFMADD213NEPBF16,
ND_INS_VFMADD213PD,
ND_INS_VFMADD213PH,
ND_INS_VFMADD213PS,
ND_INS_VFMADD213SD,
ND_INS_VFMADD213SH,
ND_INS_VFMADD213SS,
ND_INS_VFMADD231NEPBF16,
ND_INS_VFMADD231PD,
ND_INS_VFMADD231PH,
ND_INS_VFMADD231PS,
@ -963,18 +1013,21 @@ typedef enum _ND_INS_CLASS
ND_INS_VFMADDSUB231PS,
ND_INS_VFMADDSUBPD,
ND_INS_VFMADDSUBPS,
ND_INS_VFMSUB132NEPBF16,
ND_INS_VFMSUB132PD,
ND_INS_VFMSUB132PH,
ND_INS_VFMSUB132PS,
ND_INS_VFMSUB132SD,
ND_INS_VFMSUB132SH,
ND_INS_VFMSUB132SS,
ND_INS_VFMSUB213NEPBF16,
ND_INS_VFMSUB213PD,
ND_INS_VFMSUB213PH,
ND_INS_VFMSUB213PS,
ND_INS_VFMSUB213SD,
ND_INS_VFMSUB213SH,
ND_INS_VFMSUB213SS,
ND_INS_VFMSUB231NEPBF16,
ND_INS_VFMSUB231PD,
ND_INS_VFMSUB231PH,
ND_INS_VFMSUB231PS,
@ -998,18 +1051,21 @@ typedef enum _ND_INS_CLASS
ND_INS_VFMSUBSS,
ND_INS_VFMULCPH,
ND_INS_VFMULCSH,
ND_INS_VFNMADD132NEPBF16,
ND_INS_VFNMADD132PD,
ND_INS_VFNMADD132PH,
ND_INS_VFNMADD132PS,
ND_INS_VFNMADD132SD,
ND_INS_VFNMADD132SH,
ND_INS_VFNMADD132SS,
ND_INS_VFNMADD213NEPBF16,
ND_INS_VFNMADD213PD,
ND_INS_VFNMADD213PH,
ND_INS_VFNMADD213PS,
ND_INS_VFNMADD213SD,
ND_INS_VFNMADD213SH,
ND_INS_VFNMADD213SS,
ND_INS_VFNMADD231NEPBF16,
ND_INS_VFNMADD231PD,
ND_INS_VFNMADD231PH,
ND_INS_VFNMADD231PS,
@ -1020,18 +1076,21 @@ typedef enum _ND_INS_CLASS
ND_INS_VFNMADDPS,
ND_INS_VFNMADDSD,
ND_INS_VFNMADDSS,
ND_INS_VFNMSUB132NEPBF16,
ND_INS_VFNMSUB132PD,
ND_INS_VFNMSUB132PH,
ND_INS_VFNMSUB132PS,
ND_INS_VFNMSUB132SD,
ND_INS_VFNMSUB132SH,
ND_INS_VFNMSUB132SS,
ND_INS_VFNMSUB213NEPBF16,
ND_INS_VFNMSUB213PD,
ND_INS_VFNMSUB213PH,
ND_INS_VFNMSUB213PS,
ND_INS_VFNMSUB213SD,
ND_INS_VFNMSUB213SH,
ND_INS_VFNMSUB213SS,
ND_INS_VFNMSUB231NEPBF16,
ND_INS_VFNMSUB231PD,
ND_INS_VFNMSUB231PH,
ND_INS_VFNMSUB231PS,
@ -1042,6 +1101,7 @@ typedef enum _ND_INS_CLASS
ND_INS_VFNMSUBPS,
ND_INS_VFNMSUBSD,
ND_INS_VFNMSUBSS,
ND_INS_VFPCLASSPBF16,
ND_INS_VFPCLASSPD,
ND_INS_VFPCLASSPH,
ND_INS_VFPCLASSPS,
@ -1064,12 +1124,14 @@ typedef enum _ND_INS_CLASS
ND_INS_VGATHERPF1QPS,
ND_INS_VGATHERQPD,
ND_INS_VGATHERQPS,
ND_INS_VGETEXPPBF16,
ND_INS_VGETEXPPD,
ND_INS_VGETEXPPH,
ND_INS_VGETEXPPS,
ND_INS_VGETEXPSD,
ND_INS_VGETEXPSH,
ND_INS_VGETEXPSS,
ND_INS_VGETMANTPBF16,
ND_INS_VGETMANTPD,
ND_INS_VGETMANTPH,
ND_INS_VGETMANTPS,
@ -1099,6 +1161,7 @@ typedef enum _ND_INS_CLASS
ND_INS_VMASKMOVDQU,
ND_INS_VMASKMOVPD,
ND_INS_VMASKMOVPS,
ND_INS_VMAXPBF16,
ND_INS_VMAXPD,
ND_INS_VMAXPH,
ND_INS_VMAXPS,
@ -1109,6 +1172,14 @@ typedef enum _ND_INS_CLASS
ND_INS_VMCLEAR,
ND_INS_VMFUNC,
ND_INS_VMGEXIT,
ND_INS_VMINMAXNEPBF16,
ND_INS_VMINMAXPD,
ND_INS_VMINMAXPH,
ND_INS_VMINMAXPS,
ND_INS_VMINMAXSD,
ND_INS_VMINMAXSH,
ND_INS_VMINMAXSS,
ND_INS_VMINPBF16,
ND_INS_VMINPD,
ND_INS_VMINPH,
ND_INS_VMINPS,
@ -1158,6 +1229,7 @@ typedef enum _ND_INS_CLASS
ND_INS_VMRESUME,
ND_INS_VMRUN,
ND_INS_VMSAVE,
ND_INS_VMULNEPBF16,
ND_INS_VMULPD,
ND_INS_VMULPH,
ND_INS_VMULPS,
@ -1524,16 +1596,19 @@ typedef enum _ND_INS_CLASS
ND_INS_VRCP28PS,
ND_INS_VRCP28SD,
ND_INS_VRCP28SS,
ND_INS_VRCPPBF16,
ND_INS_VRCPPH,
ND_INS_VRCPPS,
ND_INS_VRCPSH,
ND_INS_VRCPSS,
ND_INS_VREDUCENEPBF16,
ND_INS_VREDUCEPD,
ND_INS_VREDUCEPH,
ND_INS_VREDUCEPS,
ND_INS_VREDUCESD,
ND_INS_VREDUCESH,
ND_INS_VREDUCESS,
ND_INS_VRNDSCALENEPBF16,
ND_INS_VRNDSCALEPD,
ND_INS_VRNDSCALEPH,
ND_INS_VRNDSCALEPS,
@ -1552,10 +1627,12 @@ typedef enum _ND_INS_CLASS
ND_INS_VRSQRT28PS,
ND_INS_VRSQRT28SD,
ND_INS_VRSQRT28SS,
ND_INS_VRSQRTPBF16,
ND_INS_VRSQRTPH,
ND_INS_VRSQRTPS,
ND_INS_VRSQRTSH,
ND_INS_VRSQRTSS,
ND_INS_VSCALEFPBF16,
ND_INS_VSCALEFPD,
ND_INS_VSCALEFPH,
ND_INS_VSCALEFPS,
@ -1588,6 +1665,7 @@ typedef enum _ND_INS_CLASS
ND_INS_VSM3RNDS2,
ND_INS_VSM4KEY4,
ND_INS_VSM4RNDS4,
ND_INS_VSQRTNEPBF16,
ND_INS_VSQRTPD,
ND_INS_VSQRTPH,
ND_INS_VSQRTPS,
@ -1595,6 +1673,7 @@ typedef enum _ND_INS_CLASS
ND_INS_VSQRTSH,
ND_INS_VSQRTSS,
ND_INS_VSTMXCSR,
ND_INS_VSUBNEPBF16,
ND_INS_VSUBPD,
ND_INS_VSUBPH,
ND_INS_VSUBPS,
@ -1606,6 +1685,9 @@ typedef enum _ND_INS_CLASS
ND_INS_VUCOMISD,
ND_INS_VUCOMISH,
ND_INS_VUCOMISS,
ND_INS_VUCOMXSD,
ND_INS_VUCOMXSH,
ND_INS_VUCOMXSS,
ND_INS_VUNPCKHPD,
ND_INS_VUNPCKHPS,
ND_INS_VUNPCKLPD,
@ -1663,6 +1745,7 @@ typedef enum _ND_INS_SET
ND_SET_AMXTILE,
ND_SET_APX_F,
ND_SET_AVX,
ND_SET_AVX102,
ND_SET_AVX2,
ND_SET_AVX2GATHER,
ND_SET_AVX5124FMAPS,
@ -1798,6 +1881,13 @@ typedef enum _ND_INS_TYPE
ND_CAT_APX,
ND_CAT_ARITH,
ND_CAT_AVX,
ND_CAT_AVX10BF16,
ND_CAT_AVX10CMPSFP,
ND_CAT_AVX10CONVERT,
ND_CAT_AVX10INT,
ND_CAT_AVX10MINMAX,
ND_CAT_AVX10PARTCOPY,
ND_CAT_AVX10SCONVERT,
ND_CAT_AVX2,
ND_CAT_AVX2GATHER,
ND_CAT_AVX512,

44
inc/bdx86_core.h
View File

@ -347,24 +347,25 @@ typedef ND_UINT32 ND_REG_SIZE;
// Misc macros.
//
// NOTE: Macros that accept a size (in bytes) are undefined if the size is not in the interval [1, 8].
// Sign extend 8 bit to 64 bit.
#define ND_SIGN_EX_8(x) (((x) & 0x00000080) ? (0xFFFFFFFFFFFFFF00 | (x)) : ((x) & 0xFF))
#define ND_SIGN_EX_8(x) ND_SIGN_EX(1, x)
// Sign extend 16 bit to 64 bit.
#define ND_SIGN_EX_16(x) (((x) & 0x00008000) ? (0xFFFFFFFFFFFF0000 | (x)) : ((x) & 0xFFFF))
#define ND_SIGN_EX_16(x) ND_SIGN_EX(2, x)
// Sign extend 32 bit to 64 bit.
#define ND_SIGN_EX_32(x) (((x) & 0x80000000) ? (0xFFFFFFFF00000000 | (x)) : ((x) & 0xFFFFFFFF))
// Sign extend to 64 bit, with minimal branches
#define ND_SIGN_EX(sz, x) (((x) & ND_SIZE_TO_MASK(sz)) | (~ND_SIZE_TO_MASK(sz) * ND_GET_SIGN(sz, x)))
#define ND_SIGN_EX_32(x) ND_SIGN_EX(4, x)
// Sign extend sz bytes to 64 bits.
#define ND_SIGN_EX(sz, x) ((((ND_UINT64)(x)) & ND_SIZE_TO_MASK(sz)) | (~ND_SIZE_TO_MASK(sz) * ND_GET_SIGN(sz, x)))
// Trim 64 bits to sz bytes.
#define ND_TRIM(sz, x) ((sz) == 1 ? (x) & 0xFF : (sz) == 2 ? (x) & 0xFFFF : \
(sz) == 4 ? (x) & 0xFFFFFFFF : (x))
#define ND_TRIM(sz, x) ((ND_UINT64)(x) & ND_SIZE_TO_MASK(sz))
// Returns most significant bit, given size in bytes sz.
#define ND_MSB(sz, x) (((x) >> ( (sz) * 8 - 1)) & 1)
#define ND_MSB(sz, x) ((((x)) >> (((sz) * 8) - 1)) & 1)
// Returns least significant bit.
#define ND_LSB(sz, x) ((x) & 1)
// Convert a size in bytes to a bitmask.
#define ND_SIZE_TO_MASK(sz) (((sz) < 8) ? ((1ULL << ((sz) * 8)) - 1) : (0xFFFFFFFFFFFFFFFF))
#define ND_SIZE_TO_MASK(sz) (0xFFFFFFFFFFFFFFFFull >> ((8 - (sz)) * 8))
// Get bit at position bit from x.
#define ND_GET_BIT(bit, x) (((x) >> (bit)) & 1)
// Return the sign of sz bytes long value x.
@ -373,12 +374,12 @@ typedef ND_UINT32 ND_REG_SIZE;
#define ND_SET_SIGN(sz, x) ND_SIGN_EX(sz, x)
#define ND_FETCH_64(b) (((ND_UINT64)ND_FETCH_32((const ND_UINT8 *)(b))) | \
(((ND_UINT64)ND_FETCH_32((const ND_UINT8 *)(b) + 4) << 32)))
#define ND_FETCH_32(b) (((ND_UINT32)ND_FETCH_16((const ND_UINT8 *)(b))) | \
(((ND_UINT32)ND_FETCH_16((const ND_UINT8 *)(b) + 2) << 16)))
#define ND_FETCH_16(b) (((ND_UINT16)ND_FETCH_8 ((const ND_UINT8 *)(b))) | \
(((ND_UINT16)ND_FETCH_8 ((const ND_UINT8 *)(b) + 1) << 8)))
#define ND_FETCH_64(b) ((ND_UINT64)(((ND_UINT64)ND_FETCH_32((const ND_UINT8 *)(b))) | \
(((ND_UINT64)ND_FETCH_32((const ND_UINT8 *)(b) + 4) << 32))))
#define ND_FETCH_32(b) ((ND_UINT32)(((ND_UINT32)ND_FETCH_16((const ND_UINT8 *)(b))) | \
(((ND_UINT32)ND_FETCH_16((const ND_UINT8 *)(b) + 2) << 16))))
#define ND_FETCH_16(b) ((ND_UINT16)(((ND_UINT16)ND_FETCH_8 ((const ND_UINT8 *)(b))) | \
(((ND_UINT16)ND_FETCH_8 ((const ND_UINT8 *)(b) + 1) << 8))))
#define ND_FETCH_8(b) (*((const ND_UINT8 *)(b)))
@ -956,7 +957,7 @@ typedef union _ND_SIB
} ND_SIB;
//
// 2-bytes VEX. Exactly as Intel defined it.
// 2-bytes VEX prefix.
//
typedef union _ND_VEX2
{
@ -972,9 +973,8 @@ typedef union _ND_VEX2
};
} ND_VEX2;
//
// 3-bytes VEX. Exactly as Intel defined it.
// 3-bytes VEX prefix.
//
typedef union _ND_VEX3
{
@ -995,9 +995,8 @@ typedef union _ND_VEX3
};
} ND_VEX3;
//
// XOP. Exactly as AMD defined it.
// XOP prefix.
//
typedef union _ND_XOP
{
@ -1018,9 +1017,8 @@ typedef union _ND_XOP
};
} ND_XOP;
//
// EVEX prefix. Exactly as Intel defined it.
// EVEX prefix.
//
typedef union _ND_EVEX
{
@ -1037,7 +1035,7 @@ typedef union _ND_EVEX
ND_UINT8 r : 1; // ~R or ~R3
ND_UINT8 p : 2; // p0, p1
ND_UINT8 x4 : 1; // ~X4 (repurposed from a hard-coded 1 bit).
ND_UINT8 u : 1; // ~U (repurposed from a hard-coded 1 bit).
ND_UINT8 v : 4; // ~v0, ~v1, ~v2, ~v3
ND_UINT8 w : 1; // W

1
inc/bdx86_cpuidflags.h
View File

@ -136,5 +136,6 @@
#define ND_CFF_MCOMMIT ND_CFF(0x80000008, 0xFFFFFFFF, NDR_EBX, 8)
#define ND_CFF_SNP ND_CFF(0x8000001F, 0xFFFFFFFF, NDR_EAX, 4)
#define ND_CFF_RMPQUERY ND_CFF(0x8000001F, 0xFFFFFFFF, NDR_EAX, 6)
#define ND_CFF_RMPREAD ND_CFF(0x8000001F, 0xFFFFFFFF, NDR_EAX, 21)
#endif // CPUID_FLAGS_H

1
isagenerator/disasmlib.py
View File

@ -291,6 +291,7 @@ valid_impops = {# register size
'pBXALb' : ('pBXAL', 'b'), # Implicit [RBX + AL], as used by XLAT.
'pDIq' : ('pDI', 'q'), # Implicit qword [RDI].
'pDIdq' : ('pDI', 'dq'), # Implicit xmmword [RDI].
'pBP' : ('pBP', 'v'), # Implicit operand size loaded from [RBP]. RBP is subject to stack address size.
# Implicit shadow stack accesses.
'SHS' : ('SHS', 'q'), # Shadow stack (SSP) implicit access, 1 qword (use by CET instructions).

1
isagenerator/instructions/cpuid.dat
View File

@ -150,3 +150,4 @@ MCOMMIT : 0x80000008, 0xFFFFFFFF, EBX, 8
SNP : 0x8000001F, 0xFFFFFFFF, EAX, 4
RMPQUERY : 0x8000001F, 0xFFFFFFFF, EAX, 6
RMPREAD : 0x8000001F, 0xFFFFFFFF, EAX, 21

3
isagenerator/instructions/flags.dat
View File

@ -113,3 +113,6 @@ ZERO : CF=0|PF=0|AF=0|ZF=0|SF=0|OF=0
# UINTR flags access, as done by TESTUI.
UINTR : CF=m|PF=0|AF=0|ZF=0|SF=0|OF=0
# AVX 10.2 Compare Scalar FP With Enhanced EFLAGS
CMPSFP : CF=m|PF=m|AF=0|ZF=m|SF=m|OF=m

8
isagenerator/instructions/table_evex_1.dat
View File

@ -52,8 +52,12 @@ VCVTSS2SI ; Gy,Wss{er} ; ; evex m:1 p:2 l:i w:x
VCVTSD2SI ; Gy,Wsd{er} ; ; evex m:1 p:3 l:i w:x 0x2D /r ; s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R, a:IWO64
VUCOMISS ; Vdq,Wss{sae} ; Fv ; evex m:1 p:0 l:i w:0 0x2E /r ; s:AVX512F, t:AVX512, l:t1s, w:R|R|W, e:E3, f:COMIS
VUCOMISD ; Vdq,Wsd{sae} ; Fv ; evex m:1 p:1 l:i w:1 0x2E /r ; s:AVX512F, t:AVX512, l:t1s, w:R|R|W, e:E3, f:COMIS
VUCOMXSD ; Vdq,Wsd{sae} ; Fv ; evex m:1 p:2 l:0 w:1 0x2E /r ; s:AVX102, t:AVX10CMPSFP, l:t1s, w:R|R|W, e:E3NF, f:CMPSFP
VUCOMXSS ; Vdq,Wss{sae} ; Fv ; evex m:1 p:3 l:0 w:0 0x2E /r ; s:AVX102, t:AVX10CMPSFP, l:t1s, w:R|R|W, e:E3NF, f:CMPSFP
VCOMISS ; Vdq,Wss{sae} ; Fv ; evex m:1 p:0 l:i w:0 0x2F /r ; s:AVX512F, t:AVX512, l:t1s, w:R|R|W, e:E3, f:COMIS
VCOMISD ; Vdq,Wsd{sae} ; Fv ; evex m:1 p:1 l:i w:1 0x2F /r ; s:AVX512F, t:AVX512, l:t1s, w:R|R|W, e:E3, f:COMIS
VCOMXSD ; Vdq,Wsd{sae} ; Fv ; evex m:1 p:2 l:0 w:1 0x2F /r ; s:AVX102, t:AVX10CMPSFP, l:t1s, w:R|R|W, e:E3NF, f:CMPSFP
VCOMXSS ; Vdq,Wss{sae} ; Fv ; evex m:1 p:3 l:0 w:0 0x2F /r ; s:AVX102, t:AVX10CMPSFP, l:t1s, w:R|R|W, e:E3NF, f:CMPSFP
# 0x50 - 0x5F
VSQRTPS ; Vfv{K}{z},Wfv|B32{er} ; ; evex m:1 p:0 l:x w:0 0x51 /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R
@ -145,6 +149,8 @@ VPSRLDQ ; Hfv,Wfv,Ib ; ; evex m:1 p:1 l:x w:i
VPSLLQ ; Hfv{K}{z},Wfv|B64,Ib ; ; evex m:1 p:1 l:x w:1 0x73 /6 ib ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R
VPSLLDQ ; Hfv,Wfv,Ib ; ; evex m:1 p:1 l:x w:i 0x73 /7 ib ; s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:W|R|R
VPCMPEQB ; rKq{K},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0x74 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R
VCVTNEPH2BF8 ; Vhv{K}{z},Wfv|B16 ; ; evex m:1 p:2 l:x w:0 0x74 /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R
VCVTNE2PH2BF8 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:1 p:3 l:x w:0 0x74 /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R|R
VPCMPEQW ; rKq{K},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0x75 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R
VPCMPEQD ; rKq{K},Hfv,Wfv|B32 ; ; evex m:1 p:1 l:x w:i 0x76 /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R
VCVTTPS2UDQ ; Vfv{K}{z},Wfv|B32{sae} ; ; evex m:1 p:0 l:x w:0 0x78 /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R
@ -172,6 +178,7 @@ VCVTUSI2SD ; Vdq,Hdq,Ey ; ; evex m:1 p:3 l:i w:0
VCVTUSI2SD ; Vdq,Hdq{er},Ey ; ; evex m:1 p:3 l:i w:1 0x7B /r ; s:AVX512F, t:CONVERT, l:t1s, e:E3, w:W|R|R, a:IWO64
VMOVD ; Ey,Vdq ; ; evex m:1 p:1 l:0 w:0 0x7E /r ; s:AVX512F, t:DATAXFER, l:t1s, e:E9NF, w:W|R, a:IWO64
VMOVQ ; Ey,Vdq ; ; evex m:1 p:1 l:0 w:1 0x7E /r ; s:AVX512F, t:DATAXFER, l:t1s, e:E9NF, w:W|R, a:IWO64
VMOVD ; Vdq,Wd ; ; evex m:1 p:2 l:0 w:0 0x7E /r ; s:AVX102, t:AVX10PARTCOPY, l:t1s, e:E9NF, w:W|R
VMOVQ ; Vdq,Wq ; ; evex m:1 p:2 l:0 w:1 0x7E /r ; s:AVX512F, t:DATAXFER, l:t1s, e:E9NF, w:W|R
VMOVDQA32 ; Wfv{K}{z},Vfv ; ; evex m:1 p:1 l:x w:0 0x7F /r ; s:AVX512F, t:DATAXFER, l:fvm, e:E1, w:W|R|R
VMOVDQA64 ; Wfv{K}{z},Vfv ; ; evex m:1 p:1 l:x w:1 0x7F /r ; s:AVX512F, t:DATAXFER, l:fvm, e:E1, w:W|R|R
@ -205,6 +212,7 @@ VPSRLD ; Vfv{K}{z},Hfv,Wdq ; ; evex m:1 p:1 l:x w:0
VPSRLQ ; Vfv{K}{z},Hfv,Wdq ; ; evex m:1 p:1 l:x w:1 0xD3 /r ; s:AVX512F, t:AVX512, l:m128, e:E4NFnb, w:W|R|R|R
VPADDQ ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:1 p:1 l:x w:1 0xD4 /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R
VPMULLW ; Vfv{K}{z},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0xD5 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R
VMOVD ; Wd,Vdq ; ; evex m:1 p:1 l:0 w:0 0xD6 /r ; s:AVX102, t:AVX10PARTCOPY, l:t1s, e:E9NF, w:W|R
VMOVQ ; Wq,Vdq ; ; evex m:1 p:1 l:0 w:1 0xD6 /r ; s:AVX512F, t:DATAXFER, l:t1s, e:E9NF, w:W|R
VPSUBUSB ; Vfv{K}{z},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0xD8 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4, w:W|R|R|R
VPSUBUSW ; Vfv{K}{z},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0xD9 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4, w:W|R|R|R

15
isagenerator/instructions/table_evex_2.dat
View File

@ -135,8 +135,15 @@ VRSQRT14SS ; Vdq{K}{z},Hdq,Wss ; ; evex m:2 p:1 l:x w:0
VRSQRT14SD ; Vdq{K}{z},Hdq,Wsd ; ; evex m:2 p:1 l:x w:1 0x4F /r ; s:AVX512F, t:AVX512, l:t1s, e:E10, w:W|R|R|R
# 0x50 - 0x5F
VPDPBUUD ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:0 l:x w:0 0x50 /r ; s:AVX102, t:AVX10INT, l:fv, e:E4, w:RW|R|R|R
VPDPBUSD ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:1 l:x w:0 0x50 /r ; s:AVX512VNNI, t:VNNI, l:fv, e:E4, w:RW|R|R|R
VPDPBSUD ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:2 l:x w:0 0x50 /r ; s:AVX102, t:AVX10INT, l:fv, e:E4, w:RW|R|R|R
VPDPBSSD ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:3 l:x w:0 0x50 /r ; s:AVX102, t:AVX10INT, l:fv, e:E4, w:RW|R|R|R
VPDPBUUDS ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:0 l:x w:0 0x51 /r ; s:AVX102, t:AVX10INT, l:fv, e:E4, w:RW|R|R|R
VPDPBUSDS ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:1 l:x w:0 0x51 /r ; s:AVX512VNNI, t:VNNI, l:fv, e:E4, w:RW|R|R|R
VPDPBSUDS ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:2 l:x w:0 0x51 /r ; s:AVX102, t:AVX10INT, l:fv, e:E4, w:RW|R|R|R
VPDPBSSDS ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:3 l:x w:0 0x51 /r ; s:AVX102, t:AVX10INT, l:fv, e:E4, w:RW|R|R|R
VDPPHPS ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:0 l:x w:0 0x52 /r ; s:AVX102, t:AVX10INT, l:fv, e:E4, w:RW|R|R|R
VPDPWSSD ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:1 l:x w:0 0x52 /r ; s:AVX512VNNI, t:VNNI, l:fv, e:E4, w:RW|R|R|R
VDPBF16PS ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:2 l:x w:0 0x52 /r ; s:AVX512BF16, t:AVX512BF16, l:fv, e:E4, w:W|R|R|R
VP4DPWSSD ; Voq{K}{z},Hoq+3,Mdq ; ; evex m:2 p:3 l:2 w:0 0x52 /r:mem ; s:AVX5124VNNIW, t:VNNIW, l:t1_4x, e:E4, w:RW|R|R|R
@ -165,6 +172,7 @@ VBLENDMPS ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:1 l:x w:0
VBLENDMPD ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:2 p:1 l:x w:1 0x65 /r ; s:AVX512F, t:BLEND, l:fv, e:E4, w:W|R|R|R
VPBLENDMB ; Vfv{K}{z},Hfv,Wfv ; ; evex m:2 p:1 l:x w:0 0x66 /r ; s:AVX512BW, t:BLEND, l:fvm, e:E4, w:W|R|R|R
VPBLENDMW ; Vfv{K}{z},Hfv,Wfv ; ; evex m:2 p:1 l:x w:1 0x66 /r ; s:AVX512BW, t:BLEND, l:fvm, e:E4, w:W|R|R|R
VCVT2PS2PHX ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0x67 /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R|R
VP2INTERSECTD ; rKq+1,Hfv,Wfv|B32 ; ; evex m:2 p:3 l:x w:0 0x68 /r ; s:AVX512VP2INTERSECT, t:AVX512VP2INTERSECT, l:fv, e:E4NF, w:W|R|R
VP2INTERSECTQ ; rKq+1,Hfv,Wfv|B64 ; ; evex m:2 p:3 l:x w:1 0x68 /r ; s:AVX512VP2INTERSECT, t:AVX512VP2INTERSECT, l:fv, e:E4NF, w:W|R|R
@ -178,6 +186,7 @@ VCVTNEPS2BF16 ; Vhv{K}{z},Wfv|B32 ; ; evex m:2 p:2 l:x w:0
VCVTNE2PS2BF16 ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:3 l:x w:0 0x72 /r ; s:AVX512BF16, t:AVX512BF16, l:fv, e:E4NF, w:W|R|R|R
VPSHRDVD ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:1 l:x w:0 0x73 /r ; s:AVX512VBMI2, t:AVX512VBMI, l:fv, e:E4, w:RW|R|R|R
VPSHRDVQ ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:2 p:1 l:x w:1 0x73 /r ; s:AVX512VBMI2, t:AVX512VBMI, l:fv, e:E4, w:RW|R|R|R
VCVTBIASPH2BF8 ; Vhv{K}{z},Hfv,Wfv|B16 ; ; evex m:2 p:0 l:x w:0 0x74 /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R|R
VPERMI2B ; Vfv{K}{z},Hfv,Wfv ; ; evex m:2 p:1 l:x w:0 0x75 /r ; s:AVX512VBMI, t:AVX512VBMI, l:fvm, e:E4NFnb, w:RW|R|R|R
VPERMI2W ; Vfv{K}{z},Hfv,Wfv ; ; evex m:2 p:1 l:x w:1 0x75 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:RW|R|R|R
@ -335,6 +344,12 @@ VRSQRT28SD ; Vdq{K}{z},Hdq,Wsd{sae} ; ; evex m:2 p:1 l:i w:1
VGF2P8MULB ; Vfv{K}{z},Hfv,Wfv ; ; evex m:2 p:1 l:x w:0 0xCF /r ; s:GFNI, t:GFNI, l:fvm, e:E4, w:W|R|R|R
# 0xD0 - 0xDF
VPDPWUUD ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:0 l:x w:0 0xD2 /r ; s:AVX102, t:AVX10INT, l:fv, e:E4, w:RW|R|R|R
VPDPWUSD ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:1 l:x w:0 0xD2 /r ; s:AVX102, t:AVX10INT, l:fv, e:E4, w:RW|R|R|R
VPDPWSUD ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:2 l:x w:0 0xD2 /r ; s:AVX102, t:AVX10INT, l:fv, e:E4, w:RW|R|R|R
VPDPWUUDS ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:0 l:x w:0 0xD3 /r ; s:AVX102, t:AVX10INT, l:fv, e:E4, w:RW|R|R|R
VPDPWUSDS ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:1 l:x w:0 0xD3 /r ; s:AVX102, t:AVX10INT, l:fv, e:E4, w:RW|R|R|R
VPDPWSUDS ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:2 l:x w:0 0xD3 /r ; s:AVX102, t:AVX10INT, l:fv, e:E4, w:RW|R|R|R
VAESENC ; Vfv,Hfv,Wfv ; ; evex m:2 p:1 l:x w:i 0xDC /r ; s:VAES, t:VAES, l:fvm, e:E4NF, w:W|R|R
VAESENCLAST ; Vfv,Hfv,Wfv ; ; evex m:2 p:1 l:x w:i 0xDD /r ; s:VAES, t:VAES, l:fvm, e:E4NF, w:W|R|R
VAESDEC ; Vfv,Hfv,Wfv ; ; evex m:2 p:1 l:x w:i 0xDE /r ; s:VAES, t:VAES, l:fvm, e:E4NF, w:W|R|R

13
isagenerator/instructions/table_evex_3.dat
View File

@ -12,6 +12,7 @@ VPERMILPS ; Vfv{K}{z},Wfv|B32,Ib ; ; evex m:3 p:1 l:x w:0
VPERMILPD ; Vfv{K}{z},Wfv|B64,Ib ; ; evex m:3 p:1 l:x w:1 0x05 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R
VRNDSCALEPH ; Vfv{K}{z},Wfv|B16{sae},Ib ; ; evex m:3 p:0 l:x w:0 0x08 /r ib ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R
VRNDSCALEPS ; Vfv{K}{z},Wfv|B32{sae},Ib ; ; evex m:3 p:1 l:x w:0 0x08 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R
VRNDSCALENEPBF16 ; Vfv{K}{z},Wfv|B16,Ib ; ; evex m:3 p:3 l:x w:0 0x08 /r ib ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:W|R|R|R
VRNDSCALEPD ; Vfv{K}{z},Wfv|B64{sae},Ib ; ; evex m:3 p:1 l:x w:1 0x09 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R
VRNDSCALESH ; Vdq{K}{z},Hdq,Wsh{sae},Ib ; ; evex m:3 p:0 l:i w:0 0x0A /r ib ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R|R
VRNDSCALESS ; Vdq{K}{z},Hdq,Wss{sae},Ib ; ; evex m:3 p:1 l:i w:0 0x0A /r ib ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R
@ -57,6 +58,7 @@ VPTERNLOGQ ; Vfv{K}{z},Hfv,Wfv|B64,Ib ; ; evex m:3 p:1 l:x w:1
VGETMANTPH ; Vfv{K}{z},Wfv|B16{sae},Ib ; ; evex m:3 p:0 l:x w:0 0x26 /r ib ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R
VGETMANTPS ; Vfv{K}{z},Wfv|B32{sae},Ib ; ; evex m:3 p:1 l:x w:0 0x26 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R
VGETMANTPD ; Vfv{K}{z},Wfv|B64{sae},Ib ; ; evex m:3 p:1 l:x w:1 0x26 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R
VGETMANTPBF16 ; Vfv{K}{z},Wfv|B16,Ib ; ; evex m:3 p:3 l:x w:0 0x26 /r ib ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:W|R|R|R
VGETMANTSH ; Vdq{K}{z},Hdq,Wsh{sae},Ib ; ; evex m:3 p:0 l:i w:0 0x27 /r ib ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R|R
VGETMANTSS ; Vdq{K}{z},Hdq,Wss{sae},Ib ; ; evex m:3 p:1 l:i w:0 0x27 /r ib ; s:AVX512F, t:AVX512, l:t1s, e:E2, w:W|R|R|R|R
VGETMANTSD ; Vdq{K}{z},Hdq,Wsd{sae},Ib ; ; evex m:3 p:1 l:i w:1 0x27 /r ib ; s:AVX512F, t:AVX512, l:t1s, e:E2, w:W|R|R|R|R
@ -77,6 +79,7 @@ VPCMPW ; rKq{K},Hfv,Wfv,Ib ; ; evex m:3 p:1 l:x w:1
# 0x40 - 0x4F
VDBPSADBW ; Vfv{K}{z},Hfv,Wfv,Ib ; ; evex m:3 p:1 l:x w:0 0x42 /r ib ; s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:W|R|R|R|R
VMPSADBW ; Vfv{K}{z},Hfv,Wfv,Ib ; ; evex m:3 p:2 l:x w:0 0x42 /r ib ; s:AVX102, t:AVX10INT, l:fvm, e:E4NF, w:W|R|R|R|R
VSHUFI32X4 ; Vuv{K}{z},Huv,Wuv|B32,Ib ; ; evex m:3 p:1 l:x w:0 0x43 /r ib ; s:AVX512F, t:AVX512, a:NOL0, l:fv, e:E4NF, w:W|R|R|R|R
VSHUFI64X2 ; Vuv{K}{z},Huv,Wuv|B64,Ib ; ; evex m:3 p:1 l:x w:1 0x43 /r ib ; s:AVX512F, t:AVX512, a:NOL0, l:fv, e:E4NF, w:W|R|R|R|R
VPCLMULQDQ ; Vfv,Hfv,Wfv,Ib ; ; evex m:3 p:1 l:x w:i 0x44 /r ib ; s:VPCLMULQDQ, t:VPCLMULQDQ, l:fvm, e:E4NF, w:W|R|R|R
@ -86,6 +89,13 @@ VRANGEPS ; Vfv{K}{z},Hfv,Wfv|B32{sae},Ib ; ; evex m:3 p:1 l:x w:0
VRANGEPD ; Vfv{K}{z},Hfv,Wfv|B64{sae},Ib ; ; evex m:3 p:1 l:x w:1 0x50 /r ib ; s:AVX512DQ, t:AVX512, l:fv, e:E2, w:W|R|R|R|R
VRANGESS ; Vdq{K}{z},Hdq,Wss{sae},Ib ; ; evex m:3 p:1 l:i w:0 0x51 /r ib ; s:AVX512DQ, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R
VRANGESD ; Vdq{K}{z},Hdq,Wsd{sae},Ib ; ; evex m:3 p:1 l:i w:1 0x51 /r ib ; s:AVX512DQ, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R
VMINMAXPH ; Vfv{K}{z},Hfv,Wfv|B16{sae},Ib ; ; evex m:3 p:0 l:x w:0 0x52 /r ib ; s:AVX102, t:AVX10MINMAX, l:fv, e:E2, w:W|R|R|R|R
VMINMAXPS ; Vfv{K}{z},Hfv,Wfv|B32{sae},Ib ; ; evex m:3 p:1 l:x w:0 0x52 /r ib ; s:AVX102, t:AVX10MINMAX, l:fv, e:E2, w:W|R|R|R|R
VMINMAXPD ; Vfv{K}{z},Hfv,Wfv|B64{sae},Ib ; ; evex m:3 p:1 l:x w:1 0x52 /r ib ; s:AVX102, t:AVX10MINMAX, l:fv, e:E2, w:W|R|R|R|R
VMINMAXNEPBF16 ; Vfv{K}{z},Hfv,Wfv|B16,Ib ; ; evex m:3 p:3 l:x w:0 0x52 /r ib ; s:AVX102, t:AVX10MINMAX, l:fv, e:E4, w:W|R|R|R|R
VMINMAXSH ; Vdq{K}{z},Hdq,Wsh{sae},Ib ; ; evex m:3 p:0 l:i w:0 0x53 /r ib ; s:AVX102, t:AVX10MINMAX, l:t1s, e:E3, w:W|R|R|R|R
VMINMAXSS ; Vdq{K}{z},Hdq,Wss{sae},Ib ; ; evex m:3 p:1 l:i w:0 0x53 /r ib ; s:AVX102, t:AVX10MINMAX, l:t1s, e:E3, w:W|R|R|R|R
VMINMAXSD ; Vdq{K}{z},Hdq,Wsd{sae},Ib ; ; evex m:3 p:1 l:i w:1 0x53 /r ib ; s:AVX102, t:AVX10MINMAX, l:t1s, e:E3, w:W|R|R|R|R
VFIXUPIMMPS ; Vfv{K}{z},Hfv,Wfv|B32{sae},Ib ; ; evex m:3 p:1 l:x w:0 0x54 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E2, w:RW|R|R|R|R
VFIXUPIMMPD ; Vfv{K}{z},Hfv,Wfv|B64{sae},Ib ; ; evex m:3 p:1 l:x w:1 0x54 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E2, w:RW|R|R|R|R
VFIXUPIMMSS ; Vdq{K}{z},Hdq,Wss{sae},Ib ; ; evex m:3 p:1 l:i w:0 0x55 /r ib ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:RW|R|R|R|R
@ -93,6 +103,7 @@ VFIXUPIMMSD ; Vdq{K}{z},Hdq,Wsd{sae},Ib ; ; evex m:3 p:1 l:i w:1
VREDUCEPH ; Vfv{K}{z},Wfv|B16{sae},Ib ; ; evex m:3 p:0 l:x w:0 0x56 /r ib ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R
VREDUCEPS ; Vfv{K}{z},Wfv|B32{sae},Ib ; ; evex m:3 p:1 l:x w:0 0x56 /r ib ; s:AVX512DQ, t:AVX512, l:fv, e:E2, w:W|R|R|R
VREDUCEPD ; Vfv{K}{z},Wfv|B64{sae},Ib ; ; evex m:3 p:1 l:x w:1 0x56 /r ib ; s:AVX512DQ, t:AVX512, l:fv, e:E2, w:W|R|R|R
VREDUCENEPBF16 ; Vfv{K}{z},Wfv|B16,Ib ; ; evex m:3 p:3 l:x w:0 0x56 /r ib ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:W|R|R|R
VREDUCESH ; Vdq{K}{z},Hdq,Wsh{sae},Ib ; ; evex m:3 p:0 l:i w:0 0x57 /r ib ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R|R
VREDUCESS ; Vdq{K}{z},Hdq,Wss{sae},Ib ; ; evex m:3 p:1 l:i w:0 0x57 /r ib ; s:AVX512DQ, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R
VREDUCESD ; Vdq{K}{z},Hdq,Wsd{sae},Ib ; ; evex m:3 p:1 l:i w:1 0x57 /r ib ; s:AVX512DQ, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R
@ -101,6 +112,7 @@ VREDUCESD ; Vdq{K}{z},Hdq,Wsd{sae},Ib ; ; evex m:3 p:1 l:i w:1
VFPCLASSPH ; rKq{K},Wfv|B16,Ib ; ; evex m:3 p:0 l:x w:0 0x66 /r ib ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E4, w:W|R|R|R
VFPCLASSPS ; rKq{K},Wfv|B32,Ib ; ; evex m:3 p:1 l:x w:0 0x66 /r ib ; s:AVX512DQ, t:AVX512, l:fv, e:E4, w:W|R|R|R
VFPCLASSPD ; rKq{K},Wfv|B64,Ib ; ; evex m:3 p:1 l:x w:1 0x66 /r ib ; s:AVX512DQ, t:AVX512, l:fv, e:E4, w:W|R|R|R
VFPCLASSPBF16 ; rKq{K},Wfv|B16,Ib ; ; evex m:3 p:3 l:x w:0 0x66 /r ib ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:W|R|R|R
VFPCLASSSH ; rKq{K},Wsh,Ib ; ; evex m:3 p:0 l:i w:0 0x67 /r ib ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E10, w:W|R|R|R
VFPCLASSSS ; rKq{K},Wss,Ib ; ; evex m:3 p:1 l:i w:0 0x67 /r ib ; s:AVX512DQ, t:AVX512, l:t1s, e:E6, w:W|R|R|R
VFPCLASSSD ; rKq{K},Wsd,Ib ; ; evex m:3 p:1 l:i w:1 0x67 /r ib ; s:AVX512DQ, t:AVX512, l:t1s, e:E6, w:W|R|R|R
@ -124,6 +136,7 @@ VPSHRDQ ; Vfv{K}{z},Hfv,Wfv|B64,Ib ; ; evex m:3 p:1 l:x w:1
# 0xC0 - 0xCF
VCMPPH ; rK{K},Hfv,Wfv|B16{sae},Ib ; ; evex m:3 p:0 l:x w:0 0xC2 /r ib ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R|R
VCMPSH ; rK{K},Hfv,Wsh{sae},Ib ; ; evex m:3 p:2 l:i w:0 0xC2 /r ib ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R|R
VCMPPBF16 ; rK{K},Hfv,Wfv|B16,Ib ; ; evex m:3 p:3 l:x w:0 0xC2 /r ib ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:W|R|R|R|R
VGF2P8AFFINEQB ; Vfv{K}{z},Hfv,Wfv|B64,Ib ; ; evex m:3 p:1 l:x w:1 0xCE /r ib ; s:GFNI, t:GFNI, l:fv, e:E4NF, w:W|R|R|R|R
VGF2P8AFFINEINVQB ; Vfv{K}{z},Hfv,Wfv|B64,Ib ; ; evex m:3 p:1 l:x w:1 0xCF /r ib ; s:GFNI, t:GFNI, l:fv, e:E4NF, w:W|R|R|R|R

38
isagenerator/instructions/table_evex_4.dat
View File

@ -776,27 +776,27 @@ PUSH2 ; Bv,Rv ; Kv2 ; evex m:4 l:0 nd:1 nf:0 p:0 w:0
PUSH2P ; Bv,Rv ; Kv2 ; evex m:4 l:0 nd:1 nf:0 p:0 w:1 0xFF /6:reg ; s:APX_F, t:PUSH, w:R|R|W, v:legacy, e:APX_EVEX_PP2, a:D64
# AES instructions.
ENCODEKEY128 ; Gd,Rd ; XMM0,XMM0-2,XMM4-6,Fv ; evex m:4 l:0 p:2 nd:0 nf:0 0xDA /r:reg ; s:APX_F, t:AESKL, w:W|R|R|W|W|W, f:ZERO, e:APX_EVEX_KEYLOCKER, v:legacy
ENCODEKEY256 ; Gd,Rd ; XMM0-1,XMM2-6,Fv ; evex m:4 l:0 p:2 nd:0 nf:0 0xDB /r:reg ; s:APX_F, t:AESKL, w:W|R|RW|W|W, f:ZERO, e:APX_EVEX_KEYLOCKER, v:legacy
AESDEC128KL ; Vdq,M384 ; Fv ; evex m:4 l:0 p:2 nd:0 nf:0 0xDD /r:mem ; s:APX_F, t:AESKL, w:RW|R|W, f:AESKL, e:APX_EVEX_KEYLOCKER, v:legacy
AESDEC256KL ; Vdq,M512 ; Fv ; evex m:4 l:0 p:2 nd:0 nf:0 0xDF /r:mem ; s:APX_F, t:AESKL, w:RW|R|W, f:AESKL, e:APX_EVEX_KEYLOCKER, v:legacy
AESENCWIDE128KL ; M384 ; XMM0-7,Fv ; evex m:4 l:0 p:2 nd:0 nf:0 0xD8 /0:mem ; s:APX_F, t:WIDE_KL, w:R|RW|W, f:AESKL, e:APX_EVEX_KEYLOCKER, v:legacy
AESDECWIDE128KL ; M384 ; XMM0-7,Fv ; evex m:4 l:0 p:2 nd:0 nf:0 0xD8 /1:mem ; s:APX_F, t:WIDE_KL, w:R|RW|W, f:AESKL, e:APX_EVEX_KEYLOCKER, v:legacy
AESENCWIDE256KL ; M512 ; XMM0-7,Fv ; evex m:4 l:0 p:2 nd:0 nf:0 0xD8 /2:mem ; s:APX_F, t:WIDE_KL, w:R|RW|W, f:AESKL, e:APX_EVEX_KEYLOCKER, v:legacy
AESDECWIDE256KL ; M512 ; XMM0-7,Fv ; evex m:4 l:0 p:2 nd:0 nf:0 0xD8 /3:mem ; s:APX_F, t:WIDE_KL, w:R|RW|W, f:AESKL, e:APX_EVEX_KEYLOCKER, v:legacy
AESENC128KL ; Vdq,M384 ; Fv ; evex m:4 l:0 p:2 nd:0 nf:0 0xDC /r:mem ; s:APX_F, t:AESKL, w:RW|R|W, f:AESKL, e:APX_EVEX_KEYLOCKER, v:legacy
AESENC256KL ; Vdq,M512 ; Fv ; evex m:4 l:0 p:2 nd:0 nf:0 0xDE /r:mem ; s:APX_F, t:AESKL, w:RW|R|W, f:AESKL, e:APX_EVEX_KEYLOCKER, v:legacy
# AES instructions. Were included in initial APX revisions, later removed in revision 4.0.
#ENCODEKEY128 ; Gd,Rd ; XMM0,XMM0-2,XMM4-6,Fv ; evex m:4 l:0 p:2 nd:0 nf:0 0xDA /r:reg ; s:APX_F, t:AESKL, w:W|R|R|W|W|W, f:ZERO, e:APX_EVEX_KEYLOCKER, v:legacy
#ENCODEKEY256 ; Gd,Rd ; XMM0-1,XMM2-6,Fv ; evex m:4 l:0 p:2 nd:0 nf:0 0xDB /r:reg ; s:APX_F, t:AESKL, w:W|R|RW|W|W, f:ZERO, e:APX_EVEX_KEYLOCKER, v:legacy
#AESDEC128KL ; Vdq,M384 ; Fv ; evex m:4 l:0 p:2 nd:0 nf:0 0xDD /r:mem ; s:APX_F, t:AESKL, w:RW|R|W, f:AESKL, e:APX_EVEX_KEYLOCKER, v:legacy
#AESDEC256KL ; Vdq,M512 ; Fv ; evex m:4 l:0 p:2 nd:0 nf:0 0xDF /r:mem ; s:APX_F, t:AESKL, w:RW|R|W, f:AESKL, e:APX_EVEX_KEYLOCKER, v:legacy
#AESENCWIDE128KL ; M384 ; XMM0-7,Fv ; evex m:4 l:0 p:2 nd:0 nf:0 0xD8 /0:mem ; s:APX_F, t:WIDE_KL, w:R|RW|W, f:AESKL, e:APX_EVEX_KEYLOCKER, v:legacy
#AESDECWIDE128KL ; M384 ; XMM0-7,Fv ; evex m:4 l:0 p:2 nd:0 nf:0 0xD8 /1:mem ; s:APX_F, t:WIDE_KL, w:R|RW|W, f:AESKL, e:APX_EVEX_KEYLOCKER, v:legacy
#AESENCWIDE256KL ; M512 ; XMM0-7,Fv ; evex m:4 l:0 p:2 nd:0 nf:0 0xD8 /2:mem ; s:APX_F, t:WIDE_KL, w:R|RW|W, f:AESKL, e:APX_EVEX_KEYLOCKER, v:legacy
#AESDECWIDE256KL ; M512 ; XMM0-7,Fv ; evex m:4 l:0 p:2 nd:0 nf:0 0xD8 /3:mem ; s:APX_F, t:WIDE_KL, w:R|RW|W, f:AESKL, e:APX_EVEX_KEYLOCKER, v:legacy
#AESENC128KL ; Vdq,M384 ; Fv ; evex m:4 l:0 p:2 nd:0 nf:0 0xDC /r:mem ; s:APX_F, t:AESKL, w:RW|R|W, f:AESKL, e:APX_EVEX_KEYLOCKER, v:legacy
#AESENC256KL ; Vdq,M512 ; Fv ; evex m:4 l:0 p:2 nd:0 nf:0 0xDE /r:mem ; s:APX_F, t:AESKL, w:RW|R|W, f:AESKL, e:APX_EVEX_KEYLOCKER, v:legacy
# SHA instructions.
SHA1RNDS4 ; Vdq,Wdq,Ib ; ; evex m:4 l:0 p:0 nd:0 nf:0 0xD4 /r ib ; s:APX_F, t:SHA, w:RW|R|R, e:APX_EVEX_SHA, v:legacy
SHA1NEXTE ; Vdq,Wdq ; ; evex m:4 l:0 p:0 nd:0 nf:0 0xD8 /r ; s:APX_F, t:SHA, w:RW|R, e:APX_EVEX_SHA, v:legacy
SHA1MSG1 ; Vdq,Wdq ; ; evex m:4 l:0 p:0 nd:0 nf:0 0xD9 /r ; s:APX_F, t:SHA, w:RW|R, e:APX_EVEX_SHA, v:legacy
SHA1MSG2 ; Vdq,Wdq ; ; evex m:4 l:0 p:0 nd:0 nf:0 0xDA /r ; s:APX_F, t:SHA, w:RW|R, e:APX_EVEX_SHA, v:legacy
SHA256MSG1 ; Vdq,Wdq ; ; evex m:4 l:0 p:0 nd:0 nf:0 0xDC /r ; s:APX_F, t:SHA, w:RW|R, e:APX_EVEX_SHA, v:legacy
SHA256MSG2 ; Vdq,Wdq ; ; evex m:4 l:0 p:0 nd:0 nf:0 0xDD /r ; s:APX_F, t:SHA, w:RW|R, e:APX_EVEX_SHA, v:legacy
SHA256RNDS2 ; Vdq,Wdq ; XMM0 ; evex m:4 l:0 p:0 nd:0 nf:0 0xDB /r ; s:APX_F, t:SHA, w:RW|R|R, e:APX_EVEX_SHA, v:legacy
# SHA instructions. Were included in initial APX revisions, later removed in revision 4.0.
#SHA1RNDS4 ; Vdq,Wdq,Ib ; ; evex m:4 l:0 p:0 nd:0 nf:0 0xD4 /r ib ; s:APX_F, t:SHA, w:RW|R|R, e:APX_EVEX_SHA, v:legacy
#SHA1NEXTE ; Vdq,Wdq ; ; evex m:4 l:0 p:0 nd:0 nf:0 0xD8 /r ; s:APX_F, t:SHA, w:RW|R, e:APX_EVEX_SHA, v:legacy
#SHA1MSG1 ; Vdq,Wdq ; ; evex m:4 l:0 p:0 nd:0 nf:0 0xD9 /r ; s:APX_F, t:SHA, w:RW|R, e:APX_EVEX_SHA, v:legacy
#SHA1MSG2 ; Vdq,Wdq ; ; evex m:4 l:0 p:0 nd:0 nf:0 0xDA /r ; s:APX_F, t:SHA, w:RW|R, e:APX_EVEX_SHA, v:legacy
#SHA256MSG1 ; Vdq,Wdq ; ; evex m:4 l:0 p:0 nd:0 nf:0 0xDC /r ; s:APX_F, t:SHA, w:RW|R, e:APX_EVEX_SHA, v:legacy
#SHA256MSG2 ; Vdq,Wdq ; ; evex m:4 l:0 p:0 nd:0 nf:0 0xDD /r ; s:APX_F, t:SHA, w:RW|R, e:APX_EVEX_SHA, v:legacy
#SHA256RNDS2 ; Vdq,Wdq ; XMM0 ; evex m:4 l:0 p:0 nd:0 nf:0 0xDB /r ; s:APX_F, t:SHA, w:RW|R|R, e:APX_EVEX_SHA, v:legacy
# INVEPT, INVPCID, INVVPID

50
isagenerator/instructions/table_evex_5.dat
View File

@ -8,22 +8,38 @@ VMOVSH ; Vdq{K}{z},Wsh ; ; evex m:5 p:2 l:i w:0
VMOVSH ; Vdq{K}{z},Hdq,Wsh ; ; evex m:5 p:2 l:i w:0 0x10 /r:reg ; s:AVX512FP16, t:AVX512FP16, e:E5, w:W|R|R|R
VMOVSH ; Wsh{K},Vdq ; ; evex m:5 p:2 l:i w:0 0x11 /r:mem ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E5, w:W|R|R
VMOVSH ; Wsh{K}{z},Hdq,Vdq ; ; evex m:5 p:2 l:i w:0 0x11 /r:reg ; s:AVX512FP16, t:AVX512FP16, e:E5, w:W|R|R|R
VCVTBIASPH2HF8 ; Vhv{K}{z},Hfv,Wfv|B16 ; ; evex m:5 p:0 l:x w:0 0x18 /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R|R
VCVTNEPH2HF8 ; Vhv{K}{z},Wfv|B16 ; ; evex m:5 p:2 l:x w:0 0x18 /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R
VCVTNE2PH2HF8 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:5 p:3 l:x w:0 0x18 /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R|R
VCVTBIASPH2HF8S ; Vhv{K}{z},Hfv,Wfv|B16 ; ; evex m:5 p:0 l:x w:0 0x1B /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R|R
VCVTNEPH2HF8S ; Vhv{K}{z},Wfv|B16 ; ; evex m:5 p:2 l:x w:0 0x1B /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R
VCVTNE2PH2HF8S ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:5 p:3 l:x w:0 0x1B /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R|R
VCVTPS2PHX ; Vhv{K}{z},Wfv|B32{er} ; ; evex m:5 p:1 l:x w:0 0x1D /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R
VCVTSS2SH ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:5 p:0 l:i w:0 0x1D /r ; s:AVX512FP16, t:AVX512FP16, l:t1s, e:E3, w:W|R|R|R
VCVTHF82PH ; Vfv{K}{z},Whv ; ; evex m:5 p:3 l:x w:0 0x1E /r ; s:AVX102, t:AVX10CONVERT, l:hv, e:E2, w:W|R|R
# 0x20 - 0x2F
VCVTSI2SH ; Vdq,Hdq,Ey ; ; evex m:5 p:2 l:i w:x 0x2A /r ; s:AVX512FP16, t:AVX512FP16, l:t1s, e:E3NF, w:W|R|R, a:IWO64
VCVTTSH2SI ; Gy,Wsh{sae} ; ; evex m:5 p:2 l:i w:x 0x2C /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3NF, w:W|R, a:IWO64
VCVTSH2SI ; Gy,Wsh{er} ; ; evex m:5 p:2 l:i w:x 0x2D /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3NF, w:W|R, a:IWO64
VUCOMISH ; Vdq,Wsh{sae} ; Fv ; evex m:5 p:0 l:i w:0 0x2E /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3NF, w:R|R|W, f:ZF=m|PF=m|CF=m|OF=0|SF=0|AF=0
VUCOMXSH ; Vdq,Wsh{sae} ; Fv ; evex m:5 p:3 l:0 w:0 0x2E /r ; s:AVX102, t:AVX10CMPSFP,l:t1s16, e:E3NF, w:R|R|W, f:CMPSFP
VCOMISH ; Vdq,Wsh{sae} ; Fv ; evex m:5 p:0 l:i w:0 0x2F /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3NF, w:R|R|W, f:ZF=m|PF=m|CF=m|OF=0|SF=0|AF=0
VCOMSBF16 ; Vdq,Wsh ; Fv ; evex m:5 p:1 l:i w:0 0x2F /r ; s:AVX102, t:AVX10BF16, l:t1s16, e:E10NF, w:R|R|W, f:ZF=m|PF=m|CF=m|OF=0|SF=0|AF=0
VCOMXSH ; Vdq,Wsh{sae} ; Fv ; evex m:5 p:3 l:0 w:0 0x2F /r ; s:AVX102, t:AVX10CMPSFP,l:t1s16, e:E3NF, w:R|R|W, f:CMPSFP
# 0x40 - 0x4F
VGETEXPPBF16 ; Vfv{K}{z},Wfv|B16 ; ; evex m:5 p:1 l:x w:0 0x42 /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:W|R|R
# 0x50 - 0x5F
VSQRTPH ; Vfv{K}{z},Wfv|B16{er} ; ; evex m:5 p:0 l:x w:0 0x51 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R
VSQRTNEPBF16 ; Vfv{K}{z},Wfv|B16 ; ; evex m:5 p:1 l:x w:0 0x51 /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:W|R|R
VSQRTSH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:5 p:2 l:i w:0 0x51 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R
VADDPH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:5 p:0 l:x w:0 0x58 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R
VADDNEPBF16 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:5 p:1 l:x w:0 0x58 /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:W|R|R|R
VADDSH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:5 p:2 l:i w:0 0x58 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R
VMULPH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:5 p:0 l:x w:0 0x59 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R
VMULNEPBF16 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:5 p:1 l:x w:0 0x59 /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:W|R|R|R
VMULSH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:5 p:2 l:i w:0 0x59 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R
VCVTPH2PD ; Vfv{K}{z},Wqv|B16{sae} ; ; evex m:5 p:0 l:x w:0 0x5A /r ; s:AVX512FP16, t:AVX512FP16, l:qv, e:E2, w:W|R|R
VCVTPD2PH ; Vdq{K}{z},Wfv|B64{er} ; ; evex m:5 p:1 l:x w:1 0x5A /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R
@ -34,19 +50,52 @@ VCVTQQ2PH ; Vdq{K}{z},Wfv|B64{er} ; ; evex m:5 p:0 l:x w:1
VCVTPH2DQ ; Vfv{K}{z},Whv|B16{er} ; ; evex m:5 p:1 l:x w:0 0x5B /r ; s:AVX512FP16, t:AVX512FP16, l:hv, e:E2, w:W|R|R
VCVTTPH2DQ ; Vfv{K}{z},Whv|B16{sae} ; ; evex m:5 p:2 l:x w:0 0x5B /r ; s:AVX512FP16, t:AVX512FP16, l:hv, e:E2, w:W|R|R
VSUBPH ; Vfv{K}{z},Hfv,Wfv|B16{sae} ; ; evex m:5 p:0 l:x w:0 0x5C /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R
VSUBNEPBF16 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:5 p:1 l:x w:0 0x5C /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:W|R|R|R
VSUBSH ; Vdq{K}{z},Hdq,Wsh{sae} ; ; evex m:5 p:2 l:i w:0 0x5C /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R
VMINPH ; Vfv{K}{z},Hfv,Wfv|B16{sae} ; ; evex m:5 p:0 l:x w:0 0x5D /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R
VMINPBF16 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:5 p:1 l:x w:0 0x5D /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:W|R|R|R
VMINSH ; Vdq{K}{z},Hdq,Wsh{sae} ; ; evex m:5 p:2 l:i w:0 0x5D /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R
VDIVPH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:5 p:0 l:x w:0 0x5E /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R
VDIVNEPBF16 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:5 p:1 l:x w:0 0x5E /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:W|R|R|R
VDIVSH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:5 p:2 l:i w:0 0x5E /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R
VMAXPH ; Vfv{K}{z},Hfv,Wfv|B16{sae} ; ; evex m:5 p:0 l:x w:0 0x5F /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R
VMAXPBF16 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:5 p:1 l:x w:0 0x5F /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:W|R|R|R
VMAXSH ; Vdq{K}{z},Hdq,Wsh{sae} ; ; evex m:5 p:2 l:i w:0 0x5F /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R
# 0x60 - 0x6F
VCVTTPH2IBS ; Vfv{K}{z},Wfv|B16{sae} ; ; evex m:5 p:0 l:x w:0 0x68 /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R
VCVTTPS2IBS ; Vfv{K}{z},Wfv|B32{sae} ; ; evex m:5 p:1 l:x w:0 0x68 /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R
VCVTTNEBF162IBS ; Vfv{K}{z},Wfv|B16 ; ; evex m:5 p:3 l:x w:0 0x68 /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E4, w:W|R|R
VCVTPH2IBS ; Vfv{K}{z},Wfv|B16{er} ; ; evex m:5 p:0 l:x w:0 0x69 /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R
VCVTPS2IBS ; Vfv{K}{z},Wfv|B32{er} ; ; evex m:5 p:1 l:x w:0 0x69 /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R
VCVTNEBF162IBS ; Vfv{K}{z},Wfv|B16 ; ; evex m:5 p:3 l:x w:0 0x69 /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E4, w:W|R|R
VCVTTPH2IUBS ; Vfv{K}{z},Wfv|B16{sae} ; ; evex m:5 p:0 l:x w:0 0x6A /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R
VCVTTPS2IUBS ; Vfv{K}{z},Wfv|B32{sae} ; ; evex m:5 p:1 l:x w:0 0x6A /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R
VCVTTNEBF162IUBS ; Vfv{K}{z},Wfv|B16 ; ; evex m:5 p:3 l:x w:0 0x6A /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E4, w:W|R|R
VCVTPH2IUBS ; Vfv{K}{z},Wfv|B16{er} ; ; evex m:5 p:0 l:x w:0 0x6B /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R
VCVTPS2IUBS ; Vfv{K}{z},Wfv|B32{er} ; ; evex m:5 p:1 l:x w:0 0x6B /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R
VCVTNEBF162IUBS ; Vfv{K}{z},Wfv|B16 ; ; evex m:5 p:3 l:x w:0 0x6B /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E4, w:W|R|R
VCVTTPS2UDQS ; Vfv{K}{z},Wfv|B32{sae} ; ; evex m:5 p:0 l:x w:0 0x6C /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R
VCVTTPD2UDQS ; Vhv{K}{z},Wfv|B64{sae} ; ; evex m:5 p:0 l:x w:1 0x6C /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R
VCVTTPS2UQQS ; Vfv{K}{z},Whv|B32{sae} ; ; evex m:5 p:1 l:x w:0 0x6C /r ; s:AVX102, t:AVX10SCONVERT, l:hv, e:E2, w:W|R|R
VCVTTPD2UQQS ; Vfv{K}{z},Wfv|B64{sae} ; ; evex m:5 p:1 l:x w:1 0x6C /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R
VCVTTSS2USIS ; Gy,Wss{sae} ; ; evex m:5 p:2 l:i w:x 0x6C /r ; s:AVX102, t:AVX10SCONVERT, l:t1s, e:E3NF, w:W|R, a:IWO64
VCVTTSD2USIS ; Gy,Wsd{sae} ; ; evex m:5 p:3 l:i w:x 0x6C /r ; s:AVX102, t:AVX10SCONVERT, l:t1s, e:E3NF, w:W|R, a:IWO64
VCVTTPS2DQS ; Vfv{K}{z},Wfv|B32{sae} ; ; evex m:5 p:0 l:x w:0 0x6D /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R
VCVTTPD2DQS ; Vhv{K}{z},Wfv|B64{sae} ; ; evex m:5 p:0 l:x w:1 0x6D /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R
VCVTTPS2QQS ; Vfv{K}{z},Whv|B32{sae} ; ; evex m:5 p:1 l:x w:0 0x6D /r ; s:AVX102, t:AVX10SCONVERT, l:hv, e:E2, w:W|R|R
VCVTTPD2QQS ; Vfv{K}{z},Wfv|B64{sae} ; ; evex m:5 p:1 l:x w:1 0x6D /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R
VCVTTSS2SIS ; Gy,Wss{sae} ; ; evex m:5 p:2 l:i w:x 0x6D /r ; s:AVX102, t:AVX10SCONVERT, l:t1s, e:E3NF, w:W|R, a:IWO64
VCVTTSD2SIS ; Gy,Wsd{sae} ; ; evex m:5 p:3 l:i w:x 0x6D /r ; s:AVX102, t:AVX10SCONVERT, l:t1s, e:E3NF, w:W|R, a:IWO64
VMOVW ; Vdq,Mw ; ; evex m:5 p:1 l:0 w:i 0x6E /r:mem ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E9NF, w:W|R
VMOVW ; Vdq,Rd ; ; evex m:5 p:1 l:0 w:i 0x6E /r:reg ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E9NF, w:W|R
VMOVW ; Vdq,Ww ; ; evex m:5 p:2 l:0 w:0 0x6E /r ; s:AVX102, t:AVX10PARTCOPY, l:t1s16, e:E9NF, w:W|R
# 0x70 - 0x7F
VCVTBIASPH2BF8S ; Vhv{K}{z},Hfv,Wfv|B16 ; ; evex m:5 p:0 l:x w:0 0x74 /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R|R
VCVTNEPH2BF8S ; Vhv{K}{z},Wfv|B16 ; ; evex m:5 p:2 l:x w:0 0x74 /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R
VCVTNE2PH2BF8S ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:5 p:3 l:x w:0 0x74 /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R|R
VCVTTPH2UDQ ; Vfv{K}{z},Whv|B16{sae} ; ; evex m:5 p:0 l:x w:0 0x78 /r ; s:AVX512FP16, t:AVX512FP16, l:hv, e:E2, w:W|R|R
VCVTTPH2UQQ ; Vfv{K}{z},Wqv|B16{sae} ; ; evex m:5 p:1 l:x w:0 0x78 /r ; s:AVX512FP16, t:AVX512FP16, l:qv, e:E2, w:W|R|R
VCVTTSH2USI ; Gy,Wsh{sae} ; ; evex m:5 p:2 l:i w:0 0x78 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3NF, w:W|R, a:IWO64
@ -66,3 +115,4 @@ VCVTW2PH ; Vfv{K}{z},Wfv|B16{er} ; ; evex m:5 p:2 l:x w:0
VCVTUW2PH ; Vfv{K}{z},Wfv|B16{er} ; ; evex m:5 p:3 l:x w:0 0x7D /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R
VMOVW ; Mw,Vdq ; ; evex m:5 p:1 l:0 w:i 0x7E /r:mem ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E9NF, w:W|R
VMOVW ; Rd,Vdq ; ; evex m:5 p:1 l:0 w:i 0x7E /r:reg ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E9NF, w:W|R
VMOVW ; Ww,Vdq ; ; evex m:5 p:2 l:0 w:0 0x7E /r ; s:AVX102, t:AVX10PARTCOPY, l:t1s16, e:E9NF, w:W|R

15
isagenerator/instructions/table_evex_6.dat
View File

@ -8,14 +8,17 @@ VCVTSH2SS ; Vdq{K}{z},Hdq,Wsh{sae} ; ; evex m:6 p:0 l:i w:0
VCVTPH2PSX ; Vfv{K}{z},Whv|B16{sae} ; ; evex m:6 p:1 l:x w:0 0x13 /r ; s:AVX512FP16, t:AVX512FP16, l:hv, e:E2, w:W|R|R
# 0x20 - 0x2F
VSCALEFPBF16 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:6 p:0 l:x w:0 0x2C /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:W|R|R|R
VSCALEFPH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0x2C /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R
VSCALEFSH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0x2D /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R
# 0x40 - 0x4F
VGETEXPPH ; Vfv{K}{z},Wfv|B16{sae} ; ; evex m:6 p:1 l:x w:0 0x42 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R
VGETEXPSH ; Vdq{K}{z},Hdq,Wsh{sae} ; ; evex m:6 p:1 l:i w:0 0x43 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R
VRCPPBF16 ; Vfv{K}{z},Wfv|B16 ; ; evex m:6 p:0 l:x w:0 0x4C /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:W|R|R
VRCPPH ; Vfv{K}{z},Wfv|B16 ; ; evex m:6 p:1 l:x w:0 0x4C /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E4, w:W|R|R
VRCPSH ; Vdq{K}{z},Hdq,Wsh ; ; evex m:6 p:1 l:i w:0 0x4D /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E10, w:W|R|R|R
VRSQRTPBF16 ; Vfv{K}{z},Wfv|B16 ; ; evex m:6 p:0 l:x w:0 0x4E /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:W|R|R
VRSQRTPH ; Vfv{K}{z},Wfv|B16 ; ; evex m:6 p:1 l:x w:0 0x4E /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E4, w:W|R|R
VRSQRTSH ; Vdq{K}{z},Hdq,Wsh ; ; evex m:6 p:1 l:i w:0 0x4F /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E10, w:W|R|R|R
@ -28,36 +31,48 @@ VFCMADDCSH ; Vdq{K}{z},Hdq,Wd{er} ; ; evex m:6 p:3 l:i w:0
# 0x90 - 0x9F
VFMADDSUB132PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0x96 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
VFMSUBADD132PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0x97 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
VFMADD132NEPBF16 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:6 p:0 l:x w:0 0x98 /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:RW|R|R|R
VFMADD132PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0x98 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
VFMADD132SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0x99 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R
VFMSUB132NEPBF16 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:6 p:0 l:x w:0 0x9A /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:RW|R|R|R
VFMSUB132PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0x9A /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
VFMSUB132SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0x9B /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R
VFNMADD132NEPBF16 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:6 p:0 l:x w:0 0x9C /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:RW|R|R|R
VFNMADD132PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0x9C /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
VFNMADD132SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0x9D /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R
VFNMSUB132NEPBF16 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:6 p:0 l:x w:0 0x9E /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:RW|R|R|R
VFNMSUB132PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0x9E /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
VFNMSUB132SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0x9F /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R
# 0xA0 - 0xAF
VFMADDSUB213PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xA6 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
VFMSUBADD213PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xA7 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
VFMADD213NEPBF16 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:6 p:0 l:x w:0 0xA8 /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:RW|R|R|R
VFMADD213PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xA8 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
VFMADD213SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0xA9 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R
VFMSUB213NEPBF16 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:6 p:0 l:x w:0 0xAA /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:RW|R|R|R
VFMSUB213PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xAA /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
VFMSUB213SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0xAB /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R
VFNMADD213NEPBF16 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:6 p:0 l:x w:0 0xAC /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:RW|R|R|R
VFNMADD213PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xAC /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
VFNMADD213SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0xAD /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R
VFNMSUB213NEPBF16 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:6 p:0 l:x w:0 0xAE /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:RW|R|R|R
VFNMSUB213PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xAE /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
VFNMSUB213SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0xAF /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R
# 0xB0 - 0xBF
VFMADDSUB231PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xB6 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
VFMSUBADD231PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xB7 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
VFMADD231NEPBF16 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:6 p:0 l:x w:0 0xB8 /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:RW|R|R|R
VFMADD231PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xB8 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
VFMADD231SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0xB9 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R
VFMSUB231NEPBF16 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:6 p:0 l:x w:0 0xBA /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:RW|R|R|R
VFMSUB231PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xBA /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
VFMSUB231SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0xBB /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R
VFNMADD231NEPBF16 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:6 p:0 l:x w:0 0xBC /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:RW|R|R|R
VFNMADD231PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xBC /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
VFNMADD231SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0xBD /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R
VFNMSUB231NEPBF16 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:6 p:0 l:x w:0 0xBE /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:RW|R|R|R
VFNMSUB231PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xBE /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
VFNMSUB231SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0xBF /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R

4
isagenerator/instructions/table_legacy_0.dat
View File

@ -343,8 +343,8 @@ MOV ; Eb,Ib ; ; 0xC6 /0 ib ; s:I
XABORT ; Ib ; yIP,EAX ; 0xC6 /0xF8 ib ; s:TSX, t:UNCOND_BR, w:R|W|RCW, i:RTM
MOV ; Ev,Iz ; ; 0xC7 /0 iz ; s:I86, t:DATAXFER, w:W|R, a:OP2SIGNEXO1, p:XRELEASE|HLEWOL
XBEGIN ; Jz ; yIP,EAX ; 0xC7 /0xF8 cz ; s:TSX, t:COND_BR, w:R|RCW|CW, i:RTM
ENTER ; Iw,Ib ; rBP,sSP,Kv ; 0xC8 iw ib ; s:I186, t:MISC, w:R|R|RW|RW|W, a:D64
LEAVE ; ; sBP,rBP,rSP,Kv ; 0xC9 ; s:I186, t:MISC, w:R|RW|RW|R, a:D64
ENTER ; Iw,Ib ; rBP,rSP,Kv,sBP,pBP; 0xC8 iw ib ; s:I186, t:MISC, w:R|R|RW|RW|W|RW|R, a:D64
LEAVE ; ; sBP,rBP,sSP,Kv ; 0xC9 ; s:I186, t:MISC, w:R|RW|RW|R, a:D64
RETF ; Iw ; CS,rIP,Kv2,SHS2 ; 0xCA iw ; s:I86, t:RET, w:R|W|W|R|R
RETF ; ; CS,rIP,Kv2,SHS2 ; 0xCB ; s:I86, t:RET, w:W|W|R|R
INT3 ; ; CS,rIP,Kv3,Fv,SHS3 ; 0xCC ; s:I86, t:INTERRUPT, w:RW|RW|RW|W|W, a:CETT, f:INT, m:NOSGX

1
isagenerator/instructions/table_legacy_1.dat
View File

@ -81,6 +81,7 @@ MWAITX ; ; EAX,ECX,EBX ; NP 0x0F 0x01 /0xF
CLZERO ; ; rAX ; 0x0F 0x01 /0xFC ; s:CLZERO, t:MISC, w:R
RDPRU ; ; EAX,EDX,ECX,Fv ; NP 0x0F 0x01 /0xFD ; s:RDPRU, t:MISC, w:W|W|R|W, f:CF=m|PF=0|AF=0|ZF=0|SF=0|OF=0
RMPQUERY ; ; pAXb,EAX,RCX,RDX,Fv ; 0xF3 0x0F 0x01 /0xFD ; s:SNP, t:SYSTEM, w:R|RW|W|RW|W, f:OF=m|ZF=m|AF=m|PF=m|SF=m, a:I67, m:O64|KERNEL, i:RMPQUERY
RMPREAD ; ; RAX,pCXdq,Fv ; 0xF2 0x0F 0x01 /0xFD ; s:SNP, t:SYSTEM, w:RW|W|W, f:OF=m|ZF=m|AF=m|PF=m|SF=m, a:I67, m:O64|KERNEL, i:RMPREAD
INVLPGB ; ; rAX,ECX,EDX ; NP 0x0F 0x01 /0xFE ; s:INVLPGB, t:SYSTEM, w:R|R|R, m:NOREAL|KERNEL
RMPADJUST ; ; pAXb,EAX,RCX,RDX,Fv ; 0xF3 0x0F 0x01 /0xFE ; s:SNP, t:SYSTEM, w:R|RW|R|R|W, f:OF=m|ZF=m|AF=m|PF=m|SF=m, a:I67, m:O64|KERNEL
RMPUPDATE ; ; RAX,pCXdq,Fv ; 0xF2 0x0F 0x01 /0xFE ; s:SNP, t:SYSTEM, w:RW|R|W, f:OF=m|ZF=m|AF=m|PF=m|SF=m, a:I67, m:O64|KERNEL