mirror of
https://github.com/bitdefender/bddisasm.git
synced 2024-12-22 05:58:07 +00:00
Added support for Intel AMX-COMPLEX instructions.
This commit is contained in:
parent
ee6cdd6cb6
commit
124521beb5
File diff suppressed because it is too large
Load Diff
@ -10,7 +10,7 @@
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#ifndef MNEMONICS_H
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#define MNEMONICS_H
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const char *gMnemonics[1734] =
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const char *gMnemonics[1736] =
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{
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"AAA", "AAD", "AADD", "AAM", "AAND", "AAS", "ADC", "ADCX", "ADD",
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"ADDPD", "ADDPS", "ADDSD", "ADDSS", "ADDSUBPD", "ADDSUBPS", "ADOX",
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@ -133,12 +133,12 @@ const char *gMnemonics[1734] =
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"STC", "STD", "STGI", "STI", "STMXCSR", "STOSB", "STOSD", "STOSQ",
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"STOSW", "STR", "STTILECFG", "STUI", "SUB", "SUBPD", "SUBPS",
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"SUBSD", "SUBSS", "SVDC", "SVLDT", "SVTS", "SWAPGS", "SYSCALL",
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"SYSENTER", "SYSEXIT", "SYSRET", "T1MSKC", "TDCALL", "TDPBF16PS",
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"TDPBSSD", "TDPBSUD", "TDPBUSD", "TDPBUUD", "TDPFP16PS", "TEST",
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"TESTUI", "TILELOADD", "TILELOADDT1", "TILERELEASE", "TILESTORED",
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"TILEZERO", "TLBSYNC", "TPAUSE", "TZCNT", "TZMSK", "UCOMISD",
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"UCOMISS", "UD0", "UD1", "UD2", "UIRET", "UMONITOR", "UMWAIT",
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"UNPCKHPD", "UNPCKHPS", "UNPCKLPD", "UNPCKLPS", "V4FMADDPS",
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"SYSENTER", "SYSEXIT", "SYSRET", "T1MSKC", "TCMMIMFP16PS", "TCMMRLFP16PS",
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"TDCALL", "TDPBF16PS", "TDPBSSD", "TDPBSUD", "TDPBUSD", "TDPBUUD",
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"TDPFP16PS", "TEST", "TESTUI", "TILELOADD", "TILELOADDT1", "TILERELEASE",
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"TILESTORED", "TILEZERO", "TLBSYNC", "TPAUSE", "TZCNT", "TZMSK",
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"UCOMISD", "UCOMISS", "UD0", "UD1", "UD2", "UIRET", "UMONITOR",
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"UMWAIT", "UNPCKHPD", "UNPCKHPS", "UNPCKLPD", "UNPCKLPS", "V4FMADDPS",
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"V4FMADDSS", "V4FNMADDPS", "V4FNMADDSS", "VADDPD", "VADDPH",
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"VADDPS", "VADDSD", "VADDSH", "VADDSS", "VADDSUBPD", "VADDSUBPS",
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"VAESDEC", "VAESDECLAST", "VAESENC", "VAESENCLAST", "VAESIMC",
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File diff suppressed because it is too large
Load Diff
@ -81,13 +81,13 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f6_mem_F3_leaf =
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const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f6_mem_NP_None_leaf =
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{
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ND_ILUT_INSTRUCTION,
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(const void *)&gInstructions[2705]
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(const void *)&gInstructions[2707]
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};
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const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f6_mem_NP_rexw_leaf =
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{
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ND_ILUT_INSTRUCTION,
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(const void *)&gInstructions[2706]
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(const void *)&gInstructions[2708]
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};
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const ND_TABLE_AUXILIARY gRootTable_root_0f_38_f6_mem_NP_auxiliary =
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@ -1834,13 +1834,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_38_cb_mprefix =
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const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f5_mem_66_None_leaf =
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{
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ND_ILUT_INSTRUCTION,
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(const void *)&gInstructions[2707]
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(const void *)&gInstructions[2709]
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};
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const ND_TABLE_INSTRUCTION gRootTable_root_0f_38_f5_mem_66_rexw_leaf =
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{
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ND_ILUT_INSTRUCTION,
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(const void *)&gInstructions[2708]
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(const void *)&gInstructions[2710]
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};
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const ND_TABLE_AUXILIARY gRootTable_root_0f_38_f5_mem_66_auxiliary =
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@ -3437,7 +3437,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_bc_None_leaf =
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const ND_TABLE_INSTRUCTION gRootTable_root_0f_bc_aF3_leaf =
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{
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ND_ILUT_INSTRUCTION,
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(const void *)&gInstructions[1383]
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(const void *)&gInstructions[1385]
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};
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const ND_TABLE_AUXILIARY gRootTable_root_0f_bc_auxiliary =
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@ -3733,7 +3733,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_03_mprefix =
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const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_01_04_66_leaf =
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{
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ND_ILUT_INSTRUCTION,
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(const void *)&gInstructions[1360]
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(const void *)&gInstructions[1362]
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};
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const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_01_04_mprefix =
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@ -3789,25 +3789,25 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_04_leaf =
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const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_01_F3_leaf =
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{
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ND_ILUT_INSTRUCTION,
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(const void *)&gInstructions[1898]
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(const void *)&gInstructions[1900]
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};
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const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_01_F2_leaf =
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{
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ND_ILUT_INSTRUCTION,
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(const void *)&gInstructions[1899]
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(const void *)&gInstructions[1901]
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};
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const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_01_None_leaf =
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{
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ND_ILUT_INSTRUCTION,
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(const void *)&gInstructions[1912]
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(const void *)&gInstructions[1914]
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};
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const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_01_66_leaf =
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{
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ND_ILUT_INSTRUCTION,
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(const void *)&gInstructions[1913]
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(const void *)&gInstructions[1915]
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};
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const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_03_01_mprefix =
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@ -3824,19 +3824,19 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_03_01_mprefix =
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const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_02_leaf =
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{
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ND_ILUT_INSTRUCTION,
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(const void *)&gInstructions[1911]
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(const void *)&gInstructions[1913]
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};
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const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_00_leaf =
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{
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ND_ILUT_INSTRUCTION,
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(const void *)&gInstructions[2026]
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(const void *)&gInstructions[2028]
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};
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const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_03_03_leaf =
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{
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ND_ILUT_INSTRUCTION,
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(const void *)&gInstructions[2027]
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(const void *)&gInstructions[2029]
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};
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const ND_TABLE_MODRM_RM gRootTable_root_0f_01_reg_03_modrmrm =
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@ -3909,7 +3909,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_00_F3_leaf =
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const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_00_F2_leaf =
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{
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ND_ILUT_INSTRUCTION,
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(const void *)&gInstructions[2761]
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(const void *)&gInstructions[2763]
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};
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const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_00_mprefix =
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@ -3932,7 +3932,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_07_F3_leaf =
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const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_07_NP_leaf =
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{
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ND_ILUT_INSTRUCTION,
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(const void *)&gInstructions[2703]
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(const void *)&gInstructions[2705]
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};
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const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_07_mprefix =
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@ -3949,7 +3949,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_07_mprefix =
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const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_05_F3_leaf =
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{
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ND_ILUT_INSTRUCTION,
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(const void *)&gInstructions[1375]
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(const void *)&gInstructions[1377]
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};
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const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_05_mprefix =
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@ -3966,7 +3966,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_05_mprefix =
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const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_04_F3_leaf =
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{
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ND_ILUT_INSTRUCTION,
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(const void *)&gInstructions[1390]
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(const void *)&gInstructions[1392]
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};
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const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_04_mprefix =
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@ -3983,7 +3983,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_04_mprefix =
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const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_05_01_F2_leaf =
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{
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ND_ILUT_INSTRUCTION,
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(const void *)&gInstructions[2743]
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(const void *)&gInstructions[2745]
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};
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const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_05_01_mprefix =
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@ -4102,7 +4102,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_07_F2_leaf =
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const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_07_07_None_leaf =
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{
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ND_ILUT_INSTRUCTION,
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(const void *)&gInstructions[1381]
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(const void *)&gInstructions[1383]
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};
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const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_07_07_mprefix =
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@ -4186,7 +4186,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_07_mprefix =
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const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_02_04_NP_leaf =
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{
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ND_ILUT_INSTRUCTION,
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(const void *)&gInstructions[1897]
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(const void *)&gInstructions[1899]
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};
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const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_04_mprefix =
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@ -4203,7 +4203,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_04_mprefix =
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const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_02_05_NP_leaf =
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{
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ND_ILUT_INSTRUCTION,
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(const void *)&gInstructions[2728]
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(const void *)&gInstructions[2730]
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};
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const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_05_mprefix =
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@ -4220,7 +4220,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_05_mprefix =
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const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_02_00_NP_leaf =
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{
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ND_ILUT_INSTRUCTION,
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(const void *)&gInstructions[2729]
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(const void *)&gInstructions[2731]
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};
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const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_00_mprefix =
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@ -4237,7 +4237,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_00_mprefix =
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const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_02_01_NP_leaf =
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{
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ND_ILUT_INSTRUCTION,
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(const void *)&gInstructions[2756]
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(const void *)&gInstructions[2758]
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};
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const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_01_mprefix =
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@ -4254,7 +4254,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_01_mprefix =
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const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_02_06_NP_leaf =
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{
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ND_ILUT_INSTRUCTION,
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(const void *)&gInstructions[2762]
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(const void *)&gInstructions[2764]
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};
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const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_02_06_mprefix =
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@ -4326,13 +4326,13 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_06_F2_leaf =
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const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_06_F3_leaf =
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{
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ND_ILUT_INSTRUCTION,
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(const void *)&gInstructions[2701]
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(const void *)&gInstructions[2703]
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};
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const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_06_NP_leaf =
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{
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ND_ILUT_INSTRUCTION,
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(const void *)&gInstructions[2702]
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(const void *)&gInstructions[2704]
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};
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const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_06_mprefix =
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@ -4349,7 +4349,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_06_mprefix =
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const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_01_NP_leaf =
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{
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ND_ILUT_INSTRUCTION,
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(const void *)&gInstructions[1895]
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(const void *)&gInstructions[1897]
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};
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const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_01_mprefix =
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@ -4366,7 +4366,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_01_mprefix =
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const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_02_NP_leaf =
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{
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ND_ILUT_INSTRUCTION,
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(const void *)&gInstructions[1910]
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(const void *)&gInstructions[1912]
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};
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const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_02_mprefix =
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@ -4383,7 +4383,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_02_mprefix =
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const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_03_NP_leaf =
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{
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ND_ILUT_INSTRUCTION,
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(const void *)&gInstructions[2025]
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(const void *)&gInstructions[2027]
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};
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const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_03_mprefix =
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@ -4400,7 +4400,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_03_mprefix =
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const ND_TABLE_INSTRUCTION gRootTable_root_0f_01_reg_00_04_NP_leaf =
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{
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ND_ILUT_INSTRUCTION,
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(const void *)&gInstructions[2039]
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(const void *)&gInstructions[2041]
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};
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const ND_TABLE_MPREFIX gRootTable_root_0f_01_reg_00_04_mprefix =
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@ -4762,13 +4762,13 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_06_66_leaf =
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const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_06_NP_None_leaf =
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{
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ND_ILUT_INSTRUCTION,
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(const void *)&gInstructions[2752]
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(const void *)&gInstructions[2754]
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};
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const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_06_NP_rexw_leaf =
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{
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ND_ILUT_INSTRUCTION,
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(const void *)&gInstructions[2753]
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(const void *)&gInstructions[2755]
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};
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const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_mem_06_NP_auxiliary =
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@ -4899,13 +4899,13 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_04_F3_leaf =
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const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_04_NP_None_leaf =
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{
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ND_ILUT_INSTRUCTION,
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(const void *)&gInstructions[2748]
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(const void *)&gInstructions[2750]
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};
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const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_04_NP_rexw_leaf =
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{
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ND_ILUT_INSTRUCTION,
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(const void *)&gInstructions[2749]
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(const void *)&gInstructions[2751]
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};
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const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_mem_04_NP_auxiliary =
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@ -4954,13 +4954,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_mem_03_mprefix =
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const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_05_NP_None_leaf =
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{
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ND_ILUT_INSTRUCTION,
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(const void *)&gInstructions[2744]
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(const void *)&gInstructions[2746]
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};
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const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_mem_05_NP_rexw_leaf =
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{
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ND_ILUT_INSTRUCTION,
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(const void *)&gInstructions[2745]
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(const void *)&gInstructions[2747]
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};
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const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_mem_05_NP_auxiliary =
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@ -5057,19 +5057,19 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_06_NP_leaf =
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const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_06_66_leaf =
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{
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ND_ILUT_INSTRUCTION,
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(const void *)&gInstructions[1382]
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(const void *)&gInstructions[1384]
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};
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const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_06_F3_leaf =
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{
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ND_ILUT_INSTRUCTION,
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(const void *)&gInstructions[1391]
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(const void *)&gInstructions[1393]
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};
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const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_06_F2_leaf =
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{
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ND_ILUT_INSTRUCTION,
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(const void *)&gInstructions[1392]
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(const void *)&gInstructions[1394]
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};
|
||||
|
||||
const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_06_mprefix =
|
||||
@ -5184,7 +5184,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_07_mprefix =
|
||||
const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_02_F3_64_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2698]
|
||||
(const void *)&gInstructions[2700]
|
||||
};
|
||||
|
||||
const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_reg_02_F3_auxiliary =
|
||||
@ -5216,7 +5216,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_ae_reg_02_mprefix =
|
||||
const ND_TABLE_INSTRUCTION gRootTable_root_0f_ae_reg_03_F3_64_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2699]
|
||||
(const void *)&gInstructions[2701]
|
||||
};
|
||||
|
||||
const ND_TABLE_AUXILIARY gRootTable_root_0f_ae_reg_03_F3_auxiliary =
|
||||
@ -5448,19 +5448,19 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_c7_mem_01_auxiliary =
|
||||
const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_06_66_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[1896]
|
||||
(const void *)&gInstructions[1898]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_06_NP_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2022]
|
||||
(const void *)&gInstructions[2024]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_06_F3_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2040]
|
||||
(const void *)&gInstructions[2042]
|
||||
};
|
||||
|
||||
const ND_TABLE_MPREFIX gRootTable_root_0f_c7_mem_06_mprefix =
|
||||
@ -5477,7 +5477,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_c7_mem_06_mprefix =
|
||||
const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_07_NP_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2023]
|
||||
(const void *)&gInstructions[2025]
|
||||
};
|
||||
|
||||
const ND_TABLE_MPREFIX gRootTable_root_0f_c7_mem_07_mprefix =
|
||||
@ -5494,13 +5494,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_c7_mem_07_mprefix =
|
||||
const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_03_NP_None_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2746]
|
||||
(const void *)&gInstructions[2748]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_03_NP_rexw_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2747]
|
||||
(const void *)&gInstructions[2749]
|
||||
};
|
||||
|
||||
const ND_TABLE_AUXILIARY gRootTable_root_0f_c7_mem_03_NP_auxiliary =
|
||||
@ -5532,13 +5532,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_c7_mem_03_mprefix =
|
||||
const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_04_NP_None_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2750]
|
||||
(const void *)&gInstructions[2752]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_04_NP_rexw_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2751]
|
||||
(const void *)&gInstructions[2753]
|
||||
};
|
||||
|
||||
const ND_TABLE_AUXILIARY gRootTable_root_0f_c7_mem_04_NP_auxiliary =
|
||||
@ -5570,13 +5570,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_c7_mem_04_mprefix =
|
||||
const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_05_NP_None_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2754]
|
||||
(const void *)&gInstructions[2756]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gRootTable_root_0f_c7_mem_05_NP_rexw_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2755]
|
||||
(const void *)&gInstructions[2757]
|
||||
};
|
||||
|
||||
const ND_TABLE_AUXILIARY gRootTable_root_0f_c7_mem_05_NP_auxiliary =
|
||||
@ -6275,7 +6275,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_78_None_F2_leaf =
|
||||
const ND_TABLE_INSTRUCTION gRootTable_root_0f_78_None_NP_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2024]
|
||||
(const void *)&gInstructions[2026]
|
||||
};
|
||||
|
||||
const ND_TABLE_MPREFIX gRootTable_root_0f_78_None_mprefix =
|
||||
@ -6332,7 +6332,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_79_None_reg_F2_leaf =
|
||||
const ND_TABLE_INSTRUCTION gRootTable_root_0f_79_None_reg_NP_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2038]
|
||||
(const void *)&gInstructions[2040]
|
||||
};
|
||||
|
||||
const ND_TABLE_MPREFIX gRootTable_root_0f_79_None_reg_mprefix =
|
||||
@ -6349,7 +6349,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_79_None_reg_mprefix =
|
||||
const ND_TABLE_INSTRUCTION gRootTable_root_0f_79_None_mem_NP_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2038]
|
||||
(const void *)&gInstructions[2040]
|
||||
};
|
||||
|
||||
const ND_TABLE_MPREFIX gRootTable_root_0f_79_None_mem_mprefix =
|
||||
@ -6426,7 +6426,7 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_37_None_mprefix =
|
||||
const ND_TABLE_INSTRUCTION gRootTable_root_0f_37_cyrix_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2704]
|
||||
(const void *)&gInstructions[2706]
|
||||
};
|
||||
|
||||
const ND_TABLE_VENDOR gRootTable_root_0f_37_vendor =
|
||||
@ -6630,13 +6630,13 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_mem_01_leaf =
|
||||
const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_mem_04_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[1594]
|
||||
(const void *)&gInstructions[1596]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_mem_05_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[1595]
|
||||
(const void *)&gInstructions[1597]
|
||||
};
|
||||
|
||||
const ND_TABLE_MODRM_REG gRootTable_root_0f_00_mem_modrmreg =
|
||||
@ -6704,13 +6704,13 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_reg_01_leaf =
|
||||
const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_reg_04_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[1594]
|
||||
(const void *)&gInstructions[1596]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gRootTable_root_0f_00_reg_05_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[1595]
|
||||
(const void *)&gInstructions[1597]
|
||||
};
|
||||
|
||||
const ND_TABLE_MODRM_REG gRootTable_root_0f_00_reg_modrmreg =
|
||||
@ -7086,7 +7086,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_a6_reg_00_modrmrm =
|
||||
const ND_TABLE_INSTRUCTION gRootTable_root_0f_a6_reg_01_00_F3_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2757]
|
||||
(const void *)&gInstructions[2759]
|
||||
};
|
||||
|
||||
const ND_TABLE_MPREFIX gRootTable_root_0f_a6_reg_01_00_mprefix =
|
||||
@ -7118,7 +7118,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_a6_reg_01_modrmrm =
|
||||
const ND_TABLE_INSTRUCTION gRootTable_root_0f_a6_reg_02_00_F3_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2758]
|
||||
(const void *)&gInstructions[2760]
|
||||
};
|
||||
|
||||
const ND_TABLE_MPREFIX gRootTable_root_0f_a6_reg_02_00_mprefix =
|
||||
@ -11056,13 +11056,13 @@ const ND_TABLE_INSTRUCTION gRootTable_root_0f_07_leaf =
|
||||
const ND_TABLE_INSTRUCTION gRootTable_root_0f_2e_66_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[1385]
|
||||
(const void *)&gInstructions[1387]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gRootTable_root_0f_2e_NP_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[1386]
|
||||
(const void *)&gInstructions[1388]
|
||||
};
|
||||
|
||||
const ND_TABLE_MPREFIX gRootTable_root_0f_2e_mprefix =
|
||||
@ -11079,31 +11079,31 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_2e_mprefix =
|
||||
const ND_TABLE_INSTRUCTION gRootTable_root_0f_ff_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[1387]
|
||||
(const void *)&gInstructions[1389]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gRootTable_root_0f_b9_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[1388]
|
||||
(const void *)&gInstructions[1390]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gRootTable_root_0f_0b_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[1389]
|
||||
(const void *)&gInstructions[1391]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gRootTable_root_0f_15_66_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[1393]
|
||||
(const void *)&gInstructions[1395]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gRootTable_root_0f_15_NP_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[1394]
|
||||
(const void *)&gInstructions[1396]
|
||||
};
|
||||
|
||||
const ND_TABLE_MPREFIX gRootTable_root_0f_15_mprefix =
|
||||
@ -11120,13 +11120,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_15_mprefix =
|
||||
const ND_TABLE_INSTRUCTION gRootTable_root_0f_14_66_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[1395]
|
||||
(const void *)&gInstructions[1397]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gRootTable_root_0f_14_NP_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[1396]
|
||||
(const void *)&gInstructions[1398]
|
||||
};
|
||||
|
||||
const ND_TABLE_MPREFIX gRootTable_root_0f_14_mprefix =
|
||||
@ -11143,13 +11143,13 @@ const ND_TABLE_MPREFIX gRootTable_root_0f_14_mprefix =
|
||||
const ND_TABLE_INSTRUCTION gRootTable_root_0f_09_None_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2696]
|
||||
(const void *)&gInstructions[2698]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gRootTable_root_0f_09_aF3_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2697]
|
||||
(const void *)&gInstructions[2699]
|
||||
};
|
||||
|
||||
const ND_TABLE_AUXILIARY gRootTable_root_0f_09_auxiliary =
|
||||
@ -11170,25 +11170,25 @@ const ND_TABLE_AUXILIARY gRootTable_root_0f_09_auxiliary =
|
||||
const ND_TABLE_INSTRUCTION gRootTable_root_0f_30_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2700]
|
||||
(const void *)&gInstructions[2702]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gRootTable_root_0f_c0_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2710]
|
||||
(const void *)&gInstructions[2712]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gRootTable_root_0f_c1_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2711]
|
||||
(const void *)&gInstructions[2713]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gRootTable_root_0f_a7_reg_02_00_F3_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2723]
|
||||
(const void *)&gInstructions[2725]
|
||||
};
|
||||
|
||||
const ND_TABLE_MPREFIX gRootTable_root_0f_a7_reg_02_00_mprefix =
|
||||
@ -11220,7 +11220,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_a7_reg_02_modrmrm =
|
||||
const ND_TABLE_INSTRUCTION gRootTable_root_0f_a7_reg_04_00_F3_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2724]
|
||||
(const void *)&gInstructions[2726]
|
||||
};
|
||||
|
||||
const ND_TABLE_MPREFIX gRootTable_root_0f_a7_reg_04_00_mprefix =
|
||||
@ -11252,7 +11252,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_a7_reg_04_modrmrm =
|
||||
const ND_TABLE_INSTRUCTION gRootTable_root_0f_a7_reg_03_00_F3_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2725]
|
||||
(const void *)&gInstructions[2727]
|
||||
};
|
||||
|
||||
const ND_TABLE_MPREFIX gRootTable_root_0f_a7_reg_03_00_mprefix =
|
||||
@ -11284,7 +11284,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_a7_reg_03_modrmrm =
|
||||
const ND_TABLE_INSTRUCTION gRootTable_root_0f_a7_reg_01_00_F3_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2726]
|
||||
(const void *)&gInstructions[2728]
|
||||
};
|
||||
|
||||
const ND_TABLE_MPREFIX gRootTable_root_0f_a7_reg_01_00_mprefix =
|
||||
@ -11316,7 +11316,7 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_a7_reg_01_modrmrm =
|
||||
const ND_TABLE_INSTRUCTION gRootTable_root_0f_a7_reg_05_00_F3_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2727]
|
||||
(const void *)&gInstructions[2729]
|
||||
};
|
||||
|
||||
const ND_TABLE_MPREFIX gRootTable_root_0f_a7_reg_05_00_mprefix =
|
||||
@ -11348,13 +11348,13 @@ const ND_TABLE_MODRM_RM gRootTable_root_0f_a7_reg_05_modrmrm =
|
||||
const ND_TABLE_INSTRUCTION gRootTable_root_0f_a7_reg_00_00_None_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2759]
|
||||
(const void *)&gInstructions[2761]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gRootTable_root_0f_a7_reg_00_00_F3_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2760]
|
||||
(const void *)&gInstructions[2762]
|
||||
};
|
||||
|
||||
const ND_TABLE_MPREFIX gRootTable_root_0f_a7_reg_00_00_mprefix =
|
||||
@ -11410,13 +11410,13 @@ const ND_TABLE_MODRM_MOD gRootTable_root_0f_a7_modrmmod =
|
||||
const ND_TABLE_INSTRUCTION gRootTable_root_0f_57_66_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2741]
|
||||
(const void *)&gInstructions[2743]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gRootTable_root_0f_57_NP_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2742]
|
||||
(const void *)&gInstructions[2744]
|
||||
};
|
||||
|
||||
const ND_TABLE_MPREFIX gRootTable_root_0f_57_mprefix =
|
||||
@ -11786,7 +11786,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_80_05_leaf =
|
||||
const ND_TABLE_INSTRUCTION gRootTable_root_80_06_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2737]
|
||||
(const void *)&gInstructions[2739]
|
||||
};
|
||||
|
||||
const ND_TABLE_MODRM_REG gRootTable_root_80_modrmreg =
|
||||
@ -11849,7 +11849,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_81_05_leaf =
|
||||
const ND_TABLE_INSTRUCTION gRootTable_root_81_06_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2738]
|
||||
(const void *)&gInstructions[2740]
|
||||
};
|
||||
|
||||
const ND_TABLE_MODRM_REG gRootTable_root_81_modrmreg =
|
||||
@ -11912,7 +11912,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_82_05_leaf =
|
||||
const ND_TABLE_INSTRUCTION gRootTable_root_82_06_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2739]
|
||||
(const void *)&gInstructions[2741]
|
||||
};
|
||||
|
||||
const ND_TABLE_MODRM_REG gRootTable_root_82_modrmreg =
|
||||
@ -11975,7 +11975,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_83_05_leaf =
|
||||
const ND_TABLE_INSTRUCTION gRootTable_root_83_06_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2740]
|
||||
(const void *)&gInstructions[2742]
|
||||
};
|
||||
|
||||
const ND_TABLE_MODRM_REG gRootTable_root_83_modrmreg =
|
||||
@ -12599,13 +12599,13 @@ const ND_TABLE_INSTRUCTION gRootTable_root_f6_02_leaf =
|
||||
const ND_TABLE_INSTRUCTION gRootTable_root_f6_00_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[1371]
|
||||
(const void *)&gInstructions[1373]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gRootTable_root_f6_01_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[1372]
|
||||
(const void *)&gInstructions[1374]
|
||||
};
|
||||
|
||||
const ND_TABLE_MODRM_REG gRootTable_root_f6_modrmreg =
|
||||
@ -12662,13 +12662,13 @@ const ND_TABLE_INSTRUCTION gRootTable_root_f7_02_leaf =
|
||||
const ND_TABLE_INSTRUCTION gRootTable_root_f7_00_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[1373]
|
||||
(const void *)&gInstructions[1375]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gRootTable_root_f7_01_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[1374]
|
||||
(const void *)&gInstructions[1376]
|
||||
};
|
||||
|
||||
const ND_TABLE_MODRM_REG gRootTable_root_f7_modrmreg =
|
||||
@ -14830,7 +14830,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_c6_reg_00_leaf =
|
||||
const ND_TABLE_INSTRUCTION gRootTable_root_c6_reg_07_00_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2709]
|
||||
(const void *)&gInstructions[2711]
|
||||
};
|
||||
|
||||
const ND_TABLE_MODRM_RM gRootTable_root_c6_reg_07_modrmrm =
|
||||
@ -14902,7 +14902,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_c7_reg_00_leaf =
|
||||
const ND_TABLE_INSTRUCTION gRootTable_root_c7_reg_07_00_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2712]
|
||||
(const void *)&gInstructions[2714]
|
||||
};
|
||||
|
||||
const ND_TABLE_MODRM_RM gRootTable_root_c7_reg_07_modrmrm =
|
||||
@ -15080,7 +15080,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_90_aF3_leaf =
|
||||
const ND_TABLE_INSTRUCTION gRootTable_root_90_rexb_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2715]
|
||||
(const void *)&gInstructions[2717]
|
||||
};
|
||||
|
||||
const ND_TABLE_AUXILIARY gRootTable_root_90_auxiliary =
|
||||
@ -16284,127 +16284,127 @@ const ND_TABLE_INSTRUCTION gRootTable_root_2d_leaf =
|
||||
const ND_TABLE_INSTRUCTION gRootTable_root_84_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[1367]
|
||||
(const void *)&gInstructions[1369]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gRootTable_root_85_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[1368]
|
||||
(const void *)&gInstructions[1370]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gRootTable_root_a8_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[1369]
|
||||
(const void *)&gInstructions[1371]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gRootTable_root_a9_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[1370]
|
||||
(const void *)&gInstructions[1372]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gRootTable_root_9b_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2695]
|
||||
(const void *)&gInstructions[2697]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gRootTable_root_86_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2713]
|
||||
(const void *)&gInstructions[2715]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gRootTable_root_87_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2714]
|
||||
(const void *)&gInstructions[2716]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gRootTable_root_91_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2716]
|
||||
(const void *)&gInstructions[2718]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gRootTable_root_92_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2717]
|
||||
(const void *)&gInstructions[2719]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gRootTable_root_93_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2718]
|
||||
(const void *)&gInstructions[2720]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gRootTable_root_94_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2719]
|
||||
(const void *)&gInstructions[2721]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gRootTable_root_95_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2720]
|
||||
(const void *)&gInstructions[2722]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gRootTable_root_96_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2721]
|
||||
(const void *)&gInstructions[2723]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gRootTable_root_97_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2722]
|
||||
(const void *)&gInstructions[2724]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gRootTable_root_d7_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2730]
|
||||
(const void *)&gInstructions[2732]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gRootTable_root_30_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2731]
|
||||
(const void *)&gInstructions[2733]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gRootTable_root_31_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2732]
|
||||
(const void *)&gInstructions[2734]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gRootTable_root_32_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2733]
|
||||
(const void *)&gInstructions[2735]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gRootTable_root_33_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2734]
|
||||
(const void *)&gInstructions[2736]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gRootTable_root_34_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2735]
|
||||
(const void *)&gInstructions[2737]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gRootTable_root_35_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2736]
|
||||
(const void *)&gInstructions[2738]
|
||||
};
|
||||
|
||||
const ND_TABLE_OPCODE gRootTable_root_opcode =
|
||||
|
File diff suppressed because it is too large
Load Diff
@ -345,7 +345,7 @@ const ND_TABLE_INSTRUCTION gXopTable_root_09_01_07_leaf =
|
||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_01_04_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[1384]
|
||||
(const void *)&gInstructions[1386]
|
||||
};
|
||||
|
||||
const ND_TABLE_MODRM_REG gXopTable_root_09_01_modrmreg =
|
||||
@ -429,127 +429,127 @@ const ND_TABLE_MODRM_MOD gXopTable_root_09_12_modrmmod =
|
||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_81_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[1822]
|
||||
(const void *)&gInstructions[1824]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_80_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[1823]
|
||||
(const void *)&gInstructions[1825]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_83_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[1824]
|
||||
(const void *)&gInstructions[1826]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_82_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[1825]
|
||||
(const void *)&gInstructions[1827]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_c2_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2243]
|
||||
(const void *)&gInstructions[2245]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_c3_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2244]
|
||||
(const void *)&gInstructions[2246]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_c1_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2245]
|
||||
(const void *)&gInstructions[2247]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_cb_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2247]
|
||||
(const void *)&gInstructions[2249]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_d2_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2249]
|
||||
(const void *)&gInstructions[2251]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_d3_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2250]
|
||||
(const void *)&gInstructions[2252]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_d1_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2251]
|
||||
(const void *)&gInstructions[2253]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_db_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2252]
|
||||
(const void *)&gInstructions[2254]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_d6_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2253]
|
||||
(const void *)&gInstructions[2255]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_d7_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2254]
|
||||
(const void *)&gInstructions[2256]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_c6_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2256]
|
||||
(const void *)&gInstructions[2258]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_c7_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2257]
|
||||
(const void *)&gInstructions[2259]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_e1_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2259]
|
||||
(const void *)&gInstructions[2261]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_e3_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2261]
|
||||
(const void *)&gInstructions[2263]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_e2_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2264]
|
||||
(const void *)&gInstructions[2266]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_90_00_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2428]
|
||||
(const void *)&gInstructions[2430]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_90_01_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2429]
|
||||
(const void *)&gInstructions[2431]
|
||||
};
|
||||
|
||||
const ND_TABLE_VEX_W gXopTable_root_09_90_w =
|
||||
@ -564,13 +564,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_90_w =
|
||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_92_00_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2431]
|
||||
(const void *)&gInstructions[2433]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_92_01_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2432]
|
||||
(const void *)&gInstructions[2434]
|
||||
};
|
||||
|
||||
const ND_TABLE_VEX_W gXopTable_root_09_92_w =
|
||||
@ -585,13 +585,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_92_w =
|
||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_93_00_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2434]
|
||||
(const void *)&gInstructions[2436]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_93_01_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2435]
|
||||
(const void *)&gInstructions[2437]
|
||||
};
|
||||
|
||||
const ND_TABLE_VEX_W gXopTable_root_09_93_w =
|
||||
@ -606,13 +606,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_93_w =
|
||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_91_00_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2437]
|
||||
(const void *)&gInstructions[2439]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_91_01_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2438]
|
||||
(const void *)&gInstructions[2440]
|
||||
};
|
||||
|
||||
const ND_TABLE_VEX_W gXopTable_root_09_91_w =
|
||||
@ -627,13 +627,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_91_w =
|
||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_98_00_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2445]
|
||||
(const void *)&gInstructions[2447]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_98_01_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2446]
|
||||
(const void *)&gInstructions[2448]
|
||||
};
|
||||
|
||||
const ND_TABLE_VEX_W gXopTable_root_09_98_w =
|
||||
@ -648,13 +648,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_98_w =
|
||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_9a_00_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2447]
|
||||
(const void *)&gInstructions[2449]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_9a_01_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2448]
|
||||
(const void *)&gInstructions[2450]
|
||||
};
|
||||
|
||||
const ND_TABLE_VEX_W gXopTable_root_09_9a_w =
|
||||
@ -669,13 +669,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_9a_w =
|
||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_9b_00_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2449]
|
||||
(const void *)&gInstructions[2451]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_9b_01_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2450]
|
||||
(const void *)&gInstructions[2452]
|
||||
};
|
||||
|
||||
const ND_TABLE_VEX_W gXopTable_root_09_9b_w =
|
||||
@ -690,13 +690,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_9b_w =
|
||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_99_00_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2451]
|
||||
(const void *)&gInstructions[2453]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_99_01_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2452]
|
||||
(const void *)&gInstructions[2454]
|
||||
};
|
||||
|
||||
const ND_TABLE_VEX_W gXopTable_root_09_99_w =
|
||||
@ -711,13 +711,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_99_w =
|
||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_94_00_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2453]
|
||||
(const void *)&gInstructions[2455]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_94_01_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2454]
|
||||
(const void *)&gInstructions[2456]
|
||||
};
|
||||
|
||||
const ND_TABLE_VEX_W gXopTable_root_09_94_w =
|
||||
@ -732,13 +732,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_94_w =
|
||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_95_01_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2455]
|
||||
(const void *)&gInstructions[2457]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_95_00_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2466]
|
||||
(const void *)&gInstructions[2468]
|
||||
};
|
||||
|
||||
const ND_TABLE_VEX_W gXopTable_root_09_95_w =
|
||||
@ -753,13 +753,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_95_w =
|
||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_96_01_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2456]
|
||||
(const void *)&gInstructions[2458]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_96_00_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2457]
|
||||
(const void *)&gInstructions[2459]
|
||||
};
|
||||
|
||||
const ND_TABLE_VEX_W gXopTable_root_09_96_w =
|
||||
@ -774,13 +774,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_96_w =
|
||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_97_00_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2464]
|
||||
(const void *)&gInstructions[2466]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopTable_root_09_97_01_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2465]
|
||||
(const void *)&gInstructions[2467]
|
||||
};
|
||||
|
||||
const ND_TABLE_VEX_W gXopTable_root_09_97_w =
|
||||
@ -1058,13 +1058,13 @@ const ND_TABLE_OPCODE gXopTable_root_09_opcode =
|
||||
const ND_TABLE_INSTRUCTION gXopTable_root_08_a2_00_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2115]
|
||||
(const void *)&gInstructions[2117]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopTable_root_08_a2_01_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2116]
|
||||
(const void *)&gInstructions[2118]
|
||||
};
|
||||
|
||||
const ND_TABLE_VEX_W gXopTable_root_08_a2_w =
|
||||
@ -1079,133 +1079,133 @@ const ND_TABLE_VEX_W gXopTable_root_08_a2_w =
|
||||
const ND_TABLE_INSTRUCTION gXopTable_root_08_cc_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2145]
|
||||
(const void *)&gInstructions[2147]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopTable_root_08_ce_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2146]
|
||||
(const void *)&gInstructions[2148]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopTable_root_08_cf_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2151]
|
||||
(const void *)&gInstructions[2153]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopTable_root_08_ec_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2152]
|
||||
(const void *)&gInstructions[2154]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopTable_root_08_ee_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2153]
|
||||
(const void *)&gInstructions[2155]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopTable_root_08_ef_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2154]
|
||||
(const void *)&gInstructions[2156]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopTable_root_08_ed_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2155]
|
||||
(const void *)&gInstructions[2157]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopTable_root_08_cd_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2156]
|
||||
(const void *)&gInstructions[2158]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopTable_root_08_9e_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2279]
|
||||
(const void *)&gInstructions[2281]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopTable_root_08_9f_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2280]
|
||||
(const void *)&gInstructions[2282]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopTable_root_08_97_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2281]
|
||||
(const void *)&gInstructions[2283]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopTable_root_08_8e_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2282]
|
||||
(const void *)&gInstructions[2284]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopTable_root_08_8f_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2283]
|
||||
(const void *)&gInstructions[2285]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopTable_root_08_87_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2284]
|
||||
(const void *)&gInstructions[2286]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopTable_root_08_86_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2285]
|
||||
(const void *)&gInstructions[2287]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopTable_root_08_85_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2286]
|
||||
(const void *)&gInstructions[2288]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopTable_root_08_96_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2287]
|
||||
(const void *)&gInstructions[2289]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopTable_root_08_95_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2288]
|
||||
(const void *)&gInstructions[2290]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopTable_root_08_a6_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2289]
|
||||
(const void *)&gInstructions[2291]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopTable_root_08_b6_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2290]
|
||||
(const void *)&gInstructions[2292]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopTable_root_08_a3_00_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2417]
|
||||
(const void *)&gInstructions[2419]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopTable_root_08_a3_01_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2418]
|
||||
(const void *)&gInstructions[2420]
|
||||
};
|
||||
|
||||
const ND_TABLE_VEX_W gXopTable_root_08_a3_w =
|
||||
@ -1220,25 +1220,25 @@ const ND_TABLE_VEX_W gXopTable_root_08_a3_w =
|
||||
const ND_TABLE_INSTRUCTION gXopTable_root_08_c0_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2427]
|
||||
(const void *)&gInstructions[2429]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopTable_root_08_c2_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2430]
|
||||
(const void *)&gInstructions[2432]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopTable_root_08_c3_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2433]
|
||||
(const void *)&gInstructions[2435]
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopTable_root_08_c1_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[2436]
|
||||
(const void *)&gInstructions[2438]
|
||||
};
|
||||
|
||||
const ND_TABLE_OPCODE gXopTable_root_08_opcode =
|
||||
|
@ -22,4 +22,7 @@
|
||||
db 0xc4, 0xe2, 0x7b, 0x49, 0xC0 ; TILEZERO tmm0
|
||||
db 0xc4, 0xe2, 0x7b, 0x49, 0xf8 ; TILEZERO tmm7
|
||||
|
||||
db 0xc4, 0xe2, 0x7b, 0x5C, 0xF4 ; TDPFP16PS tmm6, tmm4, tmm0
|
||||
db 0xc4, 0xe2, 0x7b, 0x5C, 0xF4 ; TDPFP16PS tmm6, tmm4, tmm0
|
||||
|
||||
db 0xc4, 0xe2, 0x78, 0x6C, 0xF4 ; TCMMRLFP16PS tmm6, tmm4, tmm0
|
||||
db 0xc4, 0xe2, 0x79, 0x6C, 0xF4 ; TCMMIMFP16PS tmm6, tmm4, tmm
|
@ -295,3 +295,39 @@
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: M, RegType: Tile, RegSize: 1024, RegId: 4, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: V, RegType: Tile, RegSize: 1024, RegId: 0, RegCount: 1
|
||||
|
||||
0000000000000067 c4e2786cf4 TCMMRLFP16PS tmm6, tmm4, tmm0
|
||||
DSIZE: 32, ASIZE: 64, VLEN: -
|
||||
ISA Set: AMX-COMPLEX, Ins cat: AMX, CET tracked: no
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 8
|
||||
Exception class: AMX, exception type: AMX-E4
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: no, Compat: no, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: no, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: RW, Type: Register, Size: 1024, RawSize: 1024, Encoding: R, RegType: Tile, RegSize: 1024, RegId: 6, RegCount: 1
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: M, RegType: Tile, RegSize: 1024, RegId: 4, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: V, RegType: Tile, RegSize: 1024, RegId: 0, RegCount: 1
|
||||
|
||||
000000000000006C c4e2796cf4 TCMMIMFP16PS tmm6, tmm4, tmm0
|
||||
DSIZE: 32, ASIZE: 64, VLEN: -
|
||||
ISA Set: AMX-COMPLEX, Ins cat: AMX, CET tracked: no
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 8
|
||||
Exception class: AMX, exception type: AMX-E4
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: no, Compat: no, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: no, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: RW, Type: Register, Size: 1024, RawSize: 1024, Encoding: R, RegType: Tile, RegSize: 1024, RegId: 6, RegCount: 1
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: M, RegType: Tile, RegSize: 1024, RegId: 4, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: V, RegType: Tile, RegSize: 1024, RegId: 0, RegCount: 1
|
||||
|
||||
|
Binary file not shown.
@ -12,7 +12,7 @@ from setuptools import find_packages, setup, Command, Extension, Distribution
|
||||
from codecs import open
|
||||
|
||||
VERSION = (0, 1, 3)
|
||||
LIBRARY_VERSION = (1, 36, 0)
|
||||
LIBRARY_VERSION = (1, 37, 0)
|
||||
LIBRARY_INSTRUX_SIZE = 856
|
||||
|
||||
packages = ['pybddisasm']
|
||||
|
@ -111,6 +111,7 @@ set_to_string(
|
||||
case ND_SET_AMXFP16: return "AMX-FP16";
|
||||
case ND_SET_AMXINT8: return "AMX-INT8";
|
||||
case ND_SET_AMXTILE: return "AMX-TILE";
|
||||
case ND_SET_AMXCOMPLEX: return "AMX-COMPLEX";
|
||||
case ND_SET_AVX: return "AVX";
|
||||
case ND_SET_AVX2: return "AVX2";
|
||||
case ND_SET_AVX2GATHER: return "AVX2GATHER";
|
||||
|
@ -1586,6 +1586,8 @@ std::string ins_class_to_str(const ND_INS_CLASS cls)
|
||||
case ND_INS_WRMSRLIST: return "wrmsrlist";
|
||||
case ND_INS_WRMSRNS: return "wrmsrns";
|
||||
case ND_INS_RMPQUERY: return "rmpquery";
|
||||
case ND_INS_TCMMRLFP16PS: return "tcmmrlfp16ps";
|
||||
case ND_INS_TCMMIMFP16PS: return "tcmmimfp16ps";
|
||||
default: return "unhandled!";
|
||||
}
|
||||
|
||||
@ -1722,6 +1724,7 @@ std::string ins_set_to_str(ND_INS_SET ins_set)
|
||||
case ND_SET_AMXBF16: return "amxbf16";
|
||||
case ND_SET_AMXINT8: return "amxint8";
|
||||
case ND_SET_AMXTILE: return "amxtile";
|
||||
case ND_SET_AMXCOMPLEX: return "amxcomplex";
|
||||
case ND_SET_AVX: return "avx";
|
||||
case ND_SET_AVX2: return "avx2";
|
||||
case ND_SET_AVX2GATHER: return "avx2gather";
|
||||
|
@ -724,6 +724,8 @@ typedef enum _ND_INS_CLASS
|
||||
ND_INS_SYSEXIT,
|
||||
ND_INS_SYSRET,
|
||||
ND_INS_T1MSKC,
|
||||
ND_INS_TCMMIMFP16PS,
|
||||
ND_INS_TCMMRLFP16PS,
|
||||
ND_INS_TDCALL,
|
||||
ND_INS_TDPBF16PS,
|
||||
ND_INS_TDPBSSD,
|
||||
@ -1650,6 +1652,7 @@ typedef enum _ND_INS_SET
|
||||
ND_SET_AES,
|
||||
ND_SET_AMD,
|
||||
ND_SET_AMXBF16,
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||||
ND_SET_AMXCOMPLEX,
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ND_SET_AMXFP16,
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ND_SET_AMXINT8,
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||||
ND_SET_AMXTILE,
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|
@ -107,6 +107,7 @@
|
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#define ND_CFF_MSRLIST ND_CFF(0x00000007, 0x00000001, NDR_EAX, 27)
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||||
#define ND_CFF_AVXVNNIINT8 ND_CFF(0x00000007, 0x00000001, NDR_EDX, 4)
|
||||
#define ND_CFF_AVXNECONVERT ND_CFF(0x00000007, 0x00000001, NDR_EDX, 5)
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#define ND_CFF_AMXCOMPLEX ND_CFF(0x00000007, 0x00000001, NDR_EDX, 8)
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||||
#define ND_CFF_PREFETCHITI ND_CFF(0x00000007, 0x00000001, NDR_EDX, 14)
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||||
#define ND_CFF_XSAVEOPT ND_CFF(0x0000000D, 0x00000001, NDR_EAX, 0)
|
||||
#define ND_CFF_XSAVEC ND_CFF(0x0000000D, 0x00000001, NDR_EAX, 1)
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|
@ -6,7 +6,7 @@
|
||||
#define DISASM_VER_H
|
||||
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||||
#define DISASM_VERSION_MAJOR 1
|
||||
#define DISASM_VERSION_MINOR 36
|
||||
#define DISASM_VERSION_MINOR 37
|
||||
#define DISASM_VERSION_REVISION 0
|
||||
|
||||
// bdshemu depends on bddisasm. It cannot be used without it.
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||||
|
@ -109,6 +109,7 @@ MSRLIST : 0x00000007, 0x00000001, EAX, 27
|
||||
|
||||
AVXVNNIINT8 : 0x00000007, 0x00000001, EDX, 4
|
||||
AVXNECONVERT : 0x00000007, 0x00000001, EDX, 5
|
||||
AMXCOMPLEX : 0x00000007, 0x00000001, EDX, 8
|
||||
PREFETCHITI : 0x00000007, 0x00000001, EDX, 14
|
||||
|
||||
|
||||
|
@ -182,8 +182,7 @@ NOP ; Ev ; n/a ; piti 0x0F 0x18 /7:r
|
||||
|
||||
|
||||
# MPX instructions. According to the SDM, MPX instructions have 64 bit op & address size in 64 bit mode, no matter
|
||||
# if 0x66 or 0x67 prefixes are used. 16 bit addressing cause #UD. However, these checks are not handled here (note
|
||||
# that Xed doesn't do those checks either).
|
||||
# if 0x66 or 0x67 prefixes are used. 16 bit addressing cause #UD. However, these checks are not handled here.
|
||||
|
||||
# MPX not used, these guys are wide NOPs.
|
||||
NOP ; Ev,Gv ; n/a ; 0x0F 0x1A /r ; s:PPRO, t:WIDENOP, w:N|N
|
||||
@ -312,7 +311,7 @@ CMOVLE ; Gv,Ev ; Fv ; 0x0F 0x4E /r
|
||||
CMOVNLE ; Gv,Ev ; Fv ; 0x0F 0x4F /r ; s:PPRO, t:CMOV, c:CMOVcc, w:CW|R|R, i:CMOV, f:CNLE, a:COND
|
||||
|
||||
# 0x50 - 0x5F
|
||||
# Note: for MOVMSKPS & MOVMSKPD, the Intel doc says the destination reg is y (32 or 64 bit) but XED says it must be d (only 32 bits).
|
||||
# Note: for MOVMSKPS & MOVMSKPD, the Intel doc says the destination reg is y (32 or 64 bit).
|
||||
MOVMSKPS ; Gy,Ups ; n/a ; NP 0x0F 0x50 /r:reg ; s:SSE, t:DATAXFER, w:W|R, e:7, a:D64
|
||||
MOVMSKPD ; Gy,Upd ; n/a ; 0x66 0x0F 0x50 /r:reg ; s:SSE2, t:DATAXFER, w:W|R, e:7, a:D64
|
||||
SQRTPS ; Vps,Wps ; n/a ; NP 0x0F 0x51 /r ; s:SSE, t:SSE, w:W|R, e:2
|
||||
|
@ -120,6 +120,8 @@ TDPBSUD ; rTt,mTt,vTt ; n/a ; vex m:2 p:2 l:0 w:0
|
||||
TDPBSSD ; rTt,mTt,vTt ; n/a ; vex m:2 p:3 l:0 w:0 0x5E /r:reg ; s:AMXINT8, t:AMX, w:RW|R|R, m:NOTSX|O64, e:AMX_E4
|
||||
|
||||
# 0x60 - 0x6F
|
||||
TCMMRLFP16PS ; rTt,mTt,vTt ; n/a ; vex m:2 p:0 l:0 w:0 0x6C /r:reg ; s:AMXCOMPLEX, t:AMX, w:RW|R|R, m:NOTSX|O64, e:AMX_E4
|
||||
TCMMIMFP16PS ; rTt,mTt,vTt ; n/a ; vex m:2 p:1 l:0 w:0 0x6C /r:reg ; s:AMXCOMPLEX, t:AMX, w:RW|R|R, m:NOTSX|O64, e:AMX_E4
|
||||
|
||||
# 0x70 - 0x7F
|
||||
VCVTNEPS2BF16 ; Vx,Wx ; n/a ; vex m:2 p:2 l:x w:0 0x72 /r ; s:AVXNECONVERT, t:AVXNECONVERT, w:W|R, e:4
|
||||
|
Loading…
Reference in New Issue
Block a user