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Handle reserved bits in RFLAGS when setting the entire register value.
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@ -1363,6 +1363,9 @@ ShemuSetOperandValue(
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case ND_REG_FLG:
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Context->Registers.RegFlags = ND_TRIM(Value->Size, Value->Value.Qwords[0]);
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// Handle reserved bits.
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Context->Registers.RegFlags |= (1ULL << 1);
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Context->Registers.RegFlags &= ~((1ULL << 3) | (1ULL << 5) | (1ULL << 15));
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break;
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case ND_REG_CR:
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@ -12,6 +12,6 @@
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// bdshemu depends on bddisasm. It cannot be used without it.
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#define SHEMU_VERSION_MAJOR 1
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#define SHEMU_VERSION_MINOR 1
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#define SHEMU_VERSION_REVISION 12
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#define SHEMU_VERSION_REVISION 13
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#endif // DISASM_VER_H
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