Handle reserved bits in RFLAGS when setting the entire register value.

pull/78/head
BITDEFENDER\vlutas 2 years ago
parent f62c8a2238
commit 2fc491d51d

@ -1363,6 +1363,9 @@ ShemuSetOperandValue(
case ND_REG_FLG:
Context->Registers.RegFlags = ND_TRIM(Value->Size, Value->Value.Qwords[0]);
// Handle reserved bits.
Context->Registers.RegFlags |= (1ULL << 1);
Context->Registers.RegFlags &= ~((1ULL << 3) | (1ULL << 5) | (1ULL << 15));
break;
case ND_REG_CR:

@ -12,6 +12,6 @@
// bdshemu depends on bddisasm. It cannot be used without it.
#define SHEMU_VERSION_MAJOR 1
#define SHEMU_VERSION_MINOR 1
#define SHEMU_VERSION_REVISION 12
#define SHEMU_VERSION_REVISION 13
#endif // DISASM_VER_H

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