02cbe6a298https://github.com/bitdefender/bddisasm/issues/87 - added missing `R` access for the `rIP` operand for `SYSCALL` instructions; added missing `SCS`, `rCX` and `rDX` operands for `SYSEXIT` instruction.
Andrei Vlad LUTAS
2024-02-27 09:45:05 +0200
f6f93c4112Fixed pybddisasm version.
Andrei Vlad LUTAS
2024-02-26 21:03:14 +0200
3df189f093https://github.com/bitdefender/bddisasm/issues/87 - Fixed `CALL` instruction access for `rIP` operand - it must include read access, as the instruction pointer is saved on the stack.
Andrei Vlad LUTAS
2024-02-26 20:53:42 +0200
f53cbc51e2Added support for new Intel ISA, per Intel® Architecture Instruction Set Extensions and Future Features document #319433-049 (June 2023): AVX-NNI-INT16, SHA512, SM3, SM4, TSE.
Andrei Vlad LUTAS
2023-07-21 09:38:49 +0300
124521beb5Added support for Intel AMX-COMPLEX instructions.
BITDEFENDER\vlutas
2023-04-05 09:45:07 +0300
ee6cdd6cb6Switched to a more parsing-friendly format for the instructions database, where individual components are sepparated by a semicolon.
BITDEFENDER\vlutas
2023-02-09 10:54:45 +0200
24665b0531Switched from nil to n/a naming for absent operands, as it is more obvious.
BITDEFENDER\vlutas
2023-02-08 17:44:45 +0200
0093439855Added some comments.
BITDEFENDER\vlutas
2023-02-02 22:10:56 +0200
089e6d5e7eSignificant cleanup in disasmtool: the obsolete search functionality, and supplying registers for shemu from a file are no longer supported.
BITDEFENDER\vlutas
2023-02-02 21:46:24 +0200
61382e95f0Since all the shemu test file are synthetic and clean, I removed the password from the test archive.
BITDEFENDER\vlutas
2022-12-16 15:17:39 +0200
9ba1e6a2f9Added support for new Intel instructions, per Intel ISA extensions document #319433-046 (September 2022): PREFETCHITI, RAO-INT, CMPCCXADD, WRMSRNS, MSRLIST, AMX-FP16, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8. Multiple minor fixes to existing instructions. Moved x86 decoding tests in a separate directory & improved the test script.
BITDEFENDER\vlutas
2022-10-04 12:22:59 +0300
4596dbda51Add copyright info when auto-generating files.
BITDEFENDER\vlutas
2022-09-10 23:15:00 +0300
b109990ba2Removed some unneeded code.
BITDEFENDER\vlutas
2022-08-09 20:15:30 +0300
47da322ea5Improved upper bits handling for SSE/AVX operations. Improved POPF handling when 16 bit operand size is used. Fixed typo in PUNPCKLBW emulation.
BITDEFENDER\vlutas
2022-08-09 20:02:45 +0300
2fc491d51dHandle reserved bits in RFLAGS when setting the entire register value.
BITDEFENDER\vlutas
2022-08-08 12:02:00 +0300
d3fd900903Fixed OF on SHL and SHR with one bit shifts.
BITDEFENDER\vlutas
2022-08-01 14:13:27 +0300
bf81c647e3Make sure all flags are set for CMPXCHG (this was left intentionally incomplete). Make sure we clear upper bits of the 256/512 bit SSE register.
BITDEFENDER\vlutas
2022-07-19 11:03:17 +0300
6dda2c122cMake sure upper 32 bit of a CMOV destination register is cleared to 0 even if the condition is not satisfied
BITDEFENDER\vlutas
2022-07-16 12:21:46 +0300
1805a9edecFixed flag setting for ADC, SBB, SAR and IMUL instructions.
BITDEFENDER\vlutas
2022-07-14 13:42:37 +0300
2f50ce9b4eImproved REG_ID macros - make sure we include block addressing and High8 designator in the reg ID. Alsom, make sure the register size fits in, since the new tile register can be 1K in size, which previously overflowed...
BITDEFENDER\vlutas
2021-12-03 12:44:57 +0200
4ff620cb76Added bdhelpers to CMake.
BITDEFENDER\vlutas
2021-11-03 09:34:04 +0200
433e723e07Implemented a reverse oprand lookup table. It holds pointers to relevant operands inside INSTRUX, for quick lookup. Moved helper functions in bdhelpers.c. Added a dedicated BranchInfo field inside INSTRUX, containing the most relevant branch information.
BITDEFENDER\vlutas
2021-11-02 11:22:22 +0200
412f065965Moved the formatting function in a dedicated source file. Added support for SIDT and RDTSC in bdshemu.
BITDEFENDER\vlutas
2021-10-19 17:33:15 +0300