BITDEFENDER\vlutas
124521beb5
Added support for Intel AMX-COMPLEX instructions.
2023-04-05 09:45:07 +03:00
BITDEFENDER\vlutas
7a254037b0
Added support for AMD RMPQUERY instruction.
2022-10-27 12:37:02 +03:00
BITDEFENDER\vlutas
9ba1e6a2f9
Added support for new Intel instructions, per Intel ISA extensions document #319433-046 (September 2022): PREFETCHITI, RAO-INT, CMPCCXADD, WRMSRNS, MSRLIST, AMX-FP16, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8.
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Multiple minor fixes to existing instructions.
Moved x86 decoding tests in a separate directory & improved the test script.
2022-10-04 12:22:59 +03:00
BITDEFENDER\vlutas
7749e06b9d
Removed ND_CAT_FRED.
2021-11-02 11:30:11 +02:00
Andrei Vlad LUTAS
76d92e73c2
Multiple changes
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- Add support for AVX512-FP16 instructions, as per https://software.intel.com/content/www/us/en/develop/download/intel-avx512-fp16-architecture-specification.html
- Bug fix: zeroing with no masking is not supported, so return an error if we encounter such encodings
- Bug fix: ignore VEX/EVEX.W field outside 64 bit mode for some instructions
- Several other minor fixes and improvements
2021-07-08 12:40:39 +03:00
Andrei Vlad LUTAS
fccf11915d
Added support for Intel FRED and LKGS instructions.
2021-03-15 14:05:44 +02:00
Andrei Vlad LUTAS
460e544652
Fixed build.
2020-11-09 09:52:49 +02:00
Andrei Vlad LUTAS
58197cc518
Removed support for PCOMMIT and CL1INVMB (not implemented by any x86/x64 CPUs), and marked MOV to/from test registers as being invalid in long mode.
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Fixed https://github.com/bitdefender/bddisasm/issues/24
Fixed https://github.com/bitdefender/bddisasm/issues/25
Fixed https://github.com/bitdefender/bddisasm/issues/26
2020-11-09 09:18:46 +02:00
Andrei Vlad LUTAS
9652450125
Added support for UINTR, HRESET and AVX-VNNI instructions, as per Intel® Architecture Instruction Set Extensions Programming Reference 41 (October 2020).
2020-10-05 13:19:03 +03:00
Andrei Vlad LUTAS
4f8b030ddd
Added support for Intel Key Locker instructions, as per https://software.intel.com/content/www/us/en/develop/download/intel-key-locker-specification.html .
2020-09-16 11:56:05 +03:00
Andrei Vlad LUTAS
33078e4670
Added support for TDX instructions, per https://software.intel.com/content/dam/develop/external/us/en/documents/intel-tdx-cpu-architectural-specification.pdf .
2020-09-10 11:06:20 +03:00
Andrei Vlad LUTAS
144baa5140
Renamed REG_* fields to NDR_*, so that we don't conflict with _GNU_SOURCES.
2020-07-29 11:05:27 +03:00
Cristian-Bogdan SIRB
2868b2afde
disasmtool_lix: Added the --extended parameter which shows the instructions info
2020-07-28 16:14:28 +03:00
Ionel-Cristinel ANICHITEI
087ffbcf95
disasmtool_lix: Add missing instructions to ins_class_to_str
2020-07-23 15:54:05 +03:00
Andrei Vlad LUTAS
752bc626c4
Fixed RET with immediate - the immediate is not sign-extended.
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Fixed VEX decoding in 32 bit mode - vex.vvvv bit 3 is simply ignored.
Fixed several FMA instructions decoding (L/W flag should be ignored).
Print the 64 bit immediate value in disassembly, instead of the raw immediate (note that the operand always contains the sign-extended, full immediate).
XBEGIN always uses 32/64 bit RIP size (0x66 does not affect its size).
Decode WBINVD even if it's preceded by 0x66/0xF2 prefixes.
Several mnemonic fixes (FXSAVE64, FXRSTOR64, PUSHA/PUSHAD...).
Properly decode VPERMIL2* instructions.
Fixed SSE register decoding when it is encoded in immediate.
Decode SCATTER instructions even though they use the VSIB index as source.
Some disp8 fixes (t1s -> t1s8/t1s16).
SYSCALL/SYSRET are decoded and executed in 32 bit compat modem, even though SDM states they are invalid.
RDPID uses 32/64 bit reg size, never 16.
Various other minor tweaks & fixes.
Re-generated the test files, and added some more, new tests.
2020-07-23 14:08:01 +03:00
Andrei Vlad LUTAS
960e9eaeee
disasmtool_lix dumper fix - dump cet_ss and cet_ibt.
2020-07-22 09:32:18 +03:00
Andrei Vlad LUTAS
698ba367a1
Initial commit.
2020-07-21 11:19:18 +03:00
