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Fixed RET with immediate - the immediate is not sign-extended.

Browse Source 
Fixed VEX decoding in 32 bit mode - vex.vvvv bit 3 is simply ignored.
Fixed several FMA instructions decoding (L/W flag should be ignored).
Print the 64 bit immediate value in disassembly, instead of the raw immediate (note that the operand always contains the sign-extended, full immediate).
XBEGIN always uses 32/64 bit RIP size (0x66 does not affect its size).
Decode WBINVD even if it's preceded by 0x66/0xF2 prefixes.
Several mnemonic fixes (FXSAVE64, FXRSTOR64, PUSHA/PUSHAD...).
Properly decode VPERMIL2* instructions.
Fixed SSE register decoding when it is encoded in immediate.
Decode SCATTER instructions even though they use the VSIB index as source.
Some disp8 fixes (t1s -> t1s8/t1s16).
SYSCALL/SYSRET are decoded and executed in 32 bit compat modem, even though SDM states they are invalid.
RDPID uses 32/64 bit reg size, never 16.
Various other minor tweaks & fixes.
Re-generated the test files, and added some more, new tests.
pull/9/head
Andrei Vlad LUTAS 3 years ago
parent 52ed638c13
commit 752bc626c4
60 changed files with 7135 additions and 6755 deletions
Show Stats Download Patch File Download Diff File

53
bddisasm/bddisasm.c
Unescape View File

@ -203,6 +203,8 @@ static const uint16_t gOperandMap[] =
ND_OPE_S, // ND_OPT_MEM_SHSP
ND_OPE_S, // ND_OPT_MEM_SHS0
ND_OPE_L, // ND_OPT_Im2z
ND_OPE_S, // ND_OPT_CR_0
ND_OPE_S, // ND_OPT_IDTR
ND_OPE_S, // ND_OPT_GDTR
@ -529,10 +531,7 @@ NdFetchVex3(
// Vex.R and Vex.X have been tested by the initial if.
// Vex.vvvv must be less than 8.
if ((Instrux->Exs.v & 0x8) == 0x8)
{
return ND_STATUS_INVALID_ENCODING_IN_MODE;
}
Instrux->Exs.v &= 7;
// Vex.B is ignored, so we force it to 0.
Instrux->Exs.b = 0;
@ -1243,7 +1242,7 @@ NdGetCompDispSize(
case ND_TUPLE_T1S16:
return 2;
case ND_TUPLE_T1S:
return Instrux->Exs.w ? 8 : 4;
return !!(Instrux->Attributes & ND_FLAG_WIG) ? 4 : Instrux->Exs.w ? 8 : 4;
case ND_TUPLE_T1F:
return (uint8_t)MemSize;
case ND_TUPLE_T2:
@ -2330,6 +2329,13 @@ NdParseOperand(
}
break;
case ND_OPT_Im2z:
{
operand->Type = ND_OP_IMM;
operand->Info.Immediate.Imm = Instrux->SseImmediate & 3;
}
break;
case ND_OPT_J:
// Fetch the relative offset. NOTE: The size of the relative can't exceed 4 bytes.
status = NdFetchRelativeOffset(Instrux, Code, Offset, Size, (uint8_t)size);
@ -2571,12 +2577,6 @@ memory:
{
if ((Instrux->ModRm.mod == 0) && (Instrux->ModRm.rm == REG_RBP))
{
// Some instructions (example: MPX) don't support RIP relative addressing.
if (!!(Instrux->Attributes & ND_FLAG_NO_RIP_REL))
{
return ND_STATUS_RIP_REL_ADDRESSING_NOT_SUPPORTED;
}
//
// RIP relative addressing addresses a memory region relative to the current RIP; However,
// the current RIP, when executing the current instruction, is already updated and points
@ -2585,6 +2585,12 @@ memory:
// addressing, as long as we're in long mode.
//
operand->Info.Memory.IsRipRel = Instrux->IsRipRelative = (Instrux->DefCode == ND_CODE_64);
// Some instructions (example: MPX) don't support RIP relative addressing.
if (operand->Info.Memory.IsRipRel && !!(Instrux->Attributes & ND_FLAG_NO_RIP_REL))
{
return ND_STATUS_RIP_REL_ADDRESSING_NOT_SUPPORTED;
}
}
else
{
@ -2728,7 +2734,12 @@ memory:
operand->Type = ND_OP_REG;
operand->Info.Register.Type = ND_REG_SSE;
operand->Info.Register.Size = (ND_REG_SIZE)(size < ND_SIZE_128BIT ? ND_SIZE_128BIT : size);
operand->Info.Register.Reg = ((Instrux->SseImmediate >> 4) & 0xF) | ((Instrux->SseImmediate & 8) << 1);
operand->Info.Register.Reg = (Instrux->SseImmediate >> 4) & 0xF;
if (Instrux->DefCode != ND_CODE_64)
{
operand->Info.Register.Reg &= 0x7;
}
Offset = Instrux->Length;
break;
@ -3637,6 +3648,7 @@ NdGetEffectiveOpMode(
break;
case ND_CODE_64:
Instrux->EfOpMode = (width || f64 || (d64 && !has66)) ? ND_OPSZ_64 : (has66 ? ND_OPSZ_16 : ND_OPSZ_32);
Instrux->AddrMode = !!(Instrux->Attributes & ND_FLAG_I67) ? ND_ADDR_64 : Instrux->AddrMode;
break;
default:
return ND_STATUS_INVALID_INSTRUX;
@ -3692,7 +3704,8 @@ NdValidateInstruction(
}
// VSIB instructions have a restriction: the same vector register can't be used by more than one operand.
if (ND_HAS_VSIB(Instrux))
// The exception is SCATTER*, which can use the VSIB reg as two sources.
if (ND_HAS_VSIB(Instrux) && Instrux->Category != ND_CAT_SCATTER)
{
uint8_t usedVects[32] = { 0 };
@ -3769,8 +3782,10 @@ NdValidateInstruction(
}
}
// EVEX.b must be 0 if SAE/ER is not used.
if (Instrux->Exs.bm && (Instrux->ModRm.mod == 3) && !ND_SAE_SUPPORT(Instrux) && !ND_ER_SUPPORT(Instrux))
// EVEX.b must be 0 if SAE/ER is not used, but can be ignored if the ignore embedded rounding flag is set.
if (Instrux->Exs.bm && (Instrux->ModRm.mod == 3) &&
!ND_SAE_SUPPORT(Instrux) && !ND_ER_SUPPORT(Instrux) &&
!(Instrux->Attributes & ND_FLAG_IER))
{
return ND_STATUS_ER_SAE_NOT_SUPPORTED;
}
@ -4483,7 +4498,7 @@ NdToText(
case ND_OP_IMM:
{
switch (pOp->RawSize)
switch (pOp->Size)
{
case 1:
status = NdSprintf(temp, sizeof(temp), "0x%02x", (uint8_t)pOp->Info.Immediate.Imm);
@ -4563,8 +4578,10 @@ NdToText(
case ND_OP_MEM:
{
// Prepend the size.
switch (pOp->Size)
// Prepend the size. For VSIB addressing, store the VSIB element size, not the total accessed size.
ND_OPERAND_SIZE size = pOp->Info.Memory.IsVsib ? pOp->Info.Memory.Vsib.ElemSize : pOp->Size;
switch (size)
{
case 1:
res = nd_strcat_s(Buffer, BufferSize, "byte ptr ");

8173
bddisasm/include/instructions.h
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File diff suppressed because it is too large Load Diff

218
bddisasm/include/mnemonics.h
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@ -1,7 +1,7 @@
#ifndef _MNEMONICS_H_
#define _MNEMONICS_H_
const char *gMnemonics[1561] =
const char *gMnemonics[1567] =
{
"AAA", "AAD", "AAM", "AAS", "ADC", "ADCX", "ADD", "ADDPD", "ADDPS",
"ADDSD", "ADDSS", "ADDSUBPD", "ADDSUBPS", "ADOX", "AESDEC", "AESDECLAST",
@ -40,109 +40,109 @@ const char *gMnemonics[1561] =
"FSIN", "FSINCOS", "FSQRT", "FST", "FSTDW", "FSTP", "FSTPNCE",
"FSTSG", "FSUB", "FSUBP", "FSUBR", "FSUBRP", "FTST", "FUCOM",
"FUCOMI", "FUCOMIP", "FUCOMP", "FUCOMPP", "FXAM", "FXCH", "FXRSTOR",
"FXSAVE", "FXTRACT", "FYL2X", "FYL2XP1", "GETSEC", "GF2P8AFFINEINVQB",
"GF2P8AFFINEQB", "GF2P8MULB", "HADDPD", "HADDPS", "HLT", "HSUBPD",
"HSUBPS", "IDIV", "IMUL", "IN", "INC", "INCSSPD", "INCSSPQ",
"INSB", "INSD", "INSERTPS", "INSERTQ", "INSW", "INT", "INT1",
"INT3", "INTO", "INVD", "INVEPT", "INVLPG", "INVLPGA", "INVLPGB",
"INVPCID", "INVVPID", "IRETD", "IRETQ", "IRETW", "JBE", "JC",
"JCXZ", "JECXZ", "JL", "JLE", "JMP", "JMPE", "JMPF", "JNBE",
"JNC", "JNL", "JNLE", "JNO", "JNP", "JNS", "JNZ", "JO", "JP",
"JRCXZ", "JS", "JZ", "KADDB", "KADDD", "KADDQ", "KADDW", "KANDB",
"KANDD", "KANDNB", "KANDND", "KANDNQ", "KANDNW", "KANDQ", "KANDW",
"KMERGE2L1H", "KMERGE2L1L", "KMOVB", "KMOVD", "KMOVQ", "KMOVW",
"KNOTB", "KNOTD", "KNOTQ", "KNOTW", "KORB", "KORD", "KORQ", "KORTESTB",
"KORTESTD", "KORTESTQ", "KORTESTW", "KORW", "KSHIFTLB", "KSHIFTLD",
"KSHIFTLQ", "KSHIFTLW", "KSHIFTRB", "KSHIFTRD", "KSHIFTRQ", "KSHIFTRW",
"KTESTB", "KTESTD", "KTESTQ", "KTESTW", "KUNPCKBW", "KUNPCKDQ",
"KUNPCKWD", "KXNORB", "KXNORD", "KXNORQ", "KXNORW", "KXORB",
"KXORD", "KXORQ", "KXORW", "LAHF", "LAR", "LDDQU", "LDMXCSR",
"LDS", "LDTILECFG", "LEA", "LEAVE", "LES", "LFENCE", "LFS", "LGDT",
"LGS", "LIDT", "LLDT", "LLWPCB", "LMSW", "LOADALL", "LOADALLD",
"FXRSTOR64", "FXSAVE", "FXSAVE64", "FXTRACT", "FYL2X", "FYL2XP1",
"GETSEC", "GF2P8AFFINEINVQB", "GF2P8AFFINEQB", "GF2P8MULB", "HADDPD",
"HADDPS", "HLT", "HSUBPD", "HSUBPS", "IDIV", "IMUL", "IN", "INC",
"INCSSPD", "INCSSPQ", "INSB", "INSD", "INSERTPS", "INSERTQ",
"INSW", "INT", "INT1", "INT3", "INTO", "INVD", "INVEPT", "INVLPG",
"INVLPGA", "INVLPGB", "INVPCID", "INVVPID", "IRETD", "IRETQ",
"IRETW", "JBE", "JC", "JCXZ", "JECXZ", "JL", "JLE", "JMP", "JMPE",
"JMPF", "JNBE", "JNC", "JNL", "JNLE", "JNO", "JNP", "JNS", "JNZ",
"JO", "JP", "JRCXZ", "JS", "JZ", "KADDB", "KADDD", "KADDQ", "KADDW",
"KANDB", "KANDD", "KANDNB", "KANDND", "KANDNQ", "KANDNW", "KANDQ",
"KANDW", "KMERGE2L1H", "KMERGE2L1L", "KMOVB", "KMOVD", "KMOVQ",
"KMOVW", "KNOTB", "KNOTD", "KNOTQ", "KNOTW", "KORB", "KORD",
"KORQ", "KORTESTB", "KORTESTD", "KORTESTQ", "KORTESTW", "KORW",
"KSHIFTLB", "KSHIFTLD", "KSHIFTLQ", "KSHIFTLW", "KSHIFTRB", "KSHIFTRD",
"KSHIFTRQ", "KSHIFTRW", "KTESTB", "KTESTD", "KTESTQ", "KTESTW",
"KUNPCKBW", "KUNPCKDQ", "KUNPCKWD", "KXNORB", "KXNORD", "KXNORQ",
"KXNORW", "KXORB", "KXORD", "KXORQ", "KXORW", "LAHF", "LAR",
"LDDQU", "LDMXCSR", "LDS", "LDTILECFG", "LEA", "LEAVE", "LES",
"LFENCE", "LFS", "LGDT", "LGS", "LIDT", "LLDT", "LLWPCB", "LMSW",
"LODSB", "LODSD", "LODSQ", "LODSW", "LOOP", "LOOPNZ", "LOOPZ",
"LSL", "LSS", "LTR", "LWPINS", "LWPVAL", "LZCNT", "MASKMOVDQU",
"MASKMOVQ", "MAXPD", "MAXPS", "MAXSD", "MAXSS", "MCOMMIT", "MFENCE",
"MINPD", "MINPS", "MINSD", "MINSS", "MONITOR", "MONITORX", "MONTMUL",
"MOV", "MOVAPD", "MOVAPS", "MOVBE", "MOVD", "MOVDDUP", "MOVDIR64B",
"MOVDIRI", "MOVDQ2Q", "MOVDQA", "MOVDQU", "MOVHPD", "MOVHPS",
"MOVLHPS", "MOVLPD", "MOVLPS", "MOVMSKPD", "MOVMSKPS", "MOVNTDQ",
"MOVNTDQA", "MOVNTI", "MOVNTPD", "MOVNTPS", "MOVNTQ", "MOVNTSD",
"MOVNTSS", "MOVQ", "MOVQ2DQ", "MOVSB", "MOVSD", "MOVSHDUP", "MOVSLDUP",
"MOVSQ", "MOVSS", "MOVSW", "MOVSX", "MOVSXD", "MOVUPD", "MOVUPS",
"MOVZX", "MPSADBW", "MUL", "MULPD", "MULPS", "MULSD", "MULSS",
"MULX", "MWAIT", "MWAITX", "NEG", "NOP", "NOT", "OR", "ORPD",
"ORPS", "OUT", "OUTSB", "OUTSD", "OUTSW", "PABSB", "PABSD", "PABSW",
"PACKSSDW", "PACKSSWB", "PACKUSDW", "PACKUSWB", "PADDB", "PADDD",
"PADDQ", "PADDSB", "PADDSW", "PADDUSB", "PADDUSW", "PADDW", "PALIGNR",
"PAND", "PANDN", "PAUSE", "PAVGB", "PAVGUSB", "PAVGW", "PBLENDVB",
"PBLENDW", "PCLMULQDQ", "PCMPEQB", "PCMPEQD", "PCMPEQQ", "PCMPEQW",
"PCMPESTRI", "PCMPESTRM", "PCMPGTB", "PCMPGTD", "PCMPGTQ", "PCMPGTW",
"PCMPISTRI", "PCMPISTRM", "PCOMMIT", "PCONFIG", "PDEP", "PEXT",
"PEXTRB", "PEXTRD", "PEXTRQ", "PEXTRW", "PF2ID", "PF2IW", "PFACC",
"PFADD", "PFCMPEQ", "PFCMPGE", "PFCMPGT", "PFMAX", "PFMIN", "PFMUL",
"PFNACC", "PFPNACC", "PFRCPIT1", "PFRCPIT2", "PFRCPV", "PFRSQIT1",
"PFRSQRT", "PFRSQRTV", "PFSUB", "PFSUBR", "PHADDD", "PHADDSW",
"PHADDW", "PHMINPOSUW", "PHSUBD", "PHSUBSW", "PHSUBW", "PI2FD",
"PI2FW", "PINSRB", "PINSRD", "PINSRQ", "PINSRW", "PMADDUBSW",
"PMADDWD", "PMAXSB", "PMAXSD", "PMAXSW", "PMAXUB", "PMAXUD",
"PMAXUW", "PMINSB", "PMINSD", "PMINSW", "PMINUB", "PMINUD", "PMINUW",
"PMOVMSKB", "PMOVSXBD", "PMOVSXBQ", "PMOVSXBW", "PMOVSXDQ", "PMOVSXWD",
"PMOVSXWQ", "PMOVZXBD", "PMOVZXBQ", "PMOVZXBW", "PMOVZXDQ", "PMOVZXWD",
"PMOVZXWQ", "PMULDQ", "PMULHRSW", "PMULHRW", "PMULHUW", "PMULHW",
"PMULLD", "PMULLW", "PMULUDQ", "POP", "POPA", "POPCNT", "POPFD",
"POPFQ", "POPFW", "POR", "PREFETCH", "PREFETCHE", "PREFETCHM",
"PREFETCHNTA", "PREFETCHT0", "PREFETCHT1", "PREFETCHT2", "PREFETCHW",
"PREFETCHWT1", "PSADBW", "PSHUFB", "PSHUFD", "PSHUFHW", "PSHUFLW",
"PSHUFW", "PSIGNB", "PSIGND", "PSIGNW", "PSLLD", "PSLLDQ", "PSLLQ",
"PSLLW", "PSMASH", "PSRAD", "PSRAW", "PSRLD", "PSRLDQ", "PSRLQ",
"PSRLW", "PSUBB", "PSUBD", "PSUBQ", "PSUBSB", "PSUBSW", "PSUBUSB",
"PSUBUSW", "PSUBW", "PSWAPD", "PTEST", "PTWRITE", "PUNPCKHBW",
"PUNPCKHDQ", "PUNPCKHQDQ", "PUNPCKHWD", "PUNPCKLBW", "PUNPCKLDQ",
"PUNPCKLQDQ", "PUNPCKLWD", "PUSH", "PUSHA", "PUSHFD", "PUSHFQ",
"PUSHFW", "PVALIDATE", "PXOR", "RCL", "RCPPS", "RCPSS", "RCR",
"RDFSBASE", "RDGSBASE", "RDMSR", "RDPID", "RDPKRU", "RDPMC",
"RDPRU", "RDRAND", "RDSEED", "RDSHR", "RDSSPD", "RDSSPQ", "RDTSC",
"RDTSCP", "RETF", "RETN", "RMPADJUST", "RMPUPDATE", "ROL", "ROR",
"RORX", "ROUNDPD", "ROUNDPS", "ROUNDSD", "ROUNDSS", "RSDC", "RSLDT",
"RSM", "RSQRTPS", "RSQRTSS", "RSTORSSP", "RSTS", "SAHF", "SAL",
"SALC", "SAR", "SARX", "SAVEPREVSSP", "SBB", "SCASB", "SCASD",
"SCASQ", "SCASW", "SERIALIZE", "SETBE", "SETC", "SETL", "SETLE",
"SETNB", "SETNC", "SETNL", "SETNLE", "SETNO", "SETNP", "SETNS",
"SETNZ", "SETO", "SETP", "SETS", "SETSSBSY", "SETZ", "SFENCE",
"SGDT", "SHA1MSG1", "SHA1MSG2", "SHA1NEXTE", "SHA1RNDS4", "SHA256MSG1",
"SHA256MSG2", "SHA256RNDS2", "SHL", "SHLD", "SHLX", "SHR", "SHRD",
"SHRX", "SHUFPD", "SHUFPS", "SIDT", "SKINIT", "SLDT", "SLWPCB",
"SMINT", "SMSW", "SPFLT", "SQRTPD", "SQRTPS", "SQRTSD", "SQRTSS",
"STAC", "STC", "STD", "STGI", "STI", "STMXCSR", "STOSB", "STOSD",
"STOSQ", "STOSW", "STR", "STTILECFG", "SUB", "SUBPD", "SUBPS",
"SUBSD", "SUBSS", "SVDC", "SVLDT", "SVTS", "SWAPGS", "SYSCALL",
"SYSENTER", "SYSEXIT", "SYSRET", "T1MSKC", "TDPBF16PS", "TDPBSSD",
"TDPBSUD", "TDPBUSD", "TDPBUUD", "TEST", "TILELOADD", "TILELOADDT1",
"TILERELEASE", "TILESTORED", "TILEZERO", "TLBSYNC", "TPAUSE",
"TZCNT", "TZMSK", "UCOMISD", "UCOMISS", "UD0", "UD1", "UD2",
"UMONITOR", "UMWAIT", "UNPCKHPD", "UNPCKHPS", "UNPCKLPD", "UNPCKLPS",
"V4FMADDPS", "V4FMADDSS", "V4FNMADDPS", "V4FNMADDSS", "VADDPD",
"VADDPS", "VADDSD", "VADDSS", "VADDSUBPD", "VADDSUBPS", "VAESDEC",
"VAESDECLAST", "VAESENC", "VAESENCLAST", "VAESIMC", "VAESKEYGENASSIST",
"VALIGND", "VALIGNQ", "VANDNPD", "VANDNPS", "VANDPD", "VANDPS",
"VBLENDMPD", "VBLENDMPS", "VBLENDPD", "VBLENDPS", "VBLENDVPD",
"VBLENDVPS", "VBROADCASTF128", "VBROADCASTF32X2", "VBROADCASTF32X4",
"VBROADCASTF32X8", "VBROADCASTF64X2", "VBROADCASTF64X4", "VBROADCASTI128",
"VBROADCASTI32X2", "VBROADCASTI32X4", "VBROADCASTI32X8", "VBROADCASTI64X2",
"VBROADCASTI64X4", "VBROADCASTSD", "VBROADCASTSS", "VCMPPD",
"VCMPPS", "VCMPSD", "VCMPSS", "VCOMISD", "VCOMISS", "VCOMPRESSPD",
"VCOMPRESSPS", "VCVTDQ2PD", "VCVTDQ2PS", "VCVTNE2PS2BF16", "VCVTNEPS2BF16",
"VCVTPD2DQ", "VCVTPD2PS", "VCVTPD2QQ", "VCVTPD2UDQ", "VCVTPD2UQQ",
"VCVTPH2PS", "VCVTPS2DQ", "VCVTPS2PD", "VCVTPS2PH", "VCVTPS2QQ",
"VCVTPS2UDQ", "VCVTPS2UQQ", "VCVTQQ2PD", "VCVTQQ2PS", "VCVTSD2SI",
"VCVTSD2SS", "VCVTSD2USI", "VCVTSI2SD", "VCVTSI2SS", "VCVTSS2SD",
"VCVTSS2SI", "VCVTSS2USI", "VCVTTPD2DQ", "VCVTTPD2QQ", "VCVTTPD2UDQ",
"VCVTTPD2UQQ", "VCVTTPS2DQ", "VCVTTPS2QQ", "VCVTTPS2UDQ", "VCVTTPS2UQQ",
"VCVTTSD2SI", "VCVTTSD2USI", "VCVTTSS2SI", "VCVTTSS2USI", "VCVTUDQ2PD",
"VCVTUDQ2PS", "VCVTUQQ2PD", "VCVTUQQ2PS", "VCVTUSI2SD", "VCVTUSI2SS",
"VDBPSADBW", "VDIVPD", "VDIVPS", "VDIVSD", "VDIVSS", "VDPBF16PS",
"VDPPD", "VDPPS", "VERR", "VERW", "VEXP2PD", "VEXP2PS", "VEXPANDPD",
"VEXPANDPS", "VEXTRACTF128", "VEXTRACTF32X4", "VEXTRACTF32X8",
"MOVDIRI", "MOVDQ2Q", "MOVDQA", "MOVDQU", "MOVHLPS", "MOVHPD",
"MOVHPS", "MOVLHPS", "MOVLPD", "MOVLPS", "MOVMSKPD", "MOVMSKPS",
"MOVNTDQ", "MOVNTDQA", "MOVNTI", "MOVNTPD", "MOVNTPS", "MOVNTQ",
"MOVNTSD", "MOVNTSS", "MOVQ", "MOVQ2DQ", "MOVSB", "MOVSD", "MOVSHDUP",
"MOVSLDUP", "MOVSQ", "MOVSS", "MOVSW", "MOVSX", "MOVSXD", "MOVUPD",
"MOVUPS", "MOVZX", "MPSADBW", "MUL", "MULPD", "MULPS", "MULSD",
"MULSS", "MULX", "MWAIT", "MWAITX", "NEG", "NOP", "NOT", "OR",
"ORPD", "ORPS", "OUT", "OUTSB", "OUTSD", "OUTSW", "PABSB", "PABSD",
"PABSW", "PACKSSDW", "PACKSSWB", "PACKUSDW", "PACKUSWB", "PADDB",
"PADDD", "PADDQ", "PADDSB", "PADDSW", "PADDUSB", "PADDUSW", "PADDW",
"PALIGNR", "PAND", "PANDN", "PAUSE", "PAVGB", "PAVGUSB", "PAVGW",
"PBLENDVB", "PBLENDW", "PCLMULQDQ", "PCMPEQB", "PCMPEQD", "PCMPEQQ",
"PCMPEQW", "PCMPESTRI", "PCMPESTRM", "PCMPGTB", "PCMPGTD", "PCMPGTQ",
"PCMPGTW", "PCMPISTRI", "PCMPISTRM", "PCOMMIT", "PCONFIG", "PDEP",
"PEXT", "PEXTRB", "PEXTRD", "PEXTRQ", "PEXTRW", "PF2ID", "PF2IW",
"PFACC", "PFADD", "PFCMPEQ", "PFCMPGE", "PFCMPGT", "PFMAX", "PFMIN",
"PFMUL", "PFNACC", "PFPNACC", "PFRCP", "PFRCPIT1", "PFRCPIT2",
"PFRCPV", "PFRSQIT1", "PFRSQRT", "PFRSQRTV", "PFSUB", "PFSUBR",
"PHADDD", "PHADDSW", "PHADDW", "PHMINPOSUW", "PHSUBD", "PHSUBSW",
"PHSUBW", "PI2FD", "PI2FW", "PINSRB", "PINSRD", "PINSRQ", "PINSRW",
"PMADDUBSW", "PMADDWD", "PMAXSB", "PMAXSD", "PMAXSW", "PMAXUB",
"PMAXUD", "PMAXUW", "PMINSB", "PMINSD", "PMINSW", "PMINUB", "PMINUD",
"PMINUW", "PMOVMSKB", "PMOVSXBD", "PMOVSXBQ", "PMOVSXBW", "PMOVSXDQ",
"PMOVSXWD", "PMOVSXWQ", "PMOVZXBD", "PMOVZXBQ", "PMOVZXBW", "PMOVZXDQ",
"PMOVZXWD", "PMOVZXWQ", "PMULDQ", "PMULHRSW", "PMULHRW", "PMULHUW",
"PMULHW", "PMULLD", "PMULLW", "PMULUDQ", "POP", "POPA", "POPAD",
"POPCNT", "POPFD", "POPFQ", "POPFW", "POR", "PREFETCH", "PREFETCHE",
"PREFETCHM", "PREFETCHNTA", "PREFETCHT0", "PREFETCHT1", "PREFETCHT2",
"PREFETCHW", "PREFETCHWT1", "PSADBW", "PSHUFB", "PSHUFD", "PSHUFHW",
"PSHUFLW", "PSHUFW", "PSIGNB", "PSIGND", "PSIGNW", "PSLLD", "PSLLDQ",
"PSLLQ", "PSLLW", "PSMASH", "PSRAD", "PSRAW", "PSRLD", "PSRLDQ",
"PSRLQ", "PSRLW", "PSUBB", "PSUBD", "PSUBQ", "PSUBSB", "PSUBSW",
"PSUBUSB", "PSUBUSW", "PSUBW", "PSWAPD", "PTEST", "PTWRITE",
"PUNPCKHBW", "PUNPCKHDQ", "PUNPCKHQDQ", "PUNPCKHWD", "PUNPCKLBW",
"PUNPCKLDQ", "PUNPCKLQDQ", "PUNPCKLWD", "PUSH", "PUSHA", "PUSHAD",
"PUSHFD", "PUSHFQ", "PUSHFW", "PVALIDATE", "PXOR", "RCL", "RCPPS",
"RCPSS", "RCR", "RDFSBASE", "RDGSBASE", "RDMSR", "RDPID", "RDPKRU",
"RDPMC", "RDPRU", "RDRAND", "RDSEED", "RDSHR", "RDSSPD", "RDSSPQ",
"RDTSC", "RDTSCP", "RETF", "RETN", "RMPADJUST", "RMPUPDATE",
"ROL", "ROR", "RORX", "ROUNDPD", "ROUNDPS", "ROUNDSD", "ROUNDSS",
"RSDC", "RSLDT", "RSM", "RSQRTPS", "RSQRTSS", "RSTORSSP", "RSTS",
"SAHF", "SAL", "SALC", "SAR", "SARX", "SAVEPREVSSP", "SBB", "SCASB",
"SCASD", "SCASQ", "SCASW", "SERIALIZE", "SETBE", "SETC", "SETL",
"SETLE", "SETNBE", "SETNC", "SETNL", "SETNLE", "SETNO", "SETNP",
"SETNS", "SETNZ", "SETO", "SETP", "SETS", "SETSSBSY", "SETZ",
"SFENCE", "SGDT", "SHA1MSG1", "SHA1MSG2", "SHA1NEXTE", "SHA1RNDS4",
"SHA256MSG1", "SHA256MSG2", "SHA256RNDS2", "SHL", "SHLD", "SHLX",
"SHR", "SHRD", "SHRX", "SHUFPD", "SHUFPS", "SIDT", "SKINIT",
"SLDT", "SLWPCB", "SMINT", "SMSW", "SPFLT", "SQRTPD", "SQRTPS",
"SQRTSD", "SQRTSS", "STAC", "STC", "STD", "STGI", "STI", "STMXCSR",
"STOSB", "STOSD", "STOSQ", "STOSW", "STR", "STTILECFG", "SUB",
"SUBPD", "SUBPS", "SUBSD", "SUBSS", "SVDC", "SVLDT", "SVTS",
"SWAPGS", "SYSCALL", "SYSENTER", "SYSEXIT", "SYSRET", "T1MSKC",
"TDPBF16PS", "TDPBSSD", "TDPBSUD", "TDPBUSD", "TDPBUUD", "TEST",
"TILELOADD", "TILELOADDT1", "TILERELEASE", "TILESTORED", "TILEZERO",
"TLBSYNC", "TPAUSE", "TZCNT", "TZMSK", "UCOMISD", "UCOMISS",
"UD0", "UD1", "UD2", "UMONITOR", "UMWAIT", "UNPCKHPD", "UNPCKHPS",
"UNPCKLPD", "UNPCKLPS", "V4FMADDPS", "V4FMADDSS", "V4FNMADDPS",
"V4FNMADDSS", "VADDPD", "VADDPS", "VADDSD", "VADDSS", "VADDSUBPD",
"VADDSUBPS", "VAESDEC", "VAESDECLAST", "VAESENC", "VAESENCLAST",
"VAESIMC", "VAESKEYGENASSIST", "VALIGND", "VALIGNQ", "VANDNPD",
"VANDNPS", "VANDPD", "VANDPS", "VBLENDMPD", "VBLENDMPS", "VBLENDPD",
"VBLENDPS", "VBLENDVPD", "VBLENDVPS", "VBROADCASTF128", "VBROADCASTF32X2",
"VBROADCASTF32X4", "VBROADCASTF32X8", "VBROADCASTF64X2", "VBROADCASTF64X4",
"VBROADCASTI128", "VBROADCASTI32X2", "VBROADCASTI32X4", "VBROADCASTI32X8",
"VBROADCASTI64X2", "VBROADCASTI64X4", "VBROADCASTSD", "VBROADCASTSS",
"VCMPPD", "VCMPPS", "VCMPSD", "VCMPSS", "VCOMISD", "VCOMISS",
"VCOMPRESSPD", "VCOMPRESSPS", "VCVTDQ2PD", "VCVTDQ2PS", "VCVTNE2PS2BF16",
"VCVTNEPS2BF16", "VCVTPD2DQ", "VCVTPD2PS", "VCVTPD2QQ", "VCVTPD2UDQ",
"VCVTPD2UQQ", "VCVTPH2PS", "VCVTPS2DQ", "VCVTPS2PD", "VCVTPS2PH",
"VCVTPS2QQ", "VCVTPS2UDQ", "VCVTPS2UQQ", "VCVTQQ2PD", "VCVTQQ2PS",
"VCVTSD2SI", "VCVTSD2SS", "VCVTSD2USI", "VCVTSI2SD", "VCVTSI2SS",
"VCVTSS2SD", "VCVTSS2SI", "VCVTSS2USI", "VCVTTPD2DQ", "VCVTTPD2QQ",
"VCVTTPD2UDQ", "VCVTTPD2UQQ", "VCVTTPS2DQ", "VCVTTPS2QQ", "VCVTTPS2UDQ",
"VCVTTPS2UQQ", "VCVTTSD2SI", "VCVTTSD2USI", "VCVTTSS2SI", "VCVTTSS2USI",
"VCVTUDQ2PD", "VCVTUDQ2PS", "VCVTUQQ2PD", "VCVTUQQ2PS", "VCVTUSI2SD",
"VCVTUSI2SS", "VDBPSADBW", "VDIVPD", "VDIVPS", "VDIVSD", "VDIVSS",
"VDPBF16PS", "VDPPD", "VDPPS", "VERR", "VERW", "VEXP2PD", "VEXP2PS",
"VEXPANDPD", "VEXPANDPS", "VEXTRACTF128", "VEXTRACTF32X4", "VEXTRACTF32X8",
"VEXTRACTF64X2", "VEXTRACTF64X4", "VEXTRACTI128", "VEXTRACTI32X4",
"VEXTRACTI32X8", "VEXTRACTI64X2", "VEXTRACTI64X4", "VEXTRACTPS",
"VFIXUPIMMPD", "VFIXUPIMMPS", "VFIXUPIMMSD", "VFIXUPIMMSS", "VFMADD132PD",
@ -202,7 +202,7 @@ const char *gMnemonics[1561] =
"VPCOMW", "VPCONFLICTD", "VPCONFLICTQ", "VPDPBUSD", "VPDPBUSDS",
"VPDPWSSD", "VPDPWSSDS", "VPERM2F128", "VPERM2I128", "VPERMB",
"VPERMD", "VPERMI2B", "VPERMI2D", "VPERMI2PD", "VPERMI2PS", "VPERMI2Q",
"VPERMI2W", "VPERMILPD", "VPERMILPS", "VPERMILzz2PD", "VPERMILzz2PS",
"VPERMI2W", "VPERMIL2PD", "VPERMIL2PS", "VPERMILPD", "VPERMILPS",
"VPERMPD", "VPERMPS", "VPERMQ", "VPERMT2B", "VPERMT2D", "VPERMT2PD",
"VPERMT2PS", "VPERMT2Q", "VPERMT2W", "VPERMW", "VPEXPANDB", "VPEXPANDD",
"VPEXPANDQ", "VPEXPANDW", "VPEXTRB", "VPEXTRD", "VPEXTRQ", "VPEXTRW",
@ -232,15 +232,15 @@ const char *gMnemonics[1561] =
"VPRORD", "VPRORQ", "VPRORVD", "VPRORVQ", "VPROTB", "VPROTD",
"VPROTQ", "VPROTW", "VPSADBW", "VPSCATTERDD", "VPSCATTERDQ",
"VPSCATTERQD", "VPSCATTERQQ", "VPSHAB", "VPSHAD", "VPSHAQ", "VPSHAW",
"VPSHLB", "VPSHLDD", "VPSHLDQ", "VPSHLDVD", "VPSHLDVQ", "VPSHLDVW",
"VPSHLDW", "VPSHLQ", "VPSHRDD", "VPSHRDQ", "VPSHRDVD", "VPSHRDVQ",
"VPSHRDVW", "VPSHRDW", "VPSHUFB", "VPSHUFBITQMB", "VPSHUFD",
"VPSHUFHW", "VPSHUFLW", "VPSIGNB", "VPSIGND", "VPSIGNW", "VPSLLD",
"VPSLLDQ", "VPSLLQ", "VPSLLVD", "VPSLLVQ", "VPSLLVW", "VPSLLW",
"VPSRAD", "VPSRAQ", "VPSRAVD", "VPSRAVQ", "VPSRAVW", "VPSRAW",
"VPSRLD", "VPSRLDQ", "VPSRLQ", "VPSRLVD", "VPSRLVQ", "VPSRLVW",
"VPSRLW", "VPSUBB", "VPSUBD", "VPSUBQ", "VPSUBSB", "VPSUBSW",
"VPSUBUSB", "VPSUBUSW", "VPSUBW", "VPTERNLOGD", "VPTERNLOGQ",
"VPSHLB", "VPSHLD", "VPSHLDD", "VPSHLDQ", "VPSHLDVD", "VPSHLDVQ",
"VPSHLDVW", "VPSHLDW", "VPSHLQ", "VPSHLW", "VPSHRDD", "VPSHRDQ",
"VPSHRDVD", "VPSHRDVQ", "VPSHRDVW", "VPSHRDW", "VPSHUFB", "VPSHUFBITQMB",
"VPSHUFD", "VPSHUFHW", "VPSHUFLW", "VPSIGNB", "VPSIGND", "VPSIGNW",
"VPSLLD", "VPSLLDQ", "VPSLLQ", "VPSLLVD", "VPSLLVQ", "VPSLLVW",
"VPSLLW", "VPSRAD", "VPSRAQ", "VPSRAVD", "VPSRAVQ", "VPSRAVW",
"VPSRAW", "VPSRLD", "VPSRLDQ", "VPSRLQ", "VPSRLVD", "VPSRLVQ",
"VPSRLVW", "VPSRLW", "VPSUBB", "VPSUBD", "VPSUBQ", "VPSUBSB",
"VPSUBSW", "VPSUBUSB", "VPSUBUSW", "VPSUBW", "VPTERNLOGD", "VPTERNLOGQ",
"VPTEST", "VPTESTMB", "VPTESTMD", "VPTESTMQ", "VPTESTMW", "VPTESTNMB",
"VPTESTNMD", "VPTESTNMQ", "VPTESTNMW", "VPUNPCKHBW", "VPUNPCKHDQ",
"VPUNPCKHQDQ", "VPUNPCKHWD", "VPUNPCKLBW", "VPUNPCKLDQ", "VPUNPCKLQDQ",

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bddisasm/include/table_evex.h
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bddisasm/include/table_root.h
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bddisasm/include/table_vex.h
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158
bddisasm/include/table_xop.h
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@ -330,13 +330,13 @@ const ND_TABLE_INSTRUCTION gXopTable_root_09_01_06_leaf =
const ND_TABLE_INSTRUCTION gXopTable_root_09_01_07_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[1293]
(const void *)&gInstructions[1295]
};
const ND_TABLE_INSTRUCTION gXopTable_root_09_01_04_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[1315]
(const void *)&gInstructions[1317]
};
const ND_TABLE_MODRM_REG gXopTable_root_09_01_modrmreg =
@ -384,13 +384,13 @@ const ND_TABLE_MODRM_REG gXopTable_root_09_02_modrmreg =
const ND_TABLE_INSTRUCTION gXopTable_root_09_12_reg_00_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[565]
(const void *)&gInstructions[567]
};
const ND_TABLE_INSTRUCTION gXopTable_root_09_12_reg_01_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[1245]
(const void *)&gInstructions[1247]
};
const ND_TABLE_MODRM_REG gXopTable_root_09_12_reg_modrmreg =
@ -420,127 +420,127 @@ const ND_TABLE_MODRM_MOD gXopTable_root_09_12_modrmmod =
const ND_TABLE_INSTRUCTION gXopTable_root_09_81_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[1666]
(const void *)&gInstructions[1668]
};
const ND_TABLE_INSTRUCTION gXopTable_root_09_80_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[1667]
(const void *)&gInstructions[1669]
};
const ND_TABLE_INSTRUCTION gXopTable_root_09_83_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[1668]
(const void *)&gInstructions[1670]
};
const ND_TABLE_INSTRUCTION gXopTable_root_09_82_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[1669]
(const void *)&gInstructions[1671]
};
const ND_TABLE_INSTRUCTION gXopTable_root_09_c2_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2054]
(const void *)&gInstructions[2057]
};
const ND_TABLE_INSTRUCTION gXopTable_root_09_c3_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2055]
(const void *)&gInstructions[2058]
};
const ND_TABLE_INSTRUCTION gXopTable_root_09_c1_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2056]
(const void *)&gInstructions[2059]
};
const ND_TABLE_INSTRUCTION gXopTable_root_09_cb_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2058]
(const void *)&gInstructions[2061]
};
const ND_TABLE_INSTRUCTION gXopTable_root_09_d2_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2060]
(const void *)&gInstructions[2063]
};
const ND_TABLE_INSTRUCTION gXopTable_root_09_d3_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2061]
(const void *)&gInstructions[2064]
};
const ND_TABLE_INSTRUCTION gXopTable_root_09_d1_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2062]
(const void *)&gInstructions[2065]
};
const ND_TABLE_INSTRUCTION gXopTable_root_09_db_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2063]
(const void *)&gInstructions[2066]
};
const ND_TABLE_INSTRUCTION gXopTable_root_09_d6_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2064]
(const void *)&gInstructions[2067]
};
const ND_TABLE_INSTRUCTION gXopTable_root_09_d7_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2065]
(const void *)&gInstructions[2068]
};
const ND_TABLE_INSTRUCTION gXopTable_root_09_c6_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2067]
(const void *)&gInstructions[2070]
};
const ND_TABLE_INSTRUCTION gXopTable_root_09_c7_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2068]
(const void *)&gInstructions[2071]
};
const ND_TABLE_INSTRUCTION gXopTable_root_09_e1_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2070]
(const void *)&gInstructions[2073]
};
const ND_TABLE_INSTRUCTION gXopTable_root_09_e3_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2072]
(const void *)&gInstructions[2075]
};
const ND_TABLE_INSTRUCTION gXopTable_root_09_e2_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2075]
(const void *)&gInstructions[2078]
};
const ND_TABLE_INSTRUCTION gXopTable_root_09_90_00_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2237]
(const void *)&gInstructions[2240]
};
const ND_TABLE_INSTRUCTION gXopTable_root_09_90_01_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2238]
(const void *)&gInstructions[2241]
};
const ND_TABLE_VEX_W gXopTable_root_09_90_w =
@ -555,13 +555,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_90_w =
const ND_TABLE_INSTRUCTION gXopTable_root_09_92_00_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2240]
(const void *)&gInstructions[2243]
};
const ND_TABLE_INSTRUCTION gXopTable_root_09_92_01_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2241]
(const void *)&gInstructions[2244]
};
const ND_TABLE_VEX_W gXopTable_root_09_92_w =
@ -576,13 +576,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_92_w =
const ND_TABLE_INSTRUCTION gXopTable_root_09_93_00_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2243]
(const void *)&gInstructions[2246]
};
const ND_TABLE_INSTRUCTION gXopTable_root_09_93_01_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2244]
(const void *)&gInstructions[2247]
};
const ND_TABLE_VEX_W gXopTable_root_09_93_w =
@ -597,13 +597,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_93_w =
const ND_TABLE_INSTRUCTION gXopTable_root_09_91_00_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2246]
(const void *)&gInstructions[2249]
};
const ND_TABLE_INSTRUCTION gXopTable_root_09_91_01_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2247]
(const void *)&gInstructions[2250]
};
const ND_TABLE_VEX_W gXopTable_root_09_91_w =
@ -618,13 +618,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_91_w =
const ND_TABLE_INSTRUCTION gXopTable_root_09_98_00_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2254]
(const void *)&gInstructions[2257]
};
const ND_TABLE_INSTRUCTION gXopTable_root_09_98_01_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2255]
(const void *)&gInstructions[2258]
};
const ND_TABLE_VEX_W gXopTable_root_09_98_w =
@ -639,13 +639,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_98_w =
const ND_TABLE_INSTRUCTION gXopTable_root_09_9a_00_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2256]
(const void *)&gInstructions[2259]
};
const ND_TABLE_INSTRUCTION gXopTable_root_09_9a_01_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2257]
(const void *)&gInstructions[2260]
};
const ND_TABLE_VEX_W gXopTable_root_09_9a_w =
@ -660,13 +660,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_9a_w =
const ND_TABLE_INSTRUCTION gXopTable_root_09_9b_00_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2258]
(const void *)&gInstructions[2261]
};
const ND_TABLE_INSTRUCTION gXopTable_root_09_9b_01_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2259]
(const void *)&gInstructions[2262]
};
const ND_TABLE_VEX_W gXopTable_root_09_9b_w =
@ -681,13 +681,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_9b_w =
const ND_TABLE_INSTRUCTION gXopTable_root_09_99_00_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2260]
(const void *)&gInstructions[2263]
};
const ND_TABLE_INSTRUCTION gXopTable_root_09_99_01_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2261]
(const void *)&gInstructions[2264]
};
const ND_TABLE_VEX_W gXopTable_root_09_99_w =
@ -702,13 +702,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_99_w =
const ND_TABLE_INSTRUCTION gXopTable_root_09_94_00_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2262]
(const void *)&gInstructions[2265]
};
const ND_TABLE_INSTRUCTION gXopTable_root_09_94_01_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2263]
(const void *)&gInstructions[2266]
};
const ND_TABLE_VEX_W gXopTable_root_09_94_w =
@ -720,16 +720,16 @@ const ND_TABLE_VEX_W gXopTable_root_09_94_w =
}
};
const ND_TABLE_INSTRUCTION gXopTable_root_09_95_00_leaf =
const ND_TABLE_INSTRUCTION gXopTable_root_09_95_01_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2264]
(const void *)&gInstructions[2267]
};
const ND_TABLE_INSTRUCTION gXopTable_root_09_95_01_leaf =
const ND_TABLE_INSTRUCTION gXopTable_root_09_95_00_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2265]
(const void *)&gInstructions[2278]
};
const ND_TABLE_VEX_W gXopTable_root_09_95_w =
@ -741,16 +741,16 @@ const ND_TABLE_VEX_W gXopTable_root_09_95_w =
}
};
const ND_TABLE_INSTRUCTION gXopTable_root_09_96_00_leaf =
const ND_TABLE_INSTRUCTION gXopTable_root_09_96_01_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2266]
(const void *)&gInstructions[2268]
};
const ND_TABLE_INSTRUCTION gXopTable_root_09_96_01_leaf =
const ND_TABLE_INSTRUCTION gXopTable_root_09_96_00_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2267]
(const void *)&gInstructions[2269]
};
const ND_TABLE_VEX_W gXopTable_root_09_96_w =
@ -765,13 +765,13 @@ const ND_TABLE_VEX_W gXopTable_root_09_96_w =
const ND_TABLE_INSTRUCTION gXopTable_root_09_97_00_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2274]
(const void *)&gInstructions[2276]
};
const ND_TABLE_INSTRUCTION gXopTable_root_09_97_01_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2275]
(const void *)&gInstructions[2277]
};
const ND_TABLE_VEX_W gXopTable_root_09_97_w =
@ -1049,13 +1049,13 @@ const ND_TABLE_OPCODE gXopTable_root_09_opcode =
const ND_TABLE_INSTRUCTION gXopTable_root_08_a2_00_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[1940]
(const void *)&gInstructions[1943]
};
const ND_TABLE_INSTRUCTION gXopTable_root_08_a2_01_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[1941]
(const void *)&gInstructions[1944]
};
const ND_TABLE_VEX_W gXopTable_root_08_a2_w =
@ -1070,133 +1070,133 @@ const ND_TABLE_VEX_W gXopTable_root_08_a2_w =
const ND_TABLE_INSTRUCTION gXopTable_root_08_cc_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[1970]
(const void *)&gInstructions[1973]
};
const ND_TABLE_INSTRUCTION gXopTable_root_08_ce_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[1971]
(const void *)&gInstructions[1974]
};
const ND_TABLE_INSTRUCTION gXopTable_root_08_cf_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[1976]
(const void *)&gInstructions[1979]
};
const ND_TABLE_INSTRUCTION gXopTable_root_08_ec_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[1977]
(const void *)&gInstructions[1980]
};
const ND_TABLE_INSTRUCTION gXopTable_root_08_ee_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[1978]
(const void *)&gInstructions[1981]
};
const ND_TABLE_INSTRUCTION gXopTable_root_08_ef_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[1979]
(const void *)&gInstructions[1982]
};
const ND_TABLE_INSTRUCTION gXopTable_root_08_ed_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[1980]
(const void *)&gInstructions[1983]
};
const ND_TABLE_INSTRUCTION gXopTable_root_08_cd_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[1981]
(const void *)&gInstructions[1984]
};
const ND_TABLE_INSTRUCTION gXopTable_root_08_9e_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2090]
(const void *)&gInstructions[2093]
};
const ND_TABLE_INSTRUCTION gXopTable_root_08_9f_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2091]
(const void *)&gInstructions[2094]
};
const ND_TABLE_INSTRUCTION gXopTable_root_08_97_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2092]
(const void *)&gInstructions[2095]
};
const ND_TABLE_INSTRUCTION gXopTable_root_08_8e_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2093]
(const void *)&gInstructions[2096]
};
const ND_TABLE_INSTRUCTION gXopTable_root_08_8f_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2094]
(const void *)&gInstructions[2097]
};
const ND_TABLE_INSTRUCTION gXopTable_root_08_87_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2095]
(const void *)&gInstructions[2098]
};
const ND_TABLE_INSTRUCTION gXopTable_root_08_86_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2096]
(const void *)&gInstructions[2099]
};
const ND_TABLE_INSTRUCTION gXopTable_root_08_85_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2097]
(const void *)&gInstructions[2100]
};
const ND_TABLE_INSTRUCTION gXopTable_root_08_96_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2098]
(const void *)&gInstructions[2101]
};
const ND_TABLE_INSTRUCTION gXopTable_root_08_95_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2099]
(const void *)&gInstructions[2102]
};
const ND_TABLE_INSTRUCTION gXopTable_root_08_a6_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2100]
(const void *)&gInstructions[2103]
};
const ND_TABLE_INSTRUCTION gXopTable_root_08_b6_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2101]
(const void *)&gInstructions[2104]
};
const ND_TABLE_INSTRUCTION gXopTable_root_08_a3_00_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2226]
(const void *)&gInstructions[2229]
};
const ND_TABLE_INSTRUCTION gXopTable_root_08_a3_01_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2227]
(const void *)&gInstructions[2230]
};
const ND_TABLE_VEX_W gXopTable_root_08_a3_w =
@ -1211,25 +1211,25 @@ const ND_TABLE_VEX_W gXopTable_root_08_a3_w =
const ND_TABLE_INSTRUCTION gXopTable_root_08_c0_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2236]
(const void *)&gInstructions[2239]
};
const ND_TABLE_INSTRUCTION gXopTable_root_08_c2_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2239]
(const void *)&gInstructions[2242]
};
const ND_TABLE_INSTRUCTION gXopTable_root_08_c3_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2242]
(const void *)&gInstructions[2245]
};
const ND_TABLE_INSTRUCTION gXopTable_root_08_c1_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2245]
(const void *)&gInstructions[2248]
};
const ND_TABLE_OPCODE gXopTable_root_08_opcode =

3
bddisasm/include/tabledefs.h
Unescape View File

@ -413,6 +413,9 @@ typedef enum _ND_OPERAND_TYPE_SPEC
ND_OPT_MEM_SHSP,
ND_OPT_MEM_SHS0,
// Special immediates.
ND_OPT_Im2z,
// Misc CR/XCR/MSR/SYS registers.
ND_OPT_CR_0,
ND_OPT_SYS_IDTR,

20
bddisasm_test/avx/avx2gather_64.result
Unescape View File

@ -1,4 +1,4 @@
0000000000000000 c4e2919294fb00100000 VGATHERDPD xmm2, xmmword ptr [rbx+xmm7*8+0x1000], xmm13
0000000000000000 c4e2919294fb00100000 VGATHERDPD xmm2, qword ptr [rbx+xmm7*8+0x1000], xmm13
DSIZE: 64, ASIZE: 64, VLEN: 128
ISA Set: AVX2GATHER, Ins cat: AVX2GATHER, CET tracked: no
Exception class: SSE/VEX, exception type: 12
@ -16,7 +16,7 @@
VSIB index size: 4, VSIB element size: 8, VSIB element count: 2
Operand: 2, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1
000000000000000A c4e2119294fb00100000 VGATHERDPS xmm2, xmmword ptr [rbx+xmm7*8+0x1000], xmm13
000000000000000A c4e2119294fb00100000 VGATHERDPS xmm2, dword ptr [rbx+xmm7*8+0x1000], xmm13
DSIZE: 32, ASIZE: 64, VLEN: 128
ISA Set: AVX2GATHER, Ins cat: AVX2GATHER, CET tracked: no
Exception class: SSE/VEX, exception type: 12
@ -34,7 +34,7 @@
VSIB index size: 4, VSIB element size: 4, VSIB element count: 4
Operand: 2, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1
0000000000000014 c4e2919394fb00100000 VGATHERQPD xmm2, xmmword ptr [rbx+xmm7*8+0x1000], xmm13
0000000000000014 c4e2919394fb00100000 VGATHERQPD xmm2, qword ptr [rbx+xmm7*8+0x1000], xmm13
DSIZE: 64, ASIZE: 64, VLEN: 128
ISA Set: AVX2GATHER, Ins cat: AVX2GATHER, CET tracked: no
Exception class: SSE/VEX, exception type: 12
@ -52,7 +52,7 @@
VSIB index size: 8, VSIB element size: 8, VSIB element count: 2
Operand: 2, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1
000000000000001E c4e2119394fb00100000 VGATHERQPS xmm2, qword ptr [rbx+xmm7*8+0x1000], xmm13
000000000000001E c4e2119394fb00100000 VGATHERQPS xmm2, dword ptr [rbx+xmm7*8+0x1000], xmm13
DSIZE: 32, ASIZE: 64, VLEN: 128
ISA Set: AVX2GATHER, Ins cat: AVX2GATHER, CET tracked: no
Exception class: SSE/VEX, exception type: 12
@ -70,7 +70,7 @@
VSIB index size: 8, VSIB element size: 4, VSIB element count: 2
Operand: 2, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1
0000000000000028 c4e2159394cb00100000 VGATHERQPS xmm2, xmmword ptr [rbx+ymm1*8+0x1000], xmm13
0000000000000028 c4e2159394cb00100000 VGATHERQPS xmm2, dword ptr [rbx+ymm1*8+0x1000], xmm13
DSIZE: 32, ASIZE: 64, VLEN: 256
ISA Set: AVX2GATHER, Ins cat: AVX2GATHER, CET tracked: no
Exception class: SSE/VEX, exception type: 12
@ -88,7 +88,7 @@
VSIB index size: 8, VSIB element size: 4, VSIB element count: 4
Operand: 2, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1
0000000000000032 c4e2119094fb00100000 VPGATHERDD xmm2, xmmword ptr [rbx+xmm7*8+0x1000], xmm13
0000000000000032 c4e2119094fb00100000 VPGATHERDD xmm2, dword ptr [rbx+xmm7*8+0x1000], xmm13
DSIZE: 32, ASIZE: 64, VLEN: 128
ISA Set: AVX2GATHER, Ins cat: AVX2GATHER, CET tracked: no
Exception class: SSE/VEX, exception type: 12
@ -106,7 +106,7 @@
VSIB index size: 4, VSIB element size: 4, VSIB element count: 4
Operand: 2, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1
000000000000003C c4e2919094fb00100000 VPGATHERDQ xmm2, xmmword ptr [rbx+xmm7*8+0x1000], xmm13
000000000000003C c4e2919094fb00100000 VPGATHERDQ xmm2, qword ptr [rbx+xmm7*8+0x1000], xmm13
DSIZE: 64, ASIZE: 64, VLEN: 128
ISA Set: AVX2GATHER, Ins cat: AVX2GATHER, CET tracked: no
Exception class: SSE/VEX, exception type: 12
@ -124,7 +124,7 @@
VSIB index size: 4, VSIB element size: 8, VSIB element count: 2
Operand: 2, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1
0000000000000046 c4e2119194fb00100000 VPGATHERQD xmm2, qword ptr [rbx+xmm7*8+0x1000], xmm13
0000000000000046 c4e2119194fb00100000 VPGATHERQD xmm2, dword ptr [rbx+xmm7*8+0x1000], xmm13
DSIZE: 32, ASIZE: 64, VLEN: 128
ISA Set: AVX2GATHER, Ins cat: AVX2GATHER, CET tracked: no
Exception class: SSE/VEX, exception type: 12
@ -142,7 +142,7 @@
VSIB index size: 8, VSIB element size: 4, VSIB element count: 2
Operand: 2, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1
0000000000000050 c4e2159194cb00100000 VPGATHERQD xmm2, xmmword ptr [rbx+ymm1*8+0x1000], xmm13
0000000000000050 c4e2159194cb00100000 VPGATHERQD xmm2, dword ptr [rbx+ymm1*8+0x1000], xmm13
DSIZE: 32, ASIZE: 64, VLEN: 256
ISA Set: AVX2GATHER, Ins cat: AVX2GATHER, CET tracked: no
Exception class: SSE/VEX, exception type: 12
@ -160,7 +160,7 @@
VSIB index size: 8, VSIB element size: 4, VSIB element count: 4
Operand: 2, Acc: RW, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 13, RegCount: 1
000000000000005A c4e2919194fb00100000 VPGATHERQQ xmm2, xmmword ptr [rbx+xmm7*8+0x1000], xmm13
000000000000005A c4e2919194fb00100000 VPGATHERQQ xmm2, qword ptr [rbx+xmm7*8+0x1000], xmm13
DSIZE: 64, ASIZE: 64, VLEN: 128
ISA Set: AVX2GATHER, Ins cat: AVX2GATHER, CET tracked: no
Exception class: SSE/VEX, exception type: 12

14
bddisasm_test/avx/avx_64.result
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@ -20609,7 +20609,7 @@
DSIZE: 32, ASIZE: 64, VLEN: 128
ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no
CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30
EVEX Tuple Type: Tuple 1 Scalar
EVEX Tuple Type: Tuple 1 scalar, 8 bit
Exception class: EVEX, exception type: E9NF
Valid modes
R0: yes, R1: yes, R2: yes, R3: yes
@ -20627,7 +20627,7 @@
DSIZE: 32, ASIZE: 64, VLEN: 128
ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no
CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30
EVEX Tuple Type: Tuple 1 Scalar
EVEX Tuple Type: Tuple 1 scalar, 8 bit
Exception class: EVEX, exception type: E9NF
Valid modes
R0: yes, R1: yes, R2: yes, R3: yes
@ -20802,7 +20802,7 @@
DSIZE: 32, ASIZE: 64, VLEN: 128
ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no
CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30
EVEX Tuple Type: Tuple 1 Scalar
EVEX Tuple Type: Tuple 1 scalar, 16 bit
Exception class: EVEX, exception type: E9NF
Valid modes
R0: yes, R1: yes, R2: yes, R3: yes
@ -20908,7 +20908,7 @@
DSIZE: 32, ASIZE: 64, VLEN: 128
ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no
CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30
EVEX Tuple Type: Tuple 1 Scalar
EVEX Tuple Type: Tuple 1 scalar, 16 bit
Exception class: EVEX, exception type: E9NF
Valid modes
R0: yes, R1: yes, R2: yes, R3: yes
@ -31299,7 +31299,7 @@
DSIZE: 32, ASIZE: 64, VLEN: 512
ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no
CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30
EVEX Tuple Type: Mem 128
EVEX Tuple Type: Full Mem
Exception class: EVEX, exception type: E4.nb
Valid modes
R0: yes, R1: yes, R2: yes, R3: yes
@ -31863,7 +31863,7 @@
DSIZE: 32, ASIZE: 64, VLEN: 512
ISA Set: AVX512BW, Ins cat: AVX512, CET tracked: no
CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 30
EVEX Tuple Type: Mem 128
EVEX Tuple Type: Full Mem
Exception class: EVEX, exception type: E4.nb
Valid modes
R0: yes, R1: yes, R2: yes, R3: yes