Browse Source

Renamed REG_* fields to NDR_*, so that we don't conflict with _GNU_SOURCES.

pull/15/head
Andrei Vlad LUTAS 2 years ago
parent
commit
144baa5140
  1. 176
      bddisasm/bddisasm.c
  2. 1448
      bddisasm/include/instructions.h
  3. 222
      bdshemu/bdshemu.c
  4. 4
      disasmtool/disasmtool.c
  5. 48
      disasmtool_lix/dumpers.cpp
  6. 194
      inc/cpuidflags.h
  7. 126
      inc/registers.h
  8. 4
      inc/version.h
  9. 4
      isagenerator/generate_tables.py
  10. 4
      pydis/_pydis/pydis.c

176
bddisasm/bddisasm.c

@ -912,7 +912,7 @@ NdFetchModrmAndSib(
}
// If needed, fetch the SIB.
if ((Instrux->ModRm.rm == REG_RSP) && (Instrux->ModRm.mod != 3) && (Instrux->AddrMode != ND_ADDR_16))
if ((Instrux->ModRm.rm == NDR_RSP) && (Instrux->ModRm.mod != 3) && (Instrux->AddrMode != ND_ADDR_16))
{
// At least one more byte must be available, for the sib.
RET_GT((size_t)Offset + 1, Size, ND_STATUS_BUFFER_TOO_SMALL);
@ -1180,17 +1180,17 @@ NdGetSegOverride(
switch (Instrux->Seg)
{
case ND_PREFIX_G2_SEG_CS:
return REG_CS;
return NDR_CS;
case ND_PREFIX_G2_SEG_DS:
return REG_DS;
return NDR_DS;
case ND_PREFIX_G2_SEG_ES:
return REG_ES;
return NDR_ES;
case ND_PREFIX_G2_SEG_SS:
return REG_SS;
return NDR_SS;
case ND_PREFIX_G2_SEG_FS:
return REG_FS;
return NDR_FS;
case ND_PREFIX_G2_SEG_GS:
return REG_GS;
return NDR_GS;
default:
return DefaultSeg;
}
@ -1714,7 +1714,7 @@ NdParseOperand(
operand->Type = ND_OP_REG;
operand->Info.Register.Type = ND_REG_GPR;
operand->Info.Register.Size = (ND_REG_SIZE)size;
operand->Info.Register.Reg = REG_RAX;
operand->Info.Register.Reg = NDR_RAX;
break;
case ND_OPT_GPR_AH:
@ -1722,7 +1722,7 @@ NdParseOperand(
operand->Type = ND_OP_REG;
operand->Info.Register.Type = ND_REG_GPR;
operand->Info.Register.Size = ND_SIZE_8BIT;
operand->Info.Register.Reg = REG_AH;
operand->Info.Register.Reg = NDR_AH;
operand->Info.Register.IsHigh8 = true;
break;
@ -1731,7 +1731,7 @@ NdParseOperand(
operand->Type = ND_OP_REG;
operand->Info.Register.Type = ND_REG_GPR;
operand->Info.Register.Size = (ND_REG_SIZE)size;
operand->Info.Register.Reg = REG_RCX;
operand->Info.Register.Reg = NDR_RCX;
break;
case ND_OPT_GPR_rDX:
@ -1739,7 +1739,7 @@ NdParseOperand(
operand->Type = ND_OP_REG;
operand->Info.Register.Type = ND_REG_GPR;
operand->Info.Register.Size = (ND_REG_SIZE)size;
operand->Info.Register.Reg = REG_RDX;
operand->Info.Register.Reg = NDR_RDX;
break;
case ND_OPT_GPR_rBX:
@ -1747,7 +1747,7 @@ NdParseOperand(
operand->Type = ND_OP_REG;
operand->Info.Register.Type = ND_REG_GPR;
operand->Info.Register.Size = (ND_REG_SIZE)size;
operand->Info.Register.Reg = REG_RBX;
operand->Info.Register.Reg = NDR_RBX;
break;
case ND_OPT_GPR_rBP:
@ -1755,7 +1755,7 @@ NdParseOperand(
operand->Type = ND_OP_REG;
operand->Info.Register.Type = ND_REG_GPR;
operand->Info.Register.Size = (ND_REG_SIZE)size;
operand->Info.Register.Reg = REG_RBP;
operand->Info.Register.Reg = NDR_RBP;
break;
case ND_OPT_GPR_rSP:
@ -1763,7 +1763,7 @@ NdParseOperand(
operand->Type = ND_OP_REG;
operand->Info.Register.Type = ND_REG_GPR;
operand->Info.Register.Size = (ND_REG_SIZE)size;
operand->Info.Register.Reg = REG_RSP;
operand->Info.Register.Reg = NDR_RSP;
break;
case ND_OPT_GPR_rSI:
@ -1771,7 +1771,7 @@ NdParseOperand(
operand->Type = ND_OP_REG;
operand->Info.Register.Type = ND_REG_GPR;
operand->Info.Register.Size = (ND_REG_SIZE)size;
operand->Info.Register.Reg = REG_RSI;
operand->Info.Register.Reg = NDR_RSI;
break;
case ND_OPT_GPR_rDI:
@ -1779,7 +1779,7 @@ NdParseOperand(
operand->Type = ND_OP_REG;
operand->Info.Register.Type = ND_REG_GPR;
operand->Info.Register.Size = (ND_REG_SIZE)size;
operand->Info.Register.Reg = REG_RDI;
operand->Info.Register.Reg = NDR_RDI;
break;
case ND_OPT_GPR_rR11:
@ -1787,7 +1787,7 @@ NdParseOperand(
operand->Type = ND_OP_REG;
operand->Info.Register.Type = ND_REG_GPR;
operand->Info.Register.Size = (ND_REG_SIZE)size;
operand->Info.Register.Reg = REG_R11;
operand->Info.Register.Reg = NDR_R11;
break;
case ND_OPT_SEG_CS:
@ -1795,7 +1795,7 @@ NdParseOperand(
operand->Type = ND_OP_REG;
operand->Info.Register.Type = ND_REG_SEG;
operand->Info.Register.Size = (ND_REG_SIZE)size;
operand->Info.Register.Reg = REG_CS;
operand->Info.Register.Reg = NDR_CS;
break;
case ND_OPT_SEG_SS:
@ -1803,7 +1803,7 @@ NdParseOperand(
operand->Type = ND_OP_REG;
operand->Info.Register.Type = ND_REG_SEG;
operand->Info.Register.Size = (ND_REG_SIZE)size;
operand->Info.Register.Reg = REG_SS;
operand->Info.Register.Reg = NDR_SS;
break;
case ND_OPT_SEG_DS:
@ -1811,7 +1811,7 @@ NdParseOperand(
operand->Type = ND_OP_REG;
operand->Info.Register.Type = ND_REG_SEG;
operand->Info.Register.Size = (ND_REG_SIZE)size;
operand->Info.Register.Reg = REG_DS;
operand->Info.Register.Reg = NDR_DS;
break;
case ND_OPT_SEG_ES:
@ -1819,7 +1819,7 @@ NdParseOperand(
operand->Type = ND_OP_REG;
operand->Info.Register.Type = ND_REG_SEG;
operand->Info.Register.Size = (ND_REG_SIZE)size;
operand->Info.Register.Reg = REG_ES;
operand->Info.Register.Reg = NDR_ES;
break;
case ND_OPT_SEG_FS:
@ -1827,7 +1827,7 @@ NdParseOperand(
operand->Type = ND_OP_REG;
operand->Info.Register.Type = ND_REG_SEG;
operand->Info.Register.Size = (ND_REG_SIZE)size;
operand->Info.Register.Reg = REG_FS;
operand->Info.Register.Reg = NDR_FS;
break;
case ND_OPT_SEG_GS:
@ -1835,7 +1835,7 @@ NdParseOperand(
operand->Type = ND_OP_REG;
operand->Info.Register.Type = ND_REG_SEG;
operand->Info.Register.Size = (ND_REG_SIZE)size;
operand->Info.Register.Reg = REG_GS;
operand->Info.Register.Reg = NDR_GS;
break;
case ND_OPT_FPU_ST0:
@ -1868,7 +1868,7 @@ NdParseOperand(
operand->Type = ND_OP_REG;
operand->Info.Register.Type = ND_REG_CR;
operand->Info.Register.Size = (ND_REG_SIZE)size;
operand->Info.Register.Reg = REG_CR0;
operand->Info.Register.Reg = NDR_CR0;
break;
case ND_OPT_SYS_GDTR:
@ -1876,7 +1876,7 @@ NdParseOperand(
operand->Type = ND_OP_REG;
operand->Info.Register.Type = ND_REG_SYS;
operand->Info.Register.Size = (ND_REG_SIZE)size;
operand->Info.Register.Reg = REG_GDTR;
operand->Info.Register.Reg = NDR_GDTR;
break;
case ND_OPT_SYS_IDTR:
@ -1884,7 +1884,7 @@ NdParseOperand(
operand->Type = ND_OP_REG;
operand->Info.Register.Type = ND_REG_SYS;
operand->Info.Register.Size = (ND_REG_SIZE)size;
operand->Info.Register.Reg = REG_IDTR;
operand->Info.Register.Reg = NDR_IDTR;
break;
case ND_OPT_SYS_LDTR:
@ -1892,7 +1892,7 @@ NdParseOperand(
operand->Type = ND_OP_REG;
operand->Info.Register.Type = ND_REG_SYS;
operand->Info.Register.Size = (ND_REG_SIZE)size;
operand->Info.Register.Reg = REG_LDTR;
operand->Info.Register.Reg = NDR_LDTR;
break;
case ND_OPT_SYS_TR:
@ -1900,7 +1900,7 @@ NdParseOperand(
operand->Type = ND_OP_REG;
operand->Info.Register.Type = ND_REG_SYS;
operand->Info.Register.Size = (ND_REG_SIZE)size;
operand->Info.Register.Reg = REG_TR;
operand->Info.Register.Reg = NDR_TR;
break;
case ND_OPT_X87_CONTROL:
@ -1908,7 +1908,7 @@ NdParseOperand(
operand->Type = ND_OP_REG;
operand->Info.Register.Type = ND_REG_SYS;
operand->Info.Register.Size = ND_SIZE_16BIT;
operand->Info.Register.Reg = REG_X87_CONTROL;
operand->Info.Register.Reg = NDR_X87_CONTROL;
break;
case ND_OPT_X87_TAG:
@ -1916,7 +1916,7 @@ NdParseOperand(
operand->Type = ND_OP_REG;
operand->Info.Register.Type = ND_REG_SYS;
operand->Info.Register.Size = ND_SIZE_16BIT;
operand->Info.Register.Reg = REG_X87_TAG;
operand->Info.Register.Reg = NDR_X87_TAG;
break;
case ND_OPT_X87_STATUS:
@ -1924,7 +1924,7 @@ NdParseOperand(
operand->Type = ND_OP_REG;
operand->Info.Register.Type = ND_REG_SYS;
operand->Info.Register.Size = ND_SIZE_16BIT;
operand->Info.Register.Reg = REG_X87_STATUS;
operand->Info.Register.Reg = NDR_X87_STATUS;
break;
case ND_OPT_MXCSR:
@ -1964,7 +1964,7 @@ NdParseOperand(
operand->Type = ND_OP_REG;
operand->Info.Register.Type = ND_REG_MSR;
operand->Info.Register.Size = ND_SIZE_64BIT;
operand->Info.Register.Reg = REG_IA32_TSC;
operand->Info.Register.Reg = NDR_IA32_TSC;
break;
case ND_OPT_MSR_TSCAUX:
@ -1972,7 +1972,7 @@ NdParseOperand(
operand->Type = ND_OP_REG;
operand->Info.Register.Type = ND_REG_MSR;
operand->Info.Register.Size = ND_SIZE_64BIT;
operand->Info.Register.Reg = REG_IA32_TSC_AUX;
operand->Info.Register.Reg = NDR_IA32_TSC_AUX;
break;
case ND_OPT_MSR_SCS:
@ -1980,7 +1980,7 @@ NdParseOperand(
operand->Type = ND_OP_REG;
operand->Info.Register.Type = ND_REG_MSR;
operand->Info.Register.Size = ND_SIZE_64BIT;
operand->Info.Register.Reg = REG_IA32_SYSENTER_CS;
operand->Info.Register.Reg = NDR_IA32_SYSENTER_CS;
break;
case ND_OPT_MSR_SESP:
@ -1988,7 +1988,7 @@ NdParseOperand(
operand->Type = ND_OP_REG;
operand->Info.Register.Type = ND_REG_MSR;
operand->Info.Register.Size = ND_SIZE_64BIT;
operand->Info.Register.Reg = REG_IA32_SYSENTER_ESP;
operand->Info.Register.Reg = NDR_IA32_SYSENTER_ESP;
break;
case ND_OPT_MSR_SEIP:
@ -1996,7 +1996,7 @@ NdParseOperand(
operand->Type = ND_OP_REG;
operand->Info.Register.Type = ND_REG_MSR;
operand->Info.Register.Size = ND_SIZE_64BIT;
operand->Info.Register.Reg = REG_IA32_SYSENTER_EIP;
operand->Info.Register.Reg = NDR_IA32_SYSENTER_EIP;
break;
case ND_OPT_MSR_STAR:
@ -2004,7 +2004,7 @@ NdParseOperand(
operand->Type = ND_OP_REG;
operand->Info.Register.Type = ND_REG_MSR;
operand->Info.Register.Size = ND_SIZE_64BIT;
operand->Info.Register.Reg = REG_IA32_STAR;
operand->Info.Register.Reg = NDR_IA32_STAR;
break;
case ND_OPT_MSR_LSTAR:
@ -2012,7 +2012,7 @@ NdParseOperand(
operand->Type = ND_OP_REG;
operand->Info.Register.Type = ND_REG_MSR;
operand->Info.Register.Size = ND_SIZE_64BIT;
operand->Info.Register.Reg = REG_IA32_LSTAR;
operand->Info.Register.Reg = NDR_IA32_LSTAR;
break;
case ND_OPT_MSR_FMASK:
@ -2020,7 +2020,7 @@ NdParseOperand(
operand->Type = ND_OP_REG;
operand->Info.Register.Type = ND_REG_MSR;
operand->Info.Register.Size = ND_SIZE_64BIT;
operand->Info.Register.Reg = REG_IA32_FMASK;
operand->Info.Register.Reg = NDR_IA32_FMASK;
break;
case ND_OPT_MSR_FSBASE:
@ -2028,7 +2028,7 @@ NdParseOperand(
operand->Type = ND_OP_REG;
operand->Info.Register.Type = ND_REG_MSR;
operand->Info.Register.Size = ND_SIZE_64BIT;
operand->Info.Register.Reg = REG_IA32_FS_BASE;
operand->Info.Register.Reg = NDR_IA32_FS_BASE;
break;
case ND_OPT_MSR_GSBASE:
@ -2036,7 +2036,7 @@ NdParseOperand(
operand->Type = ND_OP_REG;
operand->Info.Register.Type = ND_REG_MSR;
operand->Info.Register.Size = ND_SIZE_64BIT;
operand->Info.Register.Reg = REG_IA32_GS_BASE;
operand->Info.Register.Reg = NDR_IA32_GS_BASE;
break;
case ND_OPT_MSR_KGSBASE:
@ -2044,7 +2044,7 @@ NdParseOperand(
operand->Type = ND_OP_REG;
operand->Info.Register.Type = ND_REG_MSR;
operand->Info.Register.Size = ND_SIZE_64BIT;
operand->Info.Register.Reg = REG_IA32_GS_BASE;
operand->Info.Register.Reg = NDR_IA32_GS_BASE;
break;
case ND_OPT_XCR:
@ -2071,7 +2071,7 @@ NdParseOperand(
operand->Size = operand->RawSize = Instrux->WordLength;
operand->Info.Register.Type = ND_REG_GPR;
operand->Info.Register.Size = Instrux->WordLength;
operand->Info.Register.Reg = REG_EAX;
operand->Info.Register.Reg = NDR_EAX;
operand->Info.Register.Count = 8;
operand->Info.Register.IsBlock = true;
}
@ -2181,7 +2181,7 @@ NdParseOperand(
}
// If CS is loaded - #UD.
if ((operand->Info.Register.Reg == REG_CS) && operand->Access.Write)
if ((operand->Info.Register.Reg == NDR_CS) && operand->Access.Write)
{
return ND_STATUS_CS_LOAD;
}
@ -2225,10 +2225,10 @@ NdParseOperand(
operand->Type = ND_OP_MEM;
operand->Info.Memory.IsStack = true;
operand->Info.Memory.HasBase = true;
operand->Info.Memory.Base = REG_RSP;
operand->Info.Memory.Base = NDR_RSP;
operand->Info.Memory.BaseSize = szLut[Instrux->DefStack];
operand->Info.Memory.HasSeg = true;
operand->Info.Memory.Seg = REG_SS;
operand->Info.Memory.Seg = NDR_SS;
Instrux->StackWords = (uint8_t)(operand->Size / Instrux->WordLength);
Instrux->StackAccess |= operand->Access.Access;
}
@ -2414,7 +2414,7 @@ NdParseOperand(
operand->Info.Memory.DispSize = Instrux->MoffsetLength;
operand->Info.Memory.Disp = Instrux->Moffset;
operand->Info.Memory.HasSeg = true;
operand->Info.Memory.Seg = NdGetSegOverride(Instrux, REG_DS);
operand->Info.Memory.Seg = NdGetSegOverride(Instrux, NDR_DS);
Offset = Instrux->Length;
}
@ -2447,58 +2447,58 @@ memory:
operand->Info.Memory.HasBase = true;
operand->Info.Memory.HasIndex = true;
operand->Info.Memory.Scale = 1;
operand->Info.Memory.Base = REG_BX;
operand->Info.Memory.Index = REG_SI;
operand->Info.Memory.Base = NDR_BX;
operand->Info.Memory.Index = NDR_SI;
operand->Info.Memory.BaseSize = ND_SIZE_16BIT;
operand->Info.Memory.IndexSize = ND_SIZE_16BIT;
operand->Info.Memory.Seg = REG_DS;
operand->Info.Memory.Seg = NDR_DS;
break;
case 1:
// [bx + di]
operand->Info.Memory.HasBase = true;
operand->Info.Memory.HasIndex = true;
operand->Info.Memory.Scale = 1;
operand->Info.Memory.Base = REG_BX;
operand->Info.Memory.Index = REG_DI;
operand->Info.Memory.Base = NDR_BX;
operand->Info.Memory.Index = NDR_DI;
operand->Info.Memory.BaseSize = ND_SIZE_16BIT;
operand->Info.Memory.IndexSize = ND_SIZE_16BIT;
operand->Info.Memory.Seg = REG_DS;
operand->Info.Memory.Seg = NDR_DS;
break;
case 2:
// [bp + si]
operand->Info.Memory.HasBase = true;
operand->Info.Memory.HasIndex = true;
operand->Info.Memory.Scale = 1;
operand->Info.Memory.Base = REG_BP;
operand->Info.Memory.Index = REG_SI;
operand->Info.Memory.Base = NDR_BP;
operand->Info.Memory.Index = NDR_SI;
operand->Info.Memory.BaseSize = ND_SIZE_16BIT;
operand->Info.Memory.IndexSize = ND_SIZE_16BIT;
operand->Info.Memory.Seg = REG_SS;
operand->Info.Memory.Seg = NDR_SS;
break;
case 3:
// [bp + di]
operand->Info.Memory.HasBase = true;
operand->Info.Memory.HasIndex = true;
operand->Info.Memory.Scale = 1;
operand->Info.Memory.Base = REG_BP;
operand->Info.Memory.Index = REG_DI;
operand->Info.Memory.Base = NDR_BP;
operand->Info.Memory.Index = NDR_DI;
operand->Info.Memory.BaseSize = ND_SIZE_16BIT;
operand->Info.Memory.IndexSize = ND_SIZE_16BIT;
operand->Info.Memory.Seg = REG_SS;
operand->Info.Memory.Seg = NDR_SS;
break;
case 4:
// [si]
operand->Info.Memory.HasBase = true;
operand->Info.Memory.Base = REG_SI;
operand->Info.Memory.Base = NDR_SI;
operand->Info.Memory.BaseSize = ND_SIZE_16BIT;
operand->Info.Memory.Seg = REG_DS;
operand->Info.Memory.Seg = NDR_DS;
break;
case 5:
// [di]
operand->Info.Memory.HasBase = true;
operand->Info.Memory.Base = REG_DI;
operand->Info.Memory.Base = NDR_DI;
operand->Info.Memory.BaseSize = ND_SIZE_16BIT;
operand->Info.Memory.Seg = REG_DS;
operand->Info.Memory.Seg = NDR_DS;
break;
case 6:
// [bp]
@ -2506,22 +2506,22 @@ memory:
{
// If mod is not zero, than we have "[bp + displacement]".
operand->Info.Memory.HasBase = true;
operand->Info.Memory.Base = REG_BP;
operand->Info.Memory.Base = NDR_BP;
operand->Info.Memory.BaseSize = ND_SIZE_16BIT;
operand->Info.Memory.Seg = REG_SS;
operand->Info.Memory.Seg = NDR_SS;
}
else
{
// If mod is zero, than we only have a displacement that is used to directly address mem.
operand->Info.Memory.Seg = REG_DS;
operand->Info.Memory.Seg = NDR_DS;
}
break;
case 7:
// [bx]
operand->Info.Memory.HasBase = true;
operand->Info.Memory.Base = REG_BX;
operand->Info.Memory.Base = NDR_BX;
operand->Info.Memory.BaseSize = ND_SIZE_16BIT;
operand->Info.Memory.Seg = REG_DS;
operand->Info.Memory.Seg = NDR_DS;
break;
}
@ -2535,12 +2535,12 @@ memory:
uint8_t defsize = (Instrux->AddrMode == ND_ADDR_32 ? ND_SIZE_32BIT : ND_SIZE_64BIT);
// Implicit segment is DS.
operand->Info.Memory.Seg = REG_DS;
operand->Info.Memory.Seg = NDR_DS;
if (Instrux->HasSib)
{
// Check for base.
if ((Instrux->ModRm.mod == 0) && (Instrux->Sib.base == REG_RBP))
if ((Instrux->ModRm.mod == 0) && (Instrux->Sib.base == NDR_RBP))
{
// Mod is mem without displacement and base reg is RBP -> no base reg used.
// Note that this addressing mode is not RIP relative.
@ -2551,14 +2551,14 @@ memory:
operand->Info.Memory.BaseSize = defsize;
operand->Info.Memory.Base = (uint8_t)((Instrux->Exs.b << 3) | Instrux->Sib.base);
if ((operand->Info.Memory.Base == REG_RSP) || (operand->Info.Memory.Base == REG_RBP))
if ((operand->Info.Memory.Base == NDR_RSP) || (operand->Info.Memory.Base == NDR_RBP))
{
operand->Info.Memory.Seg = REG_SS;
operand->Info.Memory.Seg = NDR_SS;
}
}
// Check for index.
if ((((Instrux->Exs.x << 3) | Instrux->Sib.index) != REG_RSP) || ND_HAS_VSIB(Instrux))
if ((((Instrux->Exs.x << 3) | Instrux->Sib.index) != NDR_RSP) || ND_HAS_VSIB(Instrux))
{
// Index * Scale is present.
operand->Info.Memory.HasIndex = true;
@ -2576,7 +2576,7 @@ memory:
}
else
{
if ((Instrux->ModRm.mod == 0) && (Instrux->ModRm.rm == REG_RBP))
if ((Instrux->ModRm.mod == 0) && (Instrux->ModRm.rm == NDR_RBP))
{
//
// RIP relative addressing addresses a memory region relative to the current RIP; However,
@ -2599,9 +2599,9 @@ memory:
operand->Info.Memory.BaseSize = defsize;
operand->Info.Memory.Base = (uint8_t)((Instrux->Exs.b << 3) | Instrux->ModRm.rm);
if ((operand->Info.Memory.Base == REG_RSP) || (operand->Info.Memory.Base == REG_RBP))
if ((operand->Info.Memory.Base == NDR_RSP) || (operand->Info.Memory.Base == NDR_RBP))
{
operand->Info.Memory.Seg = REG_SS;
operand->Info.Memory.Seg = NDR_SS;
}
}
}
@ -2802,16 +2802,16 @@ memory:
operand->Info.Memory.HasBase = true;
operand->Info.Memory.BaseSize = 2 << Instrux->AddrMode;
operand->Info.Memory.HasSeg = true;
operand->Info.Memory.Base = (uint8_t)(((opt == ND_OPT_X) ? REG_RSI : REG_RDI));
operand->Info.Memory.Base = (uint8_t)(((opt == ND_OPT_X) ? NDR_RSI : NDR_RDI));
operand->Info.Memory.IsString = (ND_OPT_X == opt || ND_OPT_Y == opt);
// DS:rSI supports segment overriding. ES:rDI does not.
if (opt == ND_OPT_Y)
{
operand->Info.Memory.Seg = REG_ES;
operand->Info.Memory.Seg = NDR_ES;
}
else
{
operand->Info.Memory.Seg = NdGetSegOverride(Instrux, REG_DS);
operand->Info.Memory.Seg = NdGetSegOverride(Instrux, NDR_DS);
}
break;
@ -2823,11 +2823,11 @@ memory:
operand->Info.Memory.HasIndex = true;
operand->Info.Memory.BaseSize = 2 << Instrux->AddrMode;
operand->Info.Memory.IndexSize = ND_SIZE_8BIT; // Always 1 Byte.
operand->Info.Memory.Base = REG_RBX; // Always rBX.
operand->Info.Memory.Index = REG_AL; // Always AL.
operand->Info.Memory.Base = NDR_RBX; // Always rBX.
operand->Info.Memory.Index = NDR_AL; // Always AL.
operand->Info.Memory.Scale = 1; // Always 1.
operand->Info.Memory.HasSeg = true;
operand->Info.Memory.Seg = NdGetSegOverride(Instrux, REG_DS);
operand->Info.Memory.Seg = NdGetSegOverride(Instrux, NDR_DS);
break;
case ND_OPT_MEM_SHS:
@ -2960,7 +2960,7 @@ memory:
operand->Info.Memory.Base = (uint8_t)((Instrux->Exs.r << 3) | Instrux->ModRm.reg);
operand->Info.Memory.BaseSize = 2 << Instrux->AddrMode;
operand->Info.Memory.HasSeg = true;
operand->Info.Memory.Seg = REG_ES;
operand->Info.Memory.Seg = NDR_ES;
break;
case ND_OPT_mM:
@ -2970,7 +2970,7 @@ memory:
operand->Info.Memory.Base = (uint8_t)((Instrux->Exs.m << 3) | Instrux->ModRm.rm);
operand->Info.Memory.BaseSize = 2 << Instrux->AddrMode;
operand->Info.Memory.HasSeg = true;
operand->Info.Memory.Seg = NdGetSegOverride(Instrux, REG_DS);
operand->Info.Memory.Seg = NdGetSegOverride(Instrux, NDR_DS);
break;
case ND_OPT_rT:
@ -4632,8 +4632,8 @@ NdToText(
return ND_STATUS_INVALID_INSTRUX;
}
if ((ND_CODE_64 != Instrux->DefCode) || (REG_FS == pOp->Info.Memory.Seg) ||
(REG_GS == pOp->Info.Memory.Seg))
if ((ND_CODE_64 != Instrux->DefCode) || (NDR_FS == pOp->Info.Memory.Seg) ||
(NDR_GS == pOp->Info.Memory.Seg))
{
res = nd_strcat_s(Buffer, BufferSize, gRegSeg[pOp->Info.Memory.Seg]);
RET_EQ(res, NULL, ND_STATUS_BUFFER_OVERFLOW);
@ -4957,8 +4957,8 @@ NdGetFullAccessMap(
if (pOp->Info.Memory.IsStack)
{
AccessMap->StackAccess |= pOp->Access.Access;
AccessMap->GprAccess[REG_RSP] |= ND_ACCESS_READ|ND_ACCESS_WRITE;
AccessMap->SegAccess[REG_SS] |= ND_ACCESS_READ;
AccessMap->GprAccess[NDR_RSP] |= ND_ACCESS_READ|ND_ACCESS_WRITE;
AccessMap->SegAccess[NDR_SS] |= ND_ACCESS_READ;
}
else
{

1448
bddisasm/include/instructions.h

File diff suppressed because it is too large Load Diff

222
bdshemu/bdshemu.c

@ -321,60 +321,60 @@ ShemuSetFlags(
// PF set if the first bytes has an even number of 1 bits.
if ((pfArr[Dst & 0xF] + pfArr[(Dst >> 4) & 0xF]) % 2 == 0)
{
Context->Registers.RegFlags |= REG_RFLAG_PF;
Context->Registers.RegFlags |= NDR_RFLAG_PF;
}
else
{
Context->Registers.RegFlags &= ~REG_RFLAG_PF;
Context->Registers.RegFlags &= ~NDR_RFLAG_PF;
}
// ZF set if the result is zero.
if (Dst == 0)
{
Context->Registers.RegFlags |= REG_RFLAG_ZF;
Context->Registers.RegFlags |= NDR_RFLAG_ZF;
}
else
{
Context->Registers.RegFlags &= ~REG_RFLAG_ZF;
Context->Registers.RegFlags &= ~NDR_RFLAG_ZF;
}
// SF is set if the sign flag is set.
if (ND_GET_SIGN(Size, Dst) != 0)
{
Context->Registers.RegFlags |= REG_RFLAG_SF;
Context->Registers.RegFlags |= NDR_RFLAG_SF;
}
else
{
Context->Registers.RegFlags &= ~REG_RFLAG_SF;
Context->Registers.RegFlags &= ~NDR_RFLAG_SF;
}
// OF and CF are handled differently for some instructions.
if (FM_LOGIC == FlagsMode)
{
// OF and CF are cleared on logic instructions.
Context->Registers.RegFlags &= ~(REG_RFLAG_OF | REG_RFLAG_CF);
Context->Registers.RegFlags &= ~(NDR_RFLAG_OF | NDR_RFLAG_CF);
}
else if (FM_SHL == FlagsMode)
{
// CF is the last bit shifted out of the destination.
if (ND_GET_BIT(Src1, (Size * 8) - Src2))
{
Context->Registers.RegFlags |= REG_RFLAG_CF;
Context->Registers.RegFlags |= NDR_RFLAG_CF;
}
else
{
Context->Registers.RegFlags &= ~REG_RFLAG_CF;
Context->Registers.RegFlags &= ~NDR_RFLAG_CF;
}
if (Src2 == 1)
{
if (ND_GET_BIT(Size * 8 - 1, Dst) ^ ND_GET_BIT(Src1, (Size * 8) - Src2))
{
Context->Registers.RegFlags |= REG_RFLAG_OF;
Context->Registers.RegFlags |= NDR_RFLAG_OF;
}
else
{
Context->Registers.RegFlags &= ~REG_RFLAG_OF;
Context->Registers.RegFlags &= ~NDR_RFLAG_OF;
}
}
}
@ -383,22 +383,22 @@ ShemuSetFlags(
// CF is the last bit shifted out of the destination.
if (ND_GET_BIT(Src1, Src2 - 1))
{
Context->Registers.RegFlags |= REG_RFLAG_CF;
Context->Registers.RegFlags |= NDR_RFLAG_CF;
}
else
{
Context->Registers.RegFlags &= ~REG_RFLAG_CF;
Context->Registers.RegFlags &= ~NDR_RFLAG_CF;
}
if (Src2 == 1)
{
if (ND_GET_BIT(Size * 8 - 1, Dst))
{
Context->Registers.RegFlags |= REG_RFLAG_OF;
Context->Registers.RegFlags |= NDR_RFLAG_OF;
}
else
{
Context->Registers.RegFlags &= ~REG_RFLAG_OF;
Context->Registers.RegFlags &= ~NDR_RFLAG_OF;
}
}
}
@ -407,29 +407,29 @@ ShemuSetFlags(
// CF is the last bit shifted out of the destination.
if (ND_GET_BIT(Src1, Src2 - 1))
{
Context->Registers.RegFlags |= REG_RFLAG_CF;
Context->Registers.RegFlags |= NDR_RFLAG_CF;
}
else
{
Context->Registers.RegFlags &= ~REG_RFLAG_CF;
Context->Registers.RegFlags &= ~NDR_RFLAG_CF;
}
Context->Registers.RegFlags &= ~REG_RFLAG_OF;
Context->Registers.RegFlags &= ~NDR_RFLAG_OF;
}
else
{
// Set CF.
if ((FM_SUB == FlagsMode) && (Src1 < Src2))
{
Context->Registers.RegFlags |= REG_RFLAG_CF;
Context->Registers.RegFlags |= NDR_RFLAG_CF;
}
else if ((FM_ADD == FlagsMode) && (Dst < Src1))
{
Context->Registers.RegFlags |= REG_RFLAG_CF;
Context->Registers.RegFlags |= NDR_RFLAG_CF;
}
else
{
Context->Registers.RegFlags &= ~REG_RFLAG_CF;
Context->Registers.RegFlags &= ~NDR_RFLAG_CF;
}
// Set OF.
@ -438,11 +438,11 @@ ShemuSetFlags(
if ((ND_GET_SIGN(Size, Src1) && !ND_GET_SIGN(Size, Src2) && !ND_GET_SIGN(Size, Dst)) ||
(!ND_GET_SIGN(Size, Src1) && ND_GET_SIGN(Size, Src2) && ND_GET_SIGN(Size, Dst)))
{
Context->Registers.RegFlags |= REG_RFLAG_OF;
Context->Registers.RegFlags |= NDR_RFLAG_OF;
}
else
{
Context->Registers.RegFlags &= ~REG_RFLAG_OF;
Context->Registers.RegFlags &= ~NDR_RFLAG_OF;
}
}
else if (FM_ADD == FlagsMode)
@ -450,11 +450,11 @@ ShemuSetFlags(
if (ND_GET_SIGN(Size, Src1) == ND_GET_SIGN(Size, Src2) &&
ND_GET_SIGN(Size, Src1) != ND_GET_SIGN(Size, Dst))
{
Context->Registers.RegFlags |= REG_RFLAG_OF;
Context->Registers.RegFlags |= NDR_RFLAG_OF;
}
else
{
Context->Registers.RegFlags &= ~REG_RFLAG_OF;
Context->Registers.RegFlags &= ~NDR_RFLAG_OF;
}
}
}
@ -473,99 +473,99 @@ ShemuEvalCondition(
switch (ConditionCode)
{
case ND_COND_OVERFLOW: // O
if (GET_FLAG(Context, REG_RFLAG_OF) == 1)
if (GET_FLAG(Context, NDR_RFLAG_OF) == 1)
{
return true;
}
break;
case ND_COND_NOT(ND_COND_OVERFLOW): // NO
if (GET_FLAG(Context, REG_RFLAG_OF) == 0)
if (GET_FLAG(Context, NDR_RFLAG_OF) == 0)
{
return true;
}
break;
case ND_COND_CARRY: // C/B/NAE
if (GET_FLAG(Context, REG_RFLAG_CF) == 1)
if (GET_FLAG(Context, NDR_RFLAG_CF) == 1)
{
return true;
}
break;
case ND_COND_NOT(ND_COND_CARRY): // NC/NB/AE
if (GET_FLAG(Context, REG_RFLAG_CF) == 0)
if (GET_FLAG(Context, NDR_RFLAG_CF) == 0)
{
return true;
}
break;
case ND_COND_ZERO: // E/Z
if (GET_FLAG(Context, REG_RFLAG_ZF) == 1)
if (GET_FLAG(Context, NDR_RFLAG_ZF) == 1)
{
return true;
}
break;
case ND_COND_NOT(ND_COND_ZERO): // NE/NZ
if (GET_FLAG(Context, REG_RFLAG_ZF) == 0)
if (GET_FLAG(Context, NDR_RFLAG_ZF) == 0)
{
return true;
}
break;
case ND_COND_BELOW_OR_EQUAL: // BE/NA
if ((GET_FLAG(Context, REG_RFLAG_CF) | (GET_FLAG(Context, REG_RFLAG_ZF))) == 1)
if ((GET_FLAG(Context, NDR_RFLAG_CF) | (GET_FLAG(Context, NDR_RFLAG_ZF))) == 1)
{
return true;
}
break;
case ND_COND_NOT(ND_COND_BELOW_OR_EQUAL): // A/NBE
if ((GET_FLAG(Context, REG_RFLAG_CF) | (GET_FLAG(Context, REG_RFLAG_ZF))) == 0)
if ((GET_FLAG(Context, NDR_RFLAG_CF) | (GET_FLAG(Context, NDR_RFLAG_ZF))) == 0)
{
return true;
}
break;
case ND_COND_SIGN: // S
if (GET_FLAG(Context, REG_RFLAG_SF) == 1)
if (GET_FLAG(Context, NDR_RFLAG_SF) == 1)
{
return true;
}
break;
case ND_COND_NOT(ND_COND_SIGN): // NS
if (GET_FLAG(Context, REG_RFLAG_SF) == 0)
if (GET_FLAG(Context, NDR_RFLAG_SF) == 0)
{
return true;
}
break;
case ND_COND_PARITY: // P
if (GET_FLAG(Context, REG_RFLAG_PF) == 1)
if (GET_FLAG(Context, NDR_RFLAG_PF) == 1)
{
return true;
}
break;
case ND_COND_NOT(ND_COND_PARITY): // NP
if (GET_FLAG(Context, REG_RFLAG_PF) == 0)
if (GET_FLAG(Context, NDR_RFLAG_PF) == 0)
{
return true;
}
break;
case ND_COND_LESS: // L/NGE
if ((GET_FLAG(Context, REG_RFLAG_SF) ^ GET_FLAG(Context, REG_RFLAG_OF)) == 1)
if ((GET_FLAG(Context, NDR_RFLAG_SF) ^ GET_FLAG(Context, NDR_RFLAG_OF)) == 1)
{
return true;
}
break;
case ND_COND_NOT(ND_COND_LESS): // NL/GE
if ((GET_FLAG(Context, REG_RFLAG_SF) ^ GET_FLAG(Context, REG_RFLAG_OF)) == 0)
if ((GET_FLAG(Context, NDR_RFLAG_SF) ^ GET_FLAG(Context, NDR_RFLAG_OF)) == 0)
{
return true;
}
break;
case ND_COND_LESS_OR_EQUAL: // LE/NG
if (((GET_FLAG(Context, REG_RFLAG_SF) ^ GET_FLAG(Context, REG_RFLAG_OF)) |
(GET_FLAG(Context, REG_RFLAG_ZF))) == 1)
if (((GET_FLAG(Context, NDR_RFLAG_SF) ^ GET_FLAG(Context, NDR_RFLAG_OF)) |
(GET_FLAG(Context, NDR_RFLAG_ZF))) == 1)
{
return true;
}
break;
case ND_COND_NOT(ND_COND_LESS_OR_EQUAL): // NLE/G
if (((GET_FLAG(Context, REG_RFLAG_SF) ^ GET_FLAG(Context, REG_RFLAG_OF)) |
(GET_FLAG(Context, REG_RFLAG_ZF))) == 0)
if (((GET_FLAG(Context, NDR_RFLAG_SF) ^ GET_FLAG(Context, NDR_RFLAG_OF)) |
(GET_FLAG(Context, NDR_RFLAG_ZF))) == 0)
{
return true;
}
@ -696,17 +696,17 @@ ShemuGetSegValue(
{
switch (Reg)
{
case REG_ES:
case NDR_ES:
return Context->Segments.Es.Selector;
case REG_CS:
case NDR_CS:
return Context->Segments.Cs.Selector;
case REG_SS:
case NDR_SS:
return Context->Segments.Ss.Selector;
case REG_DS:
case NDR_DS:
return Context->Segments.Ds.Selector;
case REG_FS:
case NDR_FS:
return Context->Segments.Fs.Selector;
case REG_GS:
case NDR_GS:
return Context->Segments.Gs.Selector;
}
@ -726,22 +726,22 @@ ShemuSetSegValue(
{
switch (Reg)
{
case REG_ES:
case NDR_ES:
Context->Segments.Es.Selector = Value;
break;
case REG_CS:
case NDR_CS:
Context->Segments.Cs.Selector = Value;
break;
case REG_SS:
case NDR_SS:
Context->Segments.Ss.Selector = Value;
break;
case REG_DS:
case NDR_DS:
Context->Segments.Ds.Selector = Value;
break;
case REG_FS:
case NDR_FS:
Context->Segments.Fs.Selector = Value;
break;
case REG_GS:
case NDR_GS:
Context->Segments.Gs.Selector = Value;
break;
}
@ -759,17 +759,17 @@ ShemuGetSegBase(
{
switch (Reg)
{
case REG_ES:
case NDR_ES:
return Context->Segments.Es.Base;
case REG_CS:
case NDR_CS:
return Context->Segments.Cs.Base;
case REG_SS:
case NDR_SS:
return Context->Segments.Ss.Base;
case REG_DS:
case NDR_DS:
return Context->Segments.Ds.Base;
case REG_FS:
case NDR_FS:
return Context->Segments.Fs.Base;
case REG_GS:
case NDR_GS:
return Context->Segments.Gs.Base;
}
@ -1084,19 +1084,19 @@ ShemuGetOperandValue(
case ND_REG_CR:
switch (op->Info.Register.Reg)
{
case REG_CR0:
case NDR_CR0:
Value->Value.Qwords[0] = Context->Registers.RegCr0;
break;
case REG_CR2:
case NDR_CR2:
Value->Value.Qwords[0] = Context->Registers.RegCr2;
break;
case REG_CR3:
case NDR_CR3:
Value->Value.Qwords[0] = Context->Registers.RegCr3;
break;
case REG_CR4:
case NDR_CR4:
Value->Value.Qwords[0] = Context->Registers.RegCr4;
break;
case REG_CR8:
case NDR_CR8:
Value->Value.Qwords[0] = Context->Registers.RegCr8;
break;
default:
@ -1163,11 +1163,11 @@ ShemuGetOperandValue(
// If this is a stack access, we need to update the stack pointer.
if (op->Info.Memory.IsStack)
{
uint64_t regval = ShemuGetGprValue(Context, REG_RSP, (2 << Context->Instruction.DefStack), false);
uint64_t regval = ShemuGetGprValue(Context, NDR_RSP, (2 << Context->Instruction.DefStack), false);
regval += op->Size;
ShemuSetGprValue(Context, REG_RSP, (2 << Context->Instruction.DefStack), regval, false);
ShemuSetGprValue(Context, NDR_RSP, (2 << Context->Instruction.DefStack), regval, false);
}
// If this is a string operation, make sure we update RSI/RDI.
@ -1175,7 +1175,7 @@ ShemuGetOperandValue(
{
uint64_t regval = ShemuGetGprValue(Context, op->Info.Memory.Base, op->Info.Memory.BaseSize, false);
regval = GET_FLAG(Context, REG_RFLAG_DF) ? regval - op->Size : regval + op->Size;
regval = GET_FLAG(Context, NDR_RFLAG_DF) ? regval - op->Size : regval + op->Size;
ShemuSetGprValue(Context, op->Info.Memory.Base, op->Info.Memory.BaseSize, regval, false);
}
@ -1260,19 +1260,19 @@ ShemuSetOperandValue(
case ND_REG_CR:
switch (op->Info.Register.Reg)
{
case REG_CR0:
case NDR_CR0:
Context->Registers.RegCr0 = Value->Value.Qwords[0];
break;
case REG_CR2:
case NDR_CR2:
Context->Registers.RegCr2 = Value->Value.Qwords[0];
break;
case REG_CR3:
case NDR_CR3:
Context->Registers.RegCr3 = Value->Value.Qwords[0];
break;
case REG_CR4:
case NDR_CR4:
Context->Registers.RegCr4 = Value->Value.Qwords[0];
break;
case REG_CR8:
case NDR_CR8:
Context->Registers.RegCr8 = Value->Value.Qwords[0];
break;
default:
@ -1359,11 +1359,11 @@ ShemuSetOperandValue(
// If this is a stack access, we need to update the stack pointer.
if (op->Info.Memory.IsStack)
{
uint64_t regval = ShemuGetGprValue(Context, REG_RSP, (2 << Context->Instruction.DefStack), false);
uint64_t regval = ShemuGetGprValue(Context, NDR_RSP, (2 << Context->Instruction.DefStack), false);
regval -= op->Size;
ShemuSetGprValue(Context, REG_RSP, (2 << Context->Instruction.DefStack), regval, false);
ShemuSetGprValue(Context, NDR_RSP, (2 << Context->Instruction.DefStack), regval, false);
}
// If this is a string operation, make sure we update RSI/RDI.
@ -1371,7 +1371,7 @@ ShemuSetOperandValue(
{
uint64_t regval = ShemuGetGprValue(Context, op->Info.Memory.Base, op->Info.Memory.BaseSize, false);
regval = GET_FLAG(Context, REG_RFLAG_DF) ? regval - op->Size : regval + op->Size;
regval = GET_FLAG(Context, NDR_RFLAG_DF) ? regval - op->Size : regval + op->Size;
ShemuSetGprValue(Context, op->Info.Memory.Base, op->Info.Memory.BaseSize, regval, false);
}
@ -1660,12 +1660,12 @@ ShemuEmulate(
{
GET_OP(Context, 1, &src);
SET_OP(Context, 0, &src);
SET_FLAG(Context, REG_RFLAG_ZF, 1);
SET_FLAG(Context, NDR_RFLAG_ZF, 1);
}
else
{
SET_OP(Context, 2, &dst);
SET_FLAG(Context, REG_RFLAG_ZF, 0);
SET_FLAG(Context, NDR_RFLAG_ZF, 0);
}
break;
@ -1676,7 +1676,7 @@ ShemuEmulate(
if (ND_INS_ADC == Context->Instruction.Instruction)
{
src.Value.Qwords[0] += GET_FLAG(Context, REG_RFLAG_CF);
src.Value.Qwords[0] += GET_FLAG(Context, NDR_RFLAG_CF);
}
res.Size = src.Size;
@ -1695,7 +1695,7 @@ ShemuEmulate(
if (ND_INS_SBB == Context->Instruction.Instruction)
{
src.Value.Qwords[0] += GET_FLAG(Context, REG_RFLAG_CF);
src.Value.Qwords[0] += GET_FLAG(Context, NDR_RFLAG_CF);
}
res.Size = src.Size;
@ -1864,31 +1864,31 @@ ShemuEmulate(
while (tempcnt != 0)
{
tempCF = ND_MSB(dst.Size, dst.Value.Qwords[0]);
dst.Value.Qwords[0] = (dst.Value.Qwords[0] << 1) + GET_FLAG(Context, REG_RFLAG_CF);
SET_FLAG(Context, REG_RFLAG_CF, tempCF);
dst.Value.Qwords[0] = (dst.Value.Qwords[0] << 1) + GET_FLAG(Context, NDR_RFLAG_CF);
SET_FLAG(Context, NDR_RFLAG_CF, tempCF);
tempcnt--;
}
if ((cnt & cntmask) == 1)
{
SET_FLAG(Context, REG_RFLAG_OF, ND_MSB(dst.Size, dst.Value.Qwords[0]) ^
GET_FLAG(Context, REG_RFLAG_CF));
SET_FLAG(Context, NDR_RFLAG_OF, ND_MSB(dst.Size, dst.Value.Qwords[0]) ^
GET_FLAG(Context, NDR_RFLAG_CF));
}
}
else if (ND_INS_RCR == Context->Instruction.Instruction)
{
if ((cnt & cntmask) == 1)
{
SET_FLAG(Context, REG_RFLAG_OF, ND_MSB(dst.Size, dst.Value.Qwords[0]) ^
GET_FLAG(Context, REG_RFLAG_CF));
SET_FLAG(Context, NDR_RFLAG_OF, ND_MSB(dst.Size, dst.Value.Qwords[0]) ^
GET_FLAG(Context, NDR_RFLAG_CF));
}
while (tempcnt != 0)
{
tempCF = ND_LSB(dst.Size, dst.Value.Qwords[0]);
dst.Value.Qwords[0] = (dst.Value.Qwords[0] >> 1) +
((uint64_t)GET_FLAG(Context, REG_RFLAG_CF) << (dst.Size * 8 - 1));
SET_FLAG(Context, REG_RFLAG_CF, tempCF);
((uint64_t)GET_FLAG(Context, NDR_RFLAG_CF) << (dst.Size * 8 - 1));
SET_FLAG(Context, NDR_RFLAG_CF, tempCF);
tempcnt--;
}
}
@ -1903,13 +1903,13 @@ ShemuEmulate(
if ((cnt & cntmask) != 0)
{
SET_FLAG(Context, REG_RFLAG_CF, dst.Value.Qwords[0] & 1);
SET_FLAG(Context, NDR_RFLAG_CF, dst.Value.Qwords[0] & 1);
}
if ((cnt & cntmask) == 1)
{
SET_FLAG(Context, REG_RFLAG_OF, ND_MSB(dst.Size, dst.Value.Qwords[0]) ^
GET_FLAG(Context, REG_RFLAG_CF));
SET_FLAG(Context, NDR_RFLAG_OF, ND_MSB(dst.Size, dst.Value.Qwords[0]) ^
GET_FLAG(Context, NDR_RFLAG_CF));