Andrei Vlad LUTAS
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fad9c7e35c
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BDDISASM v2.1.0 release - please consult the CHANGELOG for details about the modifications.
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2024-02-20 13:39:22 +02:00 |
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Ionel-Cristinel ANICHITEI
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727c87ecc4
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rsbddisasm: Update bindings
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2023-07-21 10:14:31 +03:00 |
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Andrei Vlad LUTAS
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f53cbc51e2
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Added support for new Intel ISA, per Intel® Architecture Instruction Set Extensions and Future Features document #319433-049 (June 2023): AVX-NNI-INT16, SHA512, SM3, SM4, TSE.
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2023-07-21 09:38:49 +03:00 |
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Ionel-Cristinel ANICHITEI
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be0969824c
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rsbddisasm: Update CHANGELOG
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2023-07-01 10:50:49 +03:00 |
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Ionel-Cristinel ANICHITEI
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fbb38f1518
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#82: Handle 0 in OpSize::from_raw
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2023-07-01 10:44:37 +03:00 |
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Anichitei Ionel-Cristinel
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935e2dfe5b
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Merge pull request #81 from bitdefender/ci-updates
CI actions updates
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2023-06-27 14:57:15 +03:00 |
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Anichitei Ionel-Cristinel
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b90ed49d33
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ci: Update setup-msbuild to 1.3
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2023-06-27 14:52:22 +03:00 |
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Anichitei Ionel-Cristinel
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b71ad7e6d9
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ci: Update upload-release-assets to v2.0.2
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2023-06-27 14:45:14 +03:00 |
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Anichitei Ionel-Cristinel
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aa362fa43e
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ci: Update checkout to v3
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2023-06-27 14:32:31 +03:00 |
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Andrei KISARI
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11e6a3e208
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Merge pull request #80 from akisari/master
Use SWIG to create bindings between C and Python.
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2023-06-26 11:42:01 +03:00 |
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Andrei KISARI
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1384893052
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Update copyright.
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2023-06-26 10:40:30 +03:00 |
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Andrei KISARI
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455286ca13
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Fix build.
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2023-06-22 15:14:05 +03:00 |
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Andrei KISARI
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4f182b2c11
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Use SWIG to create bindings between C and Python.
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2023-06-22 14:54:41 +03:00 |
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BITDEFENDER\vlutas
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096b583c25
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Tiny comment fix.
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2023-06-02 11:22:52 +03:00 |
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BITDEFENDER\vlutas
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f293c936ee
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Optimized ror/rol/rcr/rcl instruction emulation - don't use slow loops anymore.
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2023-06-01 21:28:30 +03:00 |
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Ionel-Cristinel ANICHITEI
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d16f1d8ba3
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bdshemu_fuzz: Update build scripts
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2023-04-05 11:06:10 +03:00 |
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Ionel-Cristinel ANICHITEI
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3beaac8ae2
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Update bindings
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2023-04-05 10:02:41 +03:00 |
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BITDEFENDER\vlutas
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124521beb5
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Added support for Intel AMX-COMPLEX instructions.
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2023-04-05 09:45:07 +03:00 |
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BITDEFENDER\vlutas
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ee6cdd6cb6
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Switched to a more parsing-friendly format for the instructions database, where individual components are sepparated by a semicolon.
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2023-02-09 10:54:45 +02:00 |
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BITDEFENDER\vlutas
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24665b0531
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Switched from nil to n/a naming for absent operands, as it is more obvious.
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2023-02-08 17:44:45 +02:00 |
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BITDEFENDER\vlutas
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fc6059109d
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Improved comments & improved vector length specifiers.
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2023-02-04 12:02:05 +02:00 |
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BITDEFENDER\vlutas
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0093439855
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Added some comments.
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2023-02-02 22:10:56 +02:00 |
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BITDEFENDER\vlutas
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089e6d5e7e
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Significant cleanup in disasmtool: the obsolete search functionality, and supplying registers for shemu from a file are no longer supported.
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2023-02-02 21:46:24 +02:00 |
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BITDEFENDER\vlutas
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61382e95f0
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Since all the shemu test file are synthetic and clean, I removed the password from the test archive.
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2022-12-16 15:17:39 +02:00 |
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Anichitei Ionel-Cristinel
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102b43dd00
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Merge pull request #78 from ianichitei/master
Fix `clang-cl` and `mingw` builds
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2022-12-05 14:25:25 +01:00 |
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Ionel-Cristinel ANICHITEI
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31457a0c02
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Fix clang-cl and mingw builds
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2022-12-05 12:10:30 +02:00 |
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Ionel-Cristinel ANICHITEI
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e67584241b
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Revert "Fix clang-cl and mingw builds"
This reverts commit add871993f.
I'll make a PR with these changes.
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2022-12-05 12:07:22 +02:00 |
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Ionel-Cristinel ANICHITEI
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add871993f
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Fix clang-cl and mingw builds
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2022-12-05 12:05:15 +02:00 |
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BITDEFENDER\vlutas
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ab3461fd06
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Regenerated test archive.
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2022-12-05 11:25:39 +02:00 |
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Ionel-Cristinel ANICHITEI
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00c9ebc341
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rsbddisasm: Add RMPQUERY
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2022-10-27 12:57:13 +03:00 |
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BITDEFENDER\vlutas
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7a254037b0
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Added support for AMD RMPQUERY instruction.
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2022-10-27 12:37:02 +03:00 |
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Ionel-Cristinel ANICHITEI
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f75e1e28cd
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bdshemu_fuzz: Build with -maes
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2022-10-04 13:31:02 +03:00 |
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Ionel-Cristinel ANICHITEI
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22d7c14c51
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rsbddisasm: Update bindings
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2022-10-04 13:17:54 +03:00 |
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BITDEFENDER\vlutas
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9ba1e6a2f9
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Added support for new Intel instructions, per Intel ISA extensions document #319433-046 (September 2022): PREFETCHITI, RAO-INT, CMPCCXADD, WRMSRNS, MSRLIST, AMX-FP16, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8.
Multiple minor fixes to existing instructions.
Moved x86 decoding tests in a separate directory & improved the test script.
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2022-10-04 12:22:59 +03:00 |
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BITDEFENDER\vlutas
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4596dbda51
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Add copyright info when auto-generating files.
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2022-09-10 23:15:00 +03:00 |
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BITDEFENDER\vlutas
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b109990ba2
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Removed some unneeded code.
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2022-08-09 20:15:30 +03:00 |
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BITDEFENDER\vlutas
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47da322ea5
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Improved upper bits handling for SSE/AVX operations.
Improved POPF handling when 16 bit operand size is used.
Fixed typo in PUNPCKLBW emulation.
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2022-08-09 20:02:45 +03:00 |
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BITDEFENDER\vlutas
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2fc491d51d
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Handle reserved bits in RFLAGS when setting the entire register value.
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2022-08-08 12:02:00 +03:00 |
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BITDEFENDER\vlutas
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f62c8a2238
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https://github.com/bitdefender/bddisasm/issues/70 - fixed OF setting on ROR.
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2022-08-01 15:46:38 +03:00 |
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BITDEFENDER\vlutas
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9c6b5429c9
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Fixed pybddisasm version.
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2022-08-01 14:17:07 +03:00 |
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BITDEFENDER\vlutas
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d3fd900903
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Fixed OF on SHL and SHR with one bit shifts.
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2022-08-01 14:13:27 +03:00 |
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BITDEFENDER\vlutas
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bf81c647e3
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Make sure all flags are set for CMPXCHG (this was left intentionally incomplete).
Make sure we clear upper bits of the 256/512 bit SSE register.
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2022-07-19 11:03:17 +03:00 |
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BITDEFENDER\vlutas
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6dda2c122c
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Make sure upper 32 bit of a CMOV destination register is cleared to 0 even if the condition is not satisfied
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2022-07-16 12:21:46 +03:00 |
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BITDEFENDER\vlutas
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1805a9edec
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Fixed flag setting for ADC, SBB, SAR and IMUL instructions.
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2022-07-14 13:42:37 +03:00 |
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vlutas
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e930d49713
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Merge pull request #54 from ianichitei/master
ci: Install Windows SDK 18362 when building on Windows
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2022-02-17 15:47:09 +02:00 |
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Anichitei Ionel-Cristinel
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f900388260
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Update rust.yml
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2022-02-17 11:37:15 +02:00 |
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Anichitei Ionel-Cristinel
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59255c4ea6
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Update ci.yml
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2022-02-17 11:33:26 +02:00 |
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Anichitei Ionel-Cristinel
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90820faba4
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ci: Setup Windows SDK 18362
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2022-02-17 11:12:30 +02:00 |
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Anichitei Ionel-Cristinel
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f0804645f3
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Update ci.yml
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2022-02-17 10:59:04 +02:00 |
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Anichitei Ionel-Cristinel
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4525860ec8
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Fix a typo in the install instructions
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2022-01-25 17:31:03 +02:00 |
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