Commit Graph

262 Commits (ba14104087acc65ebca806ba15e8a680fcbd505c)
 

Author SHA1 Message Date
Anichitei Ionel-Cristinel ba14104087
rsbddisasm: Update `bindgen` to 0.62.0
3 months ago
Andrei KISARI 698686ab14 Update headers for pybddisasm.
3 months ago
Anichitei Ionel-Cristinel fbe5c1375d
Update ci.yml
3 months ago
Anichitei Ionel-Cristinel 570fa2bb62
ci: Suppress cppcheck `objectIndex` warning
3 months ago
Andrei Vlad LUTAS fad9c7e35c BDDISASM v2.1.0 release - please consult the CHANGELOG for details about the modifications.
3 months ago
Ionel-Cristinel ANICHITEI 727c87ecc4 rsbddisasm: Update bindings
10 months ago
Andrei Vlad LUTAS f53cbc51e2 Added support for new Intel ISA, per Intel® Architecture Instruction Set Extensions and Future Features document #319433-049 (June 2023): AVX-NNI-INT16, SHA512, SM3, SM4, TSE.
10 months ago
Ionel-Cristinel ANICHITEI be0969824c rsbddisasm: Update CHANGELOG
11 months ago
Ionel-Cristinel ANICHITEI fbb38f1518 #82: Handle 0 in `OpSize::from_raw`
11 months ago
Anichitei Ionel-Cristinel 935e2dfe5b
Merge pull request #81 from bitdefender/ci-updates
11 months ago
Anichitei Ionel-Cristinel b90ed49d33
ci: Update `setup-msbuild` to 1.3
11 months ago
Anichitei Ionel-Cristinel b71ad7e6d9
ci: Update `upload-release-assets` to v2.0.2
11 months ago
Anichitei Ionel-Cristinel aa362fa43e
ci: Update `checkout` to v3
11 months ago
Andrei KISARI 11e6a3e208
Merge pull request #80 from akisari/master
11 months ago
Andrei KISARI 1384893052 Update copyright.
11 months ago
Andrei KISARI 455286ca13 Fix build.
11 months ago
Andrei KISARI 4f182b2c11 Use SWIG to create bindings between C and Python.
11 months ago
BITDEFENDER\vlutas 096b583c25 Tiny comment fix.
12 months ago
BITDEFENDER\vlutas f293c936ee Optimized ror/rol/rcr/rcl instruction emulation - don't use slow loops anymore.
12 months ago
Ionel-Cristinel ANICHITEI d16f1d8ba3 bdshemu_fuzz: Update build scripts
1 year ago
Ionel-Cristinel ANICHITEI 3beaac8ae2 Update bindings
1 year ago
BITDEFENDER\vlutas 124521beb5 Added support for Intel AMX-COMPLEX instructions.
1 year ago
BITDEFENDER\vlutas ee6cdd6cb6 Switched to a more parsing-friendly format for the instructions database, where individual components are sepparated by a semicolon.
1 year ago
BITDEFENDER\vlutas 24665b0531 Switched from nil to n/a naming for absent operands, as it is more obvious.
1 year ago
BITDEFENDER\vlutas fc6059109d Improved comments & improved vector length specifiers.
1 year ago
BITDEFENDER\vlutas 0093439855 Added some comments.
1 year ago
BITDEFENDER\vlutas 089e6d5e7e Significant cleanup in disasmtool: the obsolete search functionality, and supplying registers for shemu from a file are no longer supported.
1 year ago
BITDEFENDER\vlutas 61382e95f0 Since all the shemu test file are synthetic and clean, I removed the password from the test archive.
1 year ago
Anichitei Ionel-Cristinel 102b43dd00
Merge pull request #78 from ianichitei/master
1 year ago
Ionel-Cristinel ANICHITEI 31457a0c02 Fix `clang-cl` and `mingw` builds
1 year ago
Ionel-Cristinel ANICHITEI e67584241b Revert "Fix `clang-cl` and `mingw` builds"
1 year ago
Ionel-Cristinel ANICHITEI add871993f Fix `clang-cl` and `mingw` builds
1 year ago
BITDEFENDER\vlutas ab3461fd06 Regenerated test archive.
1 year ago
Ionel-Cristinel ANICHITEI 00c9ebc341 rsbddisasm: Add `RMPQUERY`
2 years ago
BITDEFENDER\vlutas 7a254037b0 Added support for AMD RMPQUERY instruction.
2 years ago
Ionel-Cristinel ANICHITEI f75e1e28cd bdshemu_fuzz: Build with `-maes`
2 years ago
Ionel-Cristinel ANICHITEI 22d7c14c51 rsbddisasm: Update bindings
2 years ago
BITDEFENDER\vlutas 9ba1e6a2f9 Added support for new Intel instructions, per Intel ISA extensions document #319433-046 (September 2022): PREFETCHITI, RAO-INT, CMPCCXADD, WRMSRNS, MSRLIST, AMX-FP16, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8.
2 years ago
BITDEFENDER\vlutas 4596dbda51 Add copyright info when auto-generating files.
2 years ago
BITDEFENDER\vlutas b109990ba2 Removed some unneeded code.
2 years ago
BITDEFENDER\vlutas 47da322ea5 Improved upper bits handling for SSE/AVX operations.
2 years ago
BITDEFENDER\vlutas 2fc491d51d Handle reserved bits in RFLAGS when setting the entire register value.
2 years ago
BITDEFENDER\vlutas f62c8a2238 https://github.com/bitdefender/bddisasm/issues/70 - fixed OF setting on ROR.
2 years ago
BITDEFENDER\vlutas 9c6b5429c9 Fixed pybddisasm version.
2 years ago
BITDEFENDER\vlutas d3fd900903 Fixed OF on SHL and SHR with one bit shifts.
2 years ago
BITDEFENDER\vlutas bf81c647e3 Make sure all flags are set for CMPXCHG (this was left intentionally incomplete).
2 years ago
BITDEFENDER\vlutas 6dda2c122c Make sure upper 32 bit of a CMOV destination register is cleared to 0 even if the condition is not satisfied
2 years ago
BITDEFENDER\vlutas 1805a9edec Fixed flag setting for ADC, SBB, SAR and IMUL instructions.
2 years ago
vlutas e930d49713
Merge pull request #54 from ianichitei/master
2 years ago
Anichitei Ionel-Cristinel f900388260
Update rust.yml
2 years ago