Commit Graph

13 Commits (master)

Author SHA1 Message Date
Andrei Vlad LUTAS fad9c7e35c BDDISASM v2.1.0 release - please consult the CHANGELOG for details about the modifications.
3 months ago
Andrei Vlad LUTAS f53cbc51e2 Added support for new Intel ISA, per Intel® Architecture Instruction Set Extensions and Future Features document #319433-049 (June 2023): AVX-NNI-INT16, SHA512, SM3, SM4, TSE.
10 months ago
BITDEFENDER\vlutas 124521beb5 Added support for Intel AMX-COMPLEX instructions.
1 year ago
BITDEFENDER\vlutas 24665b0531 Switched from nil to n/a naming for absent operands, as it is more obvious.
1 year ago
BITDEFENDER\vlutas 7a254037b0 Added support for AMD RMPQUERY instruction.
2 years ago
BITDEFENDER\vlutas 9ba1e6a2f9 Added support for new Intel instructions, per Intel ISA extensions document #319433-046 (September 2022): PREFETCHITI, RAO-INT, CMPCCXADD, WRMSRNS, MSRLIST, AMX-FP16, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8.
2 years ago
Andrei Vlad LUTAS fccf11915d Added support for Intel FRED and LKGS instructions.
3 years ago
Andrei Vlad LUTAS 58197cc518 Removed support for PCOMMIT and CL1INVMB (not implemented by any x86/x64 CPUs), and marked MOV to/from test registers as being invalid in long mode.
4 years ago
Andrei Vlad LUTAS 9652450125 Added support for UINTR, HRESET and AVX-VNNI instructions, as per Intel® Architecture Instruction Set Extensions Programming Reference 41 (October 2020).
4 years ago
Andrei Vlad LUTAS 4f8b030ddd Added support for Intel Key Locker instructions, as per https://software.intel.com/content/www/us/en/develop/download/intel-key-locker-specification.html.
4 years ago
Andrei Vlad LUTAS 52ed638c13 Fixed some typos.
4 years ago
Andrei Vlad LUTAS 8392c97f97 Use the documented byte granularity for cache-line accesses.
4 years ago
Andrei Vlad LUTAS 698ba367a1 Initial commit.
4 years ago