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@ -1496,7 +1496,7 @@ const ND_INSTRUCTION gInstructions[2554] =
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OP(ND_OPT_F, ND_OPS_v, ND_OPF_DEFAULT|ND_OPF_W, 0, 0),
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},
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// Pos:110 Instruction:"CLDEMOTE Mcl" Encoding:"NP 0x0F 0x1C /0:mem"/"M"
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// Pos:110 Instruction:"CLDEMOTE Mb" Encoding:"NP 0x0F 0x1C /0:mem"/"M"
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{
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ND_INS_CLDEMOTE, ND_CAT_CLDEMOTE, ND_SET_CLDEMOTE, 68,
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ND_MOD_ANY,
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@ -1505,7 +1505,7 @@ const ND_INSTRUCTION gInstructions[2554] =
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0,
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0,
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0,
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OP(ND_OPT_M, ND_OPS_cl, ND_OPF_W, 0, 0),
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OP(ND_OPT_M, ND_OPS_b, ND_OPF_W, 0, 0),
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},
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// Pos:111 Instruction:"CLEVICT0 M?" Encoding:"vex m:1 p:3 0xAE /7:mem"/"M"
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@ -1532,7 +1532,7 @@ const ND_INSTRUCTION gInstructions[2554] =
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OP(ND_OPT_M, ND_OPS_unknown, ND_OPF_N, 0, 0),
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},
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// Pos:113 Instruction:"CLFLUSH Mcl" Encoding:"NP 0x0F 0xAE /7:mem"/"M"
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// Pos:113 Instruction:"CLFLUSH Mb" Encoding:"NP 0x0F 0xAE /7:mem"/"M"
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{
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ND_INS_CLFLUSH, ND_CAT_MISC, ND_SET_CLFSH, 71,
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ND_MOD_ANY,
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@ -1541,10 +1541,10 @@ const ND_INSTRUCTION gInstructions[2554] =
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0,
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0,
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0,
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OP(ND_OPT_M, ND_OPS_cl, ND_OPF_R, 0, 0),
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OP(ND_OPT_M, ND_OPS_b, ND_OPF_R, 0, 0),
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},
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// Pos:114 Instruction:"CLFLUSHOPT Mcl" Encoding:"0x66 0x0F 0xAE /7:mem"/"M"
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// Pos:114 Instruction:"CLFLUSHOPT Mb" Encoding:"0x66 0x0F 0xAE /7:mem"/"M"
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{
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ND_INS_CLFLUSHOPT, ND_CAT_MISC, ND_SET_CLFSHOPT, 72,
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ND_MOD_ANY,
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@ -1553,7 +1553,7 @@ const ND_INSTRUCTION gInstructions[2554] =
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0,
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0,
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0,
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OP(ND_OPT_M, ND_OPS_cl, ND_OPF_R, 0, 0),
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OP(ND_OPT_M, ND_OPS_b, ND_OPF_R, 0, 0),
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},
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// Pos:115 Instruction:"CLGI" Encoding:"0x0F 0x01 /0xDD"/""
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@ -1581,9 +1581,9 @@ const ND_INSTRUCTION gInstructions[2554] =
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// Pos:117 Instruction:"CLRSSBSY Mq" Encoding:"0xF3 0x0F 0xAE /6:mem"/"M"
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{
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ND_INS_CLRSSBSY, ND_CAT_CET, ND_SET_CET, 75,
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ND_INS_CLRSSBSY, ND_CAT_CET, ND_SET_CET_SS, 75,
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ND_MOD_ANY,
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0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET,
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0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS,
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0,
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0|REG_RFLAG_CF,
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0,
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@ -1604,7 +1604,7 @@ const ND_INSTRUCTION gInstructions[2554] =
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OP(ND_OPT_CR_0, ND_OPS_yf, ND_OPF_DEFAULT|ND_OPF_W, 0, 0),
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},
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// Pos:119 Instruction:"CLWB Mcl" Encoding:"0x66 0x0F 0xAE /6:mem"/"M"
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// Pos:119 Instruction:"CLWB Mb" Encoding:"0x66 0x0F 0xAE /6:mem"/"M"
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{
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ND_INS_CLWB, ND_CAT_MISC, ND_SET_CLWB, 77,
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ND_MOD_ANY,
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@ -1613,7 +1613,7 @@ const ND_INSTRUCTION gInstructions[2554] =
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0,
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0,
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0,
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OP(ND_OPT_M, ND_OPS_cl, ND_OPF_W, 0, 0),
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OP(ND_OPT_M, ND_OPS_b, ND_OPF_W, 0, 0),
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},
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// Pos:120 Instruction:"CLZERO" Encoding:"0x0F 0x01 /0xFC"/""
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@ -3046,9 +3046,9 @@ const ND_INSTRUCTION gInstructions[2554] =
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// Pos:224 Instruction:"ENDBR32" Encoding:"a0xF3 0x0F 0x1E /0xFB"/""
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{
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ND_INS_ENDBR, ND_CAT_CET, ND_SET_CET, 154,
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ND_INS_ENDBR, ND_CAT_CET, ND_SET_CET_IBT, 154,
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ND_MOD_ANY,
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0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET,
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0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_IBT,
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0,
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0,
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0,
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@ -3057,9 +3057,9 @@ const ND_INSTRUCTION gInstructions[2554] =
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// Pos:225 Instruction:"ENDBR64" Encoding:"a0xF3 0x0F 0x1E /0xFA"/""
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{
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ND_INS_ENDBR, ND_CAT_CET, ND_SET_CET, 155,
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ND_INS_ENDBR, ND_CAT_CET, ND_SET_CET_IBT, 155,
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ND_MOD_ANY,
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0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET,
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0, 0, ND_OPS_CNT(0, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_IBT,
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0,
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0,
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0,
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@ -5583,9 +5583,9 @@ const ND_INSTRUCTION gInstructions[2554] =
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// Pos:412 Instruction:"INCSSPD Rd" Encoding:"0xF3 0x0F 0xAE /5:reg"/"M"
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{
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ND_INS_INCSSP, ND_CAT_CET, ND_SET_CET, 269,
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ND_INS_INCSSP, ND_CAT_CET, ND_SET_CET_SS, 269,
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ND_MOD_ANY,
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0, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET,
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0, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_SS,
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0,
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0,
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0,
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@ -5597,9 +5597,9 @@ const ND_INSTRUCTION gInstructions[2554] =
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// Pos:413 Instruction:"INCSSPQ Rq" Encoding:"0xF3 rexw 0x0F 0xAE /5:reg"/"M"
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{
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ND_INS_INCSSP, ND_CAT_CET, ND_SET_CET, 270,
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ND_INS_INCSSP, ND_CAT_CET, ND_SET_CET_SS, 270,
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ND_MOD_ANY,
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0, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET,
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0, 0, ND_OPS_CNT(1, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_SS,
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0,
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0,
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0,
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@ -13232,7 +13232,7 @@ const ND_INSTRUCTION gInstructions[2554] =
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OP(ND_OPT_W, ND_OPS_x, ND_OPF_R, 0, 0),
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},
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// Pos:982 Instruction:"PREFETCH Mcl" Encoding:"0x0F 0x0D /4:mem"/"M"
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// Pos:982 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /4:mem"/"M"
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{
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ND_INS_PREFETCH, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 591,
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ND_MOD_ANY,
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@ -13241,10 +13241,10 @@ const ND_INSTRUCTION gInstructions[2554] =
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0,
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0,
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0,
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OP(ND_OPT_M, ND_OPS_cl, ND_OPF_R, 0, 0),
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OP(ND_OPT_M, ND_OPS_b, ND_OPF_R, 0, 0),
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},
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// Pos:983 Instruction:"PREFETCH Mcl" Encoding:"0x0F 0x0D /5:mem"/"M"
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// Pos:983 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /5:mem"/"M"
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{
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ND_INS_PREFETCH, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 591,
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ND_MOD_ANY,
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@ -13253,10 +13253,10 @@ const ND_INSTRUCTION gInstructions[2554] =
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0,
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0,
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0,
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OP(ND_OPT_M, ND_OPS_cl, ND_OPF_R, 0, 0),
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OP(ND_OPT_M, ND_OPS_b, ND_OPF_R, 0, 0),
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},
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// Pos:984 Instruction:"PREFETCH Mcl" Encoding:"0x0F 0x0D /6:mem"/"M"
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// Pos:984 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /6:mem"/"M"
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{
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ND_INS_PREFETCH, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 591,
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ND_MOD_ANY,
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@ -13265,10 +13265,10 @@ const ND_INSTRUCTION gInstructions[2554] =
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0,
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0,
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0,
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OP(ND_OPT_M, ND_OPS_cl, ND_OPF_R, 0, 0),
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OP(ND_OPT_M, ND_OPS_b, ND_OPF_R, 0, 0),
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},
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// Pos:985 Instruction:"PREFETCH Mcl" Encoding:"0x0F 0x0D /7:mem"/"M"
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// Pos:985 Instruction:"PREFETCH Mb" Encoding:"0x0F 0x0D /7:mem"/"M"
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{
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ND_INS_PREFETCH, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 591,
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ND_MOD_ANY,
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@ -13277,10 +13277,10 @@ const ND_INSTRUCTION gInstructions[2554] =
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0,
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0,
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0,
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OP(ND_OPT_M, ND_OPS_cl, ND_OPF_R, 0, 0),
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OP(ND_OPT_M, ND_OPS_b, ND_OPF_R, 0, 0),
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},
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// Pos:986 Instruction:"PREFETCHE Mcl" Encoding:"0x0F 0x0D /0:mem"/"M"
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// Pos:986 Instruction:"PREFETCHE Mb" Encoding:"0x0F 0x0D /0:mem"/"M"
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{
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ND_INS_PREFETCHE, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 592,
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ND_MOD_ANY,
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@ -13289,10 +13289,10 @@ const ND_INSTRUCTION gInstructions[2554] =
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0,
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0,
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0,
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OP(ND_OPT_M, ND_OPS_cl, ND_OPF_R, 0, 0),
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OP(ND_OPT_M, ND_OPS_b, ND_OPF_R, 0, 0),
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},
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// Pos:987 Instruction:"PREFETCHM Mcl" Encoding:"0x0F 0x0D /3:mem"/"M"
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// Pos:987 Instruction:"PREFETCHM Mb" Encoding:"0x0F 0x0D /3:mem"/"M"
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{
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ND_INS_PREFETCHM, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 593,
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ND_MOD_ANY,
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@ -13301,10 +13301,10 @@ const ND_INSTRUCTION gInstructions[2554] =
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0,
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0,
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0,
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OP(ND_OPT_M, ND_OPS_cl, ND_OPF_R, 0, 0),
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OP(ND_OPT_M, ND_OPS_b, ND_OPF_R, 0, 0),
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},
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// Pos:988 Instruction:"PREFETCHNTA Mcl" Encoding:"0x0F 0x18 /0:mem"/"M"
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// Pos:988 Instruction:"PREFETCHNTA Mb" Encoding:"0x0F 0x18 /0:mem"/"M"
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{
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ND_INS_PREFETCHNTA, ND_CAT_PREFETCH, ND_SET_SSE, 594,
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ND_MOD_ANY,
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@ -13313,10 +13313,10 @@ const ND_INSTRUCTION gInstructions[2554] =
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0,
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0,
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0,
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OP(ND_OPT_M, ND_OPS_cl, ND_OPF_R, 0, 0),
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OP(ND_OPT_M, ND_OPS_b, ND_OPF_R, 0, 0),
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},
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// Pos:989 Instruction:"PREFETCHT0 Mcl" Encoding:"0x0F 0x18 /1:mem"/"M"
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// Pos:989 Instruction:"PREFETCHT0 Mb" Encoding:"0x0F 0x18 /1:mem"/"M"
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{
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ND_INS_PREFETCHT0, ND_CAT_PREFETCH, ND_SET_SSE, 595,
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ND_MOD_ANY,
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@ -13325,10 +13325,10 @@ const ND_INSTRUCTION gInstructions[2554] =
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0,
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0,
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0,
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OP(ND_OPT_M, ND_OPS_cl, ND_OPF_R, 0, 0),
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OP(ND_OPT_M, ND_OPS_b, ND_OPF_R, 0, 0),
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},
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// Pos:990 Instruction:"PREFETCHT1 Mcl" Encoding:"0x0F 0x18 /2:mem"/"M"
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// Pos:990 Instruction:"PREFETCHT1 Mb" Encoding:"0x0F 0x18 /2:mem"/"M"
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{
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ND_INS_PREFETCHT1, ND_CAT_PREFETCH, ND_SET_SSE, 596,
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ND_MOD_ANY,
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@ -13337,10 +13337,10 @@ const ND_INSTRUCTION gInstructions[2554] =
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0,
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0,
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0,
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OP(ND_OPT_M, ND_OPS_cl, ND_OPF_R, 0, 0),
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OP(ND_OPT_M, ND_OPS_b, ND_OPF_R, 0, 0),
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},
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// Pos:991 Instruction:"PREFETCHT2 Mcl" Encoding:"0x0F 0x18 /3:mem"/"M"
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// Pos:991 Instruction:"PREFETCHT2 Mb" Encoding:"0x0F 0x18 /3:mem"/"M"
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{
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ND_INS_PREFETCHT2, ND_CAT_PREFETCH, ND_SET_SSE, 597,
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ND_MOD_ANY,
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@ -13349,10 +13349,10 @@ const ND_INSTRUCTION gInstructions[2554] =
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0,
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0,
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0,
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OP(ND_OPT_M, ND_OPS_cl, ND_OPF_R, 0, 0),
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OP(ND_OPT_M, ND_OPS_b, ND_OPF_R, 0, 0),
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},
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// Pos:992 Instruction:"PREFETCHW Mcl" Encoding:"0x0F 0x0D /1:mem"/"M"
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// Pos:992 Instruction:"PREFETCHW Mb" Encoding:"0x0F 0x0D /1:mem"/"M"
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{
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ND_INS_PREFETCHW, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 598,
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ND_MOD_ANY,
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@ -13361,10 +13361,10 @@ const ND_INSTRUCTION gInstructions[2554] =
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0,
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0,
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0,
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OP(ND_OPT_M, ND_OPS_cl, ND_OPF_R, 0, 0),
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OP(ND_OPT_M, ND_OPS_b, ND_OPF_R, 0, 0),
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},
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// Pos:993 Instruction:"PREFETCHWT1 Mcl" Encoding:"0x0F 0x0D /2:mem"/"M"
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// Pos:993 Instruction:"PREFETCHWT1 Mb" Encoding:"0x0F 0x0D /2:mem"/"M"
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{
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ND_INS_PREFETCHWT1, ND_CAT_PREFETCH, ND_SET_PREFETCH_NOP, 599,
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ND_MOD_ANY,
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@ -13373,7 +13373,7 @@ const ND_INSTRUCTION gInstructions[2554] =
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0,
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0,
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0,
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OP(ND_OPT_M, ND_OPS_cl, ND_OPF_R, 0, 0),
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OP(ND_OPT_M, ND_OPS_b, ND_OPF_R, 0, 0),
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},
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// Pos:994 Instruction:"PSADBW Pq,Qq" Encoding:"NP 0x0F 0xF6 /r"/"RM"
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@ -15119,9 +15119,9 @@ const ND_INSTRUCTION gInstructions[2554] =
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// Pos:1126 Instruction:"RDSSPD Rd" Encoding:"a0xF3 0x0F 0x1E /1:reg"/"M"
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{
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ND_INS_RSSSP, ND_CAT_CET, ND_SET_CET, 660,
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ND_INS_RSSSP, ND_CAT_CET, ND_SET_CET_SS, 660,
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ND_MOD_ANY,
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0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET,
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0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_SS,
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0,
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0,
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0,
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@ -15132,9 +15132,9 @@ const ND_INSTRUCTION gInstructions[2554] =
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// Pos:1127 Instruction:"RDSSPQ Rq" Encoding:"a0xF3 rexw 0x0F 0x1E /1:reg"/"M"
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{
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ND_INS_RSSSP, ND_CAT_CET, ND_SET_CET, 661,
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ND_INS_RSSSP, ND_CAT_CET, ND_SET_CET_SS, 661,
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ND_MOD_ANY,
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0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET,
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0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_SS,
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0,
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0,
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0,
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@ -15568,9 +15568,9 @@ const ND_INSTRUCTION gInstructions[2554] =
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// Pos:1158 Instruction:"RSTORSSP Mq" Encoding:"0xF3 0x0F 0x01 /5:mem"/"M"
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{
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ND_INS_RSTORSSP, ND_CAT_CET, ND_SET_CET, 680,
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ND_INS_RSTORSSP, ND_CAT_CET, ND_SET_CET_SS, 680,
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ND_MOD_ANY,
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0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET,
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0, 0, ND_OPS_CNT(1, 1), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS,
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0,
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0|REG_RFLAG_CF,
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0,
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@ -15801,9 +15801,9 @@ const ND_INSTRUCTION gInstructions[2554] =
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// Pos:1175 Instruction:"SAVEPREVSSP" Encoding:"0xF3 0x0F 0x01 /0xEA"/""
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{
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ND_INS_SAVEPREVSSP, ND_CAT_CET, ND_SET_CET, 687,
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ND_INS_SAVEPREVSSP, ND_CAT_CET, ND_SET_CET_SS, 687,
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ND_MOD_ANY,
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0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET,
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0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_MODRM, ND_CFF_CET_SS,
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0|REG_RFLAG_CF,
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0,
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0,
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@ -16284,9 +16284,9 @@ const ND_INSTRUCTION gInstructions[2554] =
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// Pos:1210 Instruction:"SETSSBSY" Encoding:"0xF3 0x0F 0x01 /0xE8"/""
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{
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ND_INS_SETSSBSY, ND_CAT_CET, ND_SET_CET, 709,
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ND_INS_SETSSBSY, ND_CAT_CET, ND_SET_CET_SS, 709,
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|
ND_MOD_ANY,
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|
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0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET,
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0, 0, ND_OPS_CNT(0, 2), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS,
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|
0,
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|
0,
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|
0,
|
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|
|
@ -34591,9 +34591,9 @@ const ND_INSTRUCTION gInstructions[2554] =
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// Pos:2497 Instruction:"WRSSD My,Gy" Encoding:"NP 0x0F 0x38 0xF6 /r:mem"/"MR"
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|
|
{
|
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|
|
ND_INS_WRSS, ND_CAT_CET, ND_SET_CET, 1523,
|
|
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|
|
ND_INS_WRSS, ND_CAT_CET, ND_SET_CET_SS, 1523,
|
|
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|
|
ND_MOD_ANY,
|
|
|
|
|
0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET,
|
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|
|
0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS,
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|
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|
|
0,
|
|
|
|
|
0,
|
|
|
|
|
0,
|
|
|
|
@ -34604,9 +34604,9 @@ const ND_INSTRUCTION gInstructions[2554] =
|
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|
|
|
|
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|
|
// Pos:2498 Instruction:"WRSSQ My,Gy" Encoding:"rexw NP 0x0F 0x38 0xF6 /r:mem"/"MR"
|
|
|
|
|
{
|
|
|
|
|
ND_INS_WRSS, ND_CAT_CET, ND_SET_CET, 1524,
|
|
|
|
|
ND_INS_WRSS, ND_CAT_CET, ND_SET_CET_SS, 1524,
|
|
|
|
|
ND_MOD_ANY,
|
|
|
|
|
0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET,
|
|
|
|
|
0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS,
|
|
|
|
|
0,
|
|
|
|
|
0,
|
|
|
|
|
0,
|
|
|
|
@ -34617,9 +34617,9 @@ const ND_INSTRUCTION gInstructions[2554] =
|
|
|
|
|
|
|
|
|
|
// Pos:2499 Instruction:"WRUSSD My,Gy" Encoding:"0x66 0x0F 0x38 0xF5 /r:mem"/"MR"
|
|
|
|
|
{
|
|
|
|
|
ND_INS_WRUSS, ND_CAT_CET, ND_SET_CET, 1525,
|
|
|
|
|
ND_INS_WRUSS, ND_CAT_CET, ND_SET_CET_SS, 1525,
|
|
|
|
|
ND_MOD_ANY,
|
|
|
|
|
0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET,
|
|
|
|
|
0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS,
|
|
|
|
|
0,
|
|
|
|
|
0,
|
|
|
|
|
0,
|
|
|
|
@ -34630,9 +34630,9 @@ const ND_INSTRUCTION gInstructions[2554] =
|
|
|
|
|
|
|
|
|
|
// Pos:2500 Instruction:"WRUSSQ My,Gy" Encoding:"rexw 0x66 0x0F 0x38 0xF5 /r:mem"/"MR"
|
|
|
|
|
{
|
|
|
|
|
ND_INS_WRUSS, ND_CAT_CET, ND_SET_CET, 1526,
|
|
|
|
|
ND_INS_WRUSS, ND_CAT_CET, ND_SET_CET_SS, 1526,
|
|
|
|
|
ND_MOD_ANY,
|
|
|
|
|
0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET,
|
|
|
|
|
0, 0, ND_OPS_CNT(2, 0), 0, 0, 0, 0, 0, 0, ND_FLAG_SHS|ND_FLAG_MODRM, ND_CFF_CET_SS,
|
|
|
|
|
0,
|
|
|
|
|
0,
|
|
|
|
|
0,
|
|
|
|
|