arno
/
bddisasm
mirror of https://github.com/bitdefender/bddisasm.git
1
0
Fork 0
Code Issues Releases Wiki Activity
280 Commits
2 Branches
14 Tags
7.1 MiB
Branches Tags
${ item.name }
Create tag ${ searchTerm }
Create branch ${ searchTerm }
from 'master'
${ noResults }
Commit Graph

23 Commits (master)

Author SHA1 Message Date
Andrei Vlad LUTAS 44dc7c6cbb Updated changelog & Python binding version.
1 month ago
Andrei Vlad LUTAS 37a8c94bc7 Applied some of the syntax recomandations from https://cdrdv2.intel.com/v1/dl/getContent/817241.
2 months ago
Andrei Vlad LUTAS 02cbe6a298 https://github.com/bitdefender/bddisasm/issues/87 - added missing `R` access for the `rIP` operand for `SYSCALL` instructions; added missing `SCS`, `rCX` and `rDX` operands for `SYSEXIT` instruction.
2 months ago
Andrei Vlad LUTAS f6f93c4112 Fixed pybddisasm version.
2 months ago
Andrei KISARI 698686ab14 Update headers for pybddisasm.
3 months ago
Andrei Vlad LUTAS fad9c7e35c BDDISASM v2.1.0 release - please consult the CHANGELOG for details about the modifications.
3 months ago
Andrei Vlad LUTAS f53cbc51e2 Added support for new Intel ISA, per Intel® Architecture Instruction Set Extensions and Future Features document #319433-049 (June 2023): AVX-NNI-INT16, SHA512, SM3, SM4, TSE.
10 months ago
Andrei KISARI 1384893052 Update copyright.
11 months ago
Andrei KISARI 455286ca13 Fix build.
11 months ago
Andrei KISARI 4f182b2c11 Use SWIG to create bindings between C and Python.
11 months ago
BITDEFENDER\vlutas 124521beb5 Added support for Intel AMX-COMPLEX instructions.
1 year ago
BITDEFENDER\vlutas 7a254037b0 Added support for AMD RMPQUERY instruction.
2 years ago
BITDEFENDER\vlutas 9ba1e6a2f9 Added support for new Intel instructions, per Intel ISA extensions document #319433-046 (September 2022): PREFETCHITI, RAO-INT, CMPCCXADD, WRMSRNS, MSRLIST, AMX-FP16, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8.
2 years ago
BITDEFENDER\vlutas 9c6b5429c9 Fixed pybddisasm version.
2 years ago
BITDEFENDER\vlutas bf81c647e3 Make sure all flags are set for CMPXCHG (this was left intentionally incomplete).
2 years ago
BITDEFENDER\vlutas 6dda2c122c Make sure upper 32 bit of a CMOV destination register is cleared to 0 even if the condition is not satisfied
2 years ago
BITDEFENDER\vlutas 1805a9edec Fixed flag setting for ADC, SBB, SAR and IMUL instructions.
2 years ago
BITDEFENDER\vlutas fe6a937f51 Switched to internally defined types.
2 years ago
BITDEFENDER\vlutas 63e3ee22a9 Fixed High8 handling in NdGetFullAccessMap.
2 years ago
BITDEFENDER\vlutas 2f50ce9b4e Improved REG_ID macros - make sure we include block addressing and High8 designator in the reg ID. Alsom, make sure the register size fits in, since the new tile register can be 1K in size, which previously overflowed...
2 years ago
BITDEFENDER\vlutas 7572adaeba Fixed INSTRUX size in setup.py.
3 years ago
BITDEFENDER\vlutas 433e723e07 Implemented a reverse oprand lookup table. It holds pointers to relevant operands inside INSTRUX, for quick lookup.
3 years ago
Ionel-Cristinel ANICHITEI af3d23e3ff Move pybddisasm to the bindings directory
3 years ago