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Convert some complex conditions to branchless form
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21da6eddaf
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@ -3813,22 +3813,27 @@ NdGetEffectiveAddrAndOpMode(
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static const ND_UINT8 szLut[3] = { ND_SIZE_16BIT, ND_SIZE_32BIT, ND_SIZE_64BIT };
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ND_BOOL w64, f64, d64, has66;
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if ((ND_CODE_64 != Instrux->DefCode) && !!(Instrux->Attributes & ND_FLAG_IWO64))
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// Branchless form of (ND_CODE_64 != Instrux->DefCode) && !!(Instrux->Attributes & ND_FLAG_IWO64)
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if (((ND_CODE_64 ^ Instrux->DefCode) * (Instrux->Attributes & ND_FLAG_IWO64)) != 0)
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{
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// Some instructions ignore VEX/EVEX.W field outside 64 bit mode, and treat it as 0.
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Instrux->Exs.w = 0;
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}
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// Extract the flags.
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w64 = (0 != Instrux->Exs.w) && !(Instrux->Attributes & ND_FLAG_WIG);
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// Branchless form of (0 != Instrux->Exs.w) && !(Instrux->Attributes & ND_FLAG_WIG)
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w64 = (0 != Instrux->Exs.w) * !(Instrux->Attributes & ND_FLAG_WIG);
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// In 64 bit mode, the operand is forced to 64 bit. Size-changing prefixes are ignored.
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f64 = 0 != (Instrux->Attributes & ND_FLAG_F64) && (ND_VEND_AMD != Instrux->VendMode);
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// Branchless form of 0 != (Instrux->Attributes & ND_FLAG_F64) && (ND_VEND_AMD != Instrux->VendMode)
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f64 = 0 != ((Instrux->Attributes & ND_FLAG_F64) * (ND_VEND_AMD ^ Instrux->VendMode));
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// In 64 bit mode, the operand defaults to 64 bit. No 32 bit form of the instruction exists. Note that on AMD,
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// only default 64 bit operands exist, even for branches - no operand is forced to 64 bit.
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d64 = (0 != (Instrux->Attributes & ND_FLAG_D64)) ||
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(0 != (Instrux->Attributes & ND_FLAG_F64) && (ND_VEND_AMD == Instrux->VendMode));
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// Branchless form of (0 != (Instrux->Attributes & ND_FLAG_D64)) ||
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// (0 != (Instrux->Attributes & ND_FLAG_F64) && (ND_VEND_AMD == Instrux->VendMode));
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d64 = (Instrux->Attributes & ND_FLAG_D64) +
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((Instrux->Attributes & ND_FLAG_F64) * (ND_VEND_AMD == Instrux->VendMode));
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// Check if 0x66 is indeed interpreted as a size changing prefix. Note that if 0x66 is a mandatory prefix,
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// then it won't be interpreted as a size changing prefix. However, there is an exception: MOVBE and CRC32
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