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https://github.com/bitdefender/bddisasm.git
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Use array for regular operand sizes
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Turo Lamminen
parent
c877b5007f
commit
9fb3c9cfe8
@ -1422,6 +1422,74 @@ NdParseMemoryOperand3264(
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}
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static const ND_OPERAND_SIZE operandSizes[] =
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{
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0, // none
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0, // 0
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0, // asz
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0, // ssz
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0, // a
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0, // c
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ND_SIZE_8BIT, // b, 8 bits
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ND_SIZE_16BIT, // w, 16 bits
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ND_SIZE_32BIT, // d, 32 bits
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ND_SIZE_64BIT, // q, 64 bits
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ND_SIZE_128BIT, // dq, 128 bits
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ND_SIZE_256BIT, // qq, 256 bits
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ND_SIZE_512BIT, // oq, 512 bits
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0, // v
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0, // y
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0, // yf
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0, // z
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0, // s
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0, // p
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ND_SIZE_80BIT, // fa, 80 bits packed BCD
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ND_SIZE_16BIT, // fw, 16 bits real number
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ND_SIZE_32BIT, // fd, 32 bits real number
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ND_SIZE_64BIT, // fq, 64 bits real number
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ND_SIZE_80BIT, // ft, 80 bits real number
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0, // fe
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0, // fs
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0, // l
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ND_SIZE_4096BIT, // rx, 512 bytes extended state
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ND_SIZE_CACHE_LINE, // cl, The size of one cache line
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ND_SIZE_64BIT, // sd, 128 bits scalar element (double precision)
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ND_SIZE_32BIT, // ss, 128 bits scalar element (single precision)
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ND_SIZE_16BIT, // sh, FP16 Scalar element
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0, // ps
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0, // pd
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0, // ph
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0, // ev
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0, // qv
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0, // hv
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0, // x
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0, // uv
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0, // fv
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ND_SIZE_1KB, // t, Tile register. The actual size depends on how the TILECFG register has been programmed,
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// but it can be up to 1K in size
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ND_SIZE_384BIT, // 384, 384 bit Key Locker handle
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ND_SIZE_512BIT, // 512, 512 bit Key Locker handle
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ND_SIZE_4096BIT, // 4096, 64 entries x 64 bit per entry = 4096 bit MSR address/value list
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0, // v2
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0, // v3
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0, // v4
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0, // v5
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0, // v8
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12, // 12, SAVPREVSSP instruction reads/writes 4 + 8 bytes from the shadow stack
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0, // mib, MIB addressing, the base & the index are used to form a pointer
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0, // vm32x
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0, // vm32y
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0, // vm32z
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0, // vm32h
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0, // vm32n
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0, // vm64x
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0, // vm64y
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0, // vm64z
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0, // vm64h
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0, // vm64n
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ND_SIZE_UNKNOWN // unknown
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};
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//
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// NdParseOperand
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@ -1473,10 +1541,11 @@ NdParseOperand(
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// Implicit operand access, by default.
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operand->Encoding = ND_OPE_S;
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//
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// Fill in operand size.
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//
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// Regular cases come from a table.
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size = operandSizes[ops];
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switch (ops)
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{
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case ND_OPS_asz:
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@ -1490,68 +1559,30 @@ NdParseOperand(
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break;
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case ND_OPS_0:
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// No memory access. 0 operand size.
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size = 0;
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break;
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case ND_OPS_b:
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// 8 bits.
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size = ND_SIZE_8BIT;
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break;
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case ND_OPS_w:
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// 16 bits.
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size = ND_SIZE_16BIT;
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break;
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case ND_OPS_d:
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// 32 bits.
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size = ND_SIZE_32BIT;
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break;
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case ND_OPS_q:
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// 64 bits.
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size = ND_SIZE_64BIT;
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break;
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case ND_OPS_dq:
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// 128 bits.
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size = ND_SIZE_128BIT;
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break;
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case ND_OPS_qq:
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// 256 bits.
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size = ND_SIZE_256BIT;
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break;
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case ND_OPS_oq:
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// 512 bits.
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size = ND_SIZE_512BIT;
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break;
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case ND_OPS_fa:
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// 80 bits packed BCD.
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size = ND_SIZE_80BIT;
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break;
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case ND_OPS_fw:
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// 16 bits real number.
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size = ND_SIZE_16BIT;
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break;
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case ND_OPS_fd:
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// 32 bits real number.
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size = ND_SIZE_32BIT;
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break;
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case ND_OPS_fq:
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// 64 bits real number.
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size = ND_SIZE_64BIT;
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break;
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case ND_OPS_ft:
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// 80 bits real number.
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size = ND_SIZE_80BIT;
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case ND_OPS_rx:
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case ND_OPS_cl:
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case ND_OPS_sd:
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case ND_OPS_ss:
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case ND_OPS_sh:
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case ND_OPS_mib:
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case ND_OPS_12:
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case ND_OPS_t:
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case ND_OPS_384:
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case ND_OPS_512:
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case ND_OPS_4096:
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case ND_OPS_unknown:
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break;
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case ND_OPS_fe:
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@ -1564,16 +1595,6 @@ NdParseOperand(
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size = (Instrux->EfOpMode == ND_OPSZ_16) ? ND_SIZE_752BIT : ND_SIZE_864BIT;
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break;
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case ND_OPS_rx:
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// 512 bytes extended state.
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size = ND_SIZE_4096BIT;
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break;
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case ND_OPS_cl:
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// The size of one cache line.
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size = ND_SIZE_CACHE_LINE;
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break;
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case ND_OPS_v:
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// 16, 32 or 64 bits.
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{
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@ -1739,26 +1760,6 @@ NdParseOperand(
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}
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break;
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case ND_OPS_sd:
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// 128 bits scalar element (double precision).
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size = ND_SIZE_64BIT;
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break;
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case ND_OPS_ss:
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// 128 bits scalar element (single precision).
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size = ND_SIZE_32BIT;
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break;
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case ND_OPS_sh:
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// FP16 Scalar element.
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size = ND_SIZE_16BIT;
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break;
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case ND_OPS_mib:
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// MIB addressing, the base & the index are used to form a pointer.
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size = 0;
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break;
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case ND_OPS_vm32x:
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case ND_OPS_vm32y:
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case ND_OPS_vm32z:
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@ -1842,36 +1843,6 @@ NdParseOperand(
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}
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break;
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case ND_OPS_12:
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// SAVPREVSSP instruction reads/writes 4 + 8 bytes from the shadow stack.
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size = 12;
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break;
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case ND_OPS_t:
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// Tile register. The actual size depends on how the TILECFG register has been programmed, but it can be
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// up to 1K in size.
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size = ND_SIZE_1KB;
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break;
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case ND_OPS_384:
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// 384 bit Key Locker handle.
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size = ND_SIZE_384BIT;
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break;
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case ND_OPS_512:
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// 512 bit Key Locker handle.
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size = ND_SIZE_512BIT;
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break;
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case ND_OPS_4096:
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// 64 entries x 64 bit per entry = 4096 bit MSR address/value list.
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size = ND_SIZE_4096BIT;
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break;
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case ND_OPS_unknown:
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size = ND_SIZE_UNKNOWN;
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break;
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default:
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return ND_STATUS_INVALID_INSTRUX;
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}
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