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Added 64-bit mul test case + made the code more readable.
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@ -1442,29 +1442,23 @@ ShemuX86SetOperandValue(
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//
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static void
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ShemuX86Multiply64Unsigned(
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ND_UINT64 Operand1,
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ND_UINT64 Operand2,
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ND_UINT64 *ResHigh,
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ND_UINT64 *ResLow
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SHEMU_VALUE *Operand1,
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SHEMU_VALUE *Operand2,
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SHEMU_VALUE *Result
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)
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{
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ND_UINT64 xLow, xHigh, yLow, yHigh, p0, p1, p2, p3, ps;
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ND_UINT64 p0, p1, p2, p3, p4;
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xLow = Operand1 & 0xFFFFFFFF;
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xHigh = Operand1 >> 32;
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yLow = Operand2 & 0xFFFFFFFF;
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yHigh = Operand2 >> 32;
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// Multiply the 4 parts into 4 partial products.
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p0 = xLow * yLow;
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p1 = xLow * yHigh;
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p2 = xHigh * yLow;
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p3 = xHigh * yHigh;
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ps = (((p0 >> 32) + (p1 & 0xFFFFFFFF) + (p2 & 0xFFFFFFFF)) >> 32) & 0xFFFFFFFF;
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// Multiply the 4 32-bit parts into 4 partial products.
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p0 = (ND_UINT64)Operand1->Value.Dwords[0] * (ND_UINT64)Operand2->Value.Dwords[0];
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p1 = (ND_UINT64)Operand1->Value.Dwords[0] * (ND_UINT64)Operand2->Value.Dwords[1];
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p2 = (ND_UINT64)Operand1->Value.Dwords[1] * (ND_UINT64)Operand2->Value.Dwords[0];
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p3 = (ND_UINT64)Operand1->Value.Dwords[1] * (ND_UINT64)Operand2->Value.Dwords[1];
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p4 = (((p0 >> 32) + (p1 & 0xFFFFFFFF) + (p2 & 0xFFFFFFFF)) >> 32) & 0xFFFFFFFF;
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// Fill in the final result (low & high 64-bit parts).
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*ResLow = p0 + (p1 << 32) + (p2 << 32);
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*ResHigh = p3 + (p1 >> 32) + (p2 >> 32) + ps;
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Result->Value.Qwords[0] = p0 + (p1 << 32) + (p2 << 32);
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Result->Value.Qwords[1] = p3 + (p1 >> 32) + (p2 >> 32) + p4;
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}
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@ -1473,24 +1467,23 @@ ShemuX86Multiply64Unsigned(
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//
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static void
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ShemuX86Multiply64Signed(
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ND_SINT64 Operand1,
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ND_SINT64 Operand2,
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ND_SINT64 *ResHigh,
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ND_SINT64 *ResLow
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SHEMU_VALUE *Operand1,
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SHEMU_VALUE *Operand2,
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SHEMU_VALUE *Result
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)
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{
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ShemuX86Multiply64Unsigned((ND_UINT64)Operand1, (ND_UINT64)Operand2, (ND_UINT64 *)ResHigh, (ND_UINT64 *)ResLow);
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ShemuX86Multiply64Unsigned(Operand1, Operand2, Result);
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// Negate, if needed.
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if (Operand1 < 0)
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if (ND_GET_SIGN(8, Operand1->Value.Qwords[0]))
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{
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*ResHigh -= Operand2;
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Result->Value.Qwords[1] -= Operand2->Value.Qwords[0];
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}
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// Negate, if needed.
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if (Operand2 < 0)
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if (ND_GET_SIGN(8, Operand2->Value.Qwords[0]))
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{
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*ResHigh -= Operand1;
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Result->Value.Qwords[1] -= Operand1->Value.Qwords[0];
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}
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}
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@ -2797,13 +2790,11 @@ check_far_branch:
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{
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if (ND_INS_MUL == Context->Arch.X86.Instruction.Instruction)
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{
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ShemuX86Multiply64Unsigned(dst.Value.Qwords[0], src.Value.Qwords[0],
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&res.Value.Qwords[1], &res.Value.Qwords[0]);
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ShemuX86Multiply64Unsigned(&dst, &src, &res);
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}
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else
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{
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ShemuX86Multiply64Signed((ND_SINT64)dst.Value.Qwords[0], (ND_SINT64)src.Value.Qwords[0],
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(ND_SINT64*)&res.Value.Qwords[1], (ND_SINT64*)&res.Value.Qwords[0]);
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ShemuX86Multiply64Signed(&dst, &src, &res);
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}
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}
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