mirror of
https://github.com/bitdefender/bddisasm.git
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* Add support for SIMD exceptions reporting in INSTRUX.
* Add support for new ISAs: MOVRS, MSR_IMM, AMX-FP8, AMX-TRANSPOSE, AMX-TF32, AMX-AVX512, AMX-MOVRS, EVEX-encoded SM4. Co-authored-by: ianichitei (Rust bindings)
This commit is contained in:
Andrei Vlad LUTAS
parent
7d005faa03
commit
42b6eceae6
@ -5,6 +5,13 @@ All notable (user-facing) changes to this project will be documented in this fil
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The format is based on [Keep a Changelog](https://keepachangelog.com/en/1.0.0/).
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## [2.3.0] - 2024-11-07
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### Added
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- Support for SIMD Exceptions reporting (for instructions that generate SIMD exceptions; this is equivalent to also setting or testing the associated bits in the `MXCSR`).
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- Support for the following new x86 ISAs: MOVRS, MSR_IMM, AMX-FP8, AMX-TRANSPOSE, AMX-TF32, AMX-AVX512, AMX-MOVRS and EVEX-encoded SM4 instructions.
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## [2.2.0] - 2024-09-16
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### Added
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@ -4297,7 +4297,8 @@ NdVexExceptionChecks(
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}
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// Handle AMX exception class.
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if (Instrux->ExceptionType == ND_EXT_AMX_E4)
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if (Instrux->ExceptionType == ND_EXT_AMX_E4 ||
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Instrux->ExceptionType == ND_EXT_AMX_E10)
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{
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// #UD if srcdest == src1, srcdest == src2 or src1 == src2. All three operands are tile regs.
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if (Instrux->Operands[0].Info.Register.Reg == Instrux->Operands[1].Info.Register.Reg ||
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@ -4374,7 +4375,8 @@ NdCopyInstructionInfo(
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Instrux->ValidModes.Raw = Idbe->ValidModes;
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Instrux->ValidPrefixes.Raw = Idbe->ValidPrefixes;
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Instrux->ValidDecorators.Raw = Idbe->ValidDecorators;
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*((ND_UINT8*)&Instrux->FpuFlagsAccess) = Idbe->FpuFlags;
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Instrux->FpuFlagsAccess.Raw = Idbe->FpuFlags;
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Instrux->SimdExceptions.Raw = Idbe->SimdExc;
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// Valid for EVEX, VEX and SSE instructions only. A value of 0 means it's not used.
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Instrux->ExceptionType = Idbe->ExcType;
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Instrux->TupleType = Idbe->TupleType;
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@ -4465,8 +4467,11 @@ NdDecodeWithContext(
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return ND_STATUS_INVALID_PARAMETER;
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}
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// Initialize with zero.
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nd_memzero(Instrux, sizeof(INSTRUX));
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if (0 == (Context->Options & ND_OPTION_SKIP_ZERO_INSTRUX))
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{
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// Initialize with zero.
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nd_memzero(Instrux, sizeof(INSTRUX));
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}
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Instrux->DefCode = (ND_UINT8)Context->DefCode;
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Instrux->DefData = (ND_UINT8)Context->DefData;
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File diff suppressed because it is too large
Load Diff
@ -12,7 +12,7 @@
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#ifndef BDDISASM_NO_MNEMONIC
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const char *gMnemonics[1868] =
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const char *gMnemonics[1903] =
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{
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"AAA", "AAD", "AADD", "AAM", "AAND", "AAS", "ADC", "ADCX", "ADD",
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"ADDPD", "ADDPS", "ADDSD", "ADDSS", "ADDSUBPD", "ADDSUBPS", "ADOX",
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@ -92,9 +92,9 @@ const char *gMnemonics[1868] =
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"MOVHLPS", "MOVHPD", "MOVHPS", "MOVLHPS", "MOVLPD", "MOVLPS",
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"MOVMSKPD", "MOVMSKPS", "MOVNTDQ", "MOVNTDQA", "MOVNTI", "MOVNTPD",
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"MOVNTPS", "MOVNTQ", "MOVNTSD", "MOVNTSS", "MOVQ", "MOVQ2DQ",
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"MOVSB", "MOVSD", "MOVSHDUP", "MOVSLDUP", "MOVSQ", "MOVSS", "MOVSW",
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"MOVSX", "MOVSXD", "MOVUPD", "MOVUPS", "MOVZX", "MPSADBW", "MUL",
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"MULPD", "MULPS", "MULSD", "MULSS", "MULX", "MWAIT", "MWAITX",
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"MOVRS", "MOVSB", "MOVSD", "MOVSHDUP", "MOVSLDUP", "MOVSQ", "MOVSS",
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"MOVSW", "MOVSX", "MOVSXD", "MOVUPD", "MOVUPS", "MOVZX", "MPSADBW",
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"MUL", "MULPD", "MULPS", "MULSD", "MULSS", "MULX", "MWAIT", "MWAITX",
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"NEG", "NOP", "NOT", "OR", "ORPD", "ORPS", "OUT", "OUTSB", "OUTSD",
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"OUTSW", "PABSB", "PABSD", "PABSW", "PACKSSDW", "PACKSSWB", "PACKUSDW",
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"PACKUSWB", "PADDB", "PADDD", "PADDQ", "PADDSB", "PADDSW", "PADDUSB",
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@ -116,77 +116,85 @@ const char *gMnemonics[1868] =
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"PMULHUW", "PMULHW", "PMULLD", "PMULLW", "PMULUDQ", "POP", "POP2",
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"POP2P", "POPA", "POPAD", "POPCNT", "POPFD", "POPFQ", "POPFW",
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"POPP", "POR", "PREFETCH", "PREFETCHE", "PREFETCHIT0", "PREFETCHIT1",
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"PREFETCHM", "PREFETCHNTA", "PREFETCHT0", "PREFETCHT1", "PREFETCHT2",
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"PREFETCHW", "PREFETCHWT1", "PSADBW", "PSHUFB", "PSHUFD", "PSHUFHW",
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"PSHUFLW", "PSHUFW", "PSIGNB", "PSIGND", "PSIGNW", "PSLLD", "PSLLDQ",
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"PSLLQ", "PSLLW", "PSMASH", "PSRAD", "PSRAW", "PSRLD", "PSRLDQ",
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"PSRLQ", "PSRLW", "PSUBB", "PSUBD", "PSUBQ", "PSUBSB", "PSUBSW",
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"PSUBUSB", "PSUBUSW", "PSUBW", "PSWAPD", "PTEST", "PTWRITE",
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"PUNPCKHBW", "PUNPCKHDQ", "PUNPCKHQDQ", "PUNPCKHWD", "PUNPCKLBW",
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"PUNPCKLDQ", "PUNPCKLQDQ", "PUNPCKLWD", "PUSH", "PUSH2", "PUSH2P",
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"PUSHA", "PUSHAD", "PUSHFD", "PUSHFQ", "PUSHFW", "PUSHP", "PVALIDATE",
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"PXOR", "RCL", "RCPPS", "RCPSS", "RCR", "RDFSBASE", "RDGSBASE",
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"RDMSR", "RDMSRLIST", "RDPID", "RDPKRU", "RDPMC", "RDPRU", "RDRAND",
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"RDSEED", "RDSSPD", "RDSSPQ", "RDTSC", "RDTSCP", "RETF", "RETN",
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"RMPADJUST", "RMPQUERY", "RMPREAD", "RMPUPDATE", "ROL", "ROR",
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"RORX", "ROUNDPD", "ROUNDPS", "ROUNDSD", "ROUNDSS", "RSM", "RSQRTPS",
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"RSQRTSS", "RSTORSSP", "SAHF", "SAL", "SALC", "SAR", "SARX",
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"SAVEPREVSSP", "SBB", "SCASB", "SCASD", "SCASQ", "SCASW", "SEAMCALL",
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"SEAMOPS", "SEAMRET", "SENDUIPI", "SERIALIZE", "SETBE", "SETC",
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"SETL", "SETLE", "SETNBE", "SETNC", "SETNL", "SETNLE", "SETNO",
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"SETNP", "SETNS", "SETNZ", "SETO", "SETP", "SETS", "SETSSBSY",
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"SETZ", "SFENCE", "SGDT", "SHA1MSG1", "SHA1MSG2", "SHA1NEXTE",
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"SHA1RNDS4", "SHA256MSG1", "SHA256MSG2", "SHA256RNDS2", "SHL",
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"SHLD", "SHLX", "SHR", "SHRD", "SHRX", "SHUFPD", "SHUFPS", "SIDT",
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"SKINIT", "SLDT", "SLWPCB", "SMSW", "SPFLT", "SQRTPD", "SQRTPS",
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"SQRTSD", "SQRTSS", "STAC", "STC", "STD", "STGI", "STI", "STMXCSR",
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"STOSB", "STOSD", "STOSQ", "STOSW", "STR", "STTILECFG", "STUI",
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"SUB", "SUBPD", "SUBPS", "SUBSD", "SUBSS", "SWAPGS", "SYSCALL",
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"SYSENTER", "SYSEXIT", "SYSRET", "T1MSKC", "TCMMIMFP16PS", "TCMMRLFP16PS",
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"TDCALL", "TDPBF16PS", "TDPBSSD", "TDPBSUD", "TDPBUSD", "TDPBUUD",
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"TDPFP16PS", "TEST", "TESTUI", "TILELOADD", "TILELOADDT1", "TILERELEASE",
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"TILESTORED", "TILEZERO", "TLBSYNC", "TPAUSE", "TZCNT", "TZMSK",
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"UCOMISD", "UCOMISS", "UD0", "UD1", "UD2", "UIRET", "UMONITOR",
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"UMWAIT", "UNPCKHPD", "UNPCKHPS", "UNPCKLPD", "UNPCKLPS", "URDMSR",
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"UWRMSR", "V4FMADDPS", "V4FMADDSS", "V4FNMADDPS", "V4FNMADDSS",
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"VADDNEPBF16", "VADDPD", "VADDPH", "VADDPS", "VADDSD", "VADDSH",
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"VADDSS", "VADDSUBPD", "VADDSUBPS", "VAESDEC", "VAESDECLAST",
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"VAESENC", "VAESENCLAST", "VAESIMC", "VAESKEYGENASSIST", "VALIGND",
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"VALIGNQ", "VANDNPD", "VANDNPS", "VANDPD", "VANDPS", "VBCSTNEBF162PS",
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"VBCSTNESH2PS", "VBLENDMPD", "VBLENDMPS", "VBLENDPD", "VBLENDPS",
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"VBLENDVPD", "VBLENDVPS", "VBROADCASTF128", "VBROADCASTF32X2",
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"VBROADCASTF32X4", "VBROADCASTF32X8", "VBROADCASTF64X2", "VBROADCASTF64X4",
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"VBROADCASTI128", "VBROADCASTI32X2", "VBROADCASTI32X4", "VBROADCASTI32X8",
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"VBROADCASTI64X2", "VBROADCASTI64X4", "VBROADCASTSD", "VBROADCASTSS",
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"VCMPPBF16", "VCMPPD", "VCMPPH", "VCMPPS", "VCMPSD", "VCMPSH",
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"VCMPSS", "VCOMISD", "VCOMISH", "VCOMISS", "VCOMPRESSPD", "VCOMPRESSPS",
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"VCOMSBF16", "VCOMXSD", "VCOMXSH", "VCOMXSS", "VCVT2PS2PHX",
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"VCVTBIASPH2BF8", "VCVTBIASPH2BF8S", "VCVTBIASPH2HF8", "VCVTBIASPH2HF8S",
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"VCVTDQ2PD", "VCVTDQ2PH", "VCVTDQ2PS", "VCVTHF82PH", "VCVTNE2PH2BF8",
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"VCVTNE2PH2BF8S", "VCVTNE2PH2HF8", "VCVTNE2PH2HF8S", "VCVTNE2PS2BF16",
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"VCVTNEBF162IBS", "VCVTNEBF162IUBS", "VCVTNEEBF162PS", "VCVTNEEPH2PS",
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"VCVTNEOBF162PS", "VCVTNEOPH2PS", "VCVTNEPH2BF8", "VCVTNEPH2BF8S",
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"VCVTNEPH2HF8", "VCVTNEPH2HF8S", "VCVTNEPS2BF16", "VCVTPD2DQ",
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"VCVTPD2PH", "VCVTPD2PS", "VCVTPD2QQ", "VCVTPD2UDQ", "VCVTPD2UQQ",
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"VCVTPH2DQ", "VCVTPH2IBS", "VCVTPH2IUBS", "VCVTPH2PD", "VCVTPH2PS",
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"VCVTPH2PSX", "VCVTPH2QQ", "VCVTPH2UDQ", "VCVTPH2UQQ", "VCVTPH2UW",
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"VCVTPH2W", "VCVTPS2DQ", "VCVTPS2IBS", "VCVTPS2IUBS", "VCVTPS2PD",
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"VCVTPS2PH", "VCVTPS2PHX", "VCVTPS2QQ", "VCVTPS2UDQ", "VCVTPS2UQQ",
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"VCVTQQ2PD", "VCVTQQ2PH", "VCVTQQ2PS", "VCVTSD2SH", "VCVTSD2SI",
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"VCVTSD2SS", "VCVTSD2USI", "VCVTSH2SD", "VCVTSH2SI", "VCVTSH2SS",
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"VCVTSH2USI", "VCVTSI2SD", "VCVTSI2SH", "VCVTSI2SS", "VCVTSS2SD",
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"VCVTSS2SH", "VCVTSS2SI", "VCVTSS2USI", "VCVTTNEBF162IBS", "VCVTTNEBF162IUBS",
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"VCVTTPD2DQ", "VCVTTPD2DQS", "VCVTTPD2QQ", "VCVTTPD2QQS", "VCVTTPD2UDQ",
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"VCVTTPD2UDQS", "VCVTTPD2UQQ", "VCVTTPD2UQQS", "VCVTTPH2DQ",
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"VCVTTPH2IBS", "VCVTTPH2IUBS", "VCVTTPH2QQ", "VCVTTPH2UDQ", "VCVTTPH2UQQ",
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"VCVTTPH2UW", "VCVTTPH2W", "VCVTTPS2DQ", "VCVTTPS2DQS", "VCVTTPS2IBS",
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"VCVTTPS2IUBS", "VCVTTPS2QQ", "VCVTTPS2QQS", "VCVTTPS2UDQ", "VCVTTPS2UDQS",
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"VCVTTPS2UQQ", "VCVTTPS2UQQS", "VCVTTSD2SI", "VCVTTSD2SIS", "VCVTTSD2USI",
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"VCVTTSD2USIS", "VCVTTSH2SI", "VCVTTSH2USI", "VCVTTSS2SI", "VCVTTSS2SIS",
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"VCVTTSS2USI", "VCVTTSS2USIS", "VCVTUDQ2PD", "VCVTUDQ2PH", "VCVTUDQ2PS",
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"VCVTUQQ2PD", "VCVTUQQ2PH", "VCVTUQQ2PS", "VCVTUSI2SD", "VCVTUSI2SH",
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"VCVTUSI2SS", "VCVTUW2PH", "VCVTW2PH", "VDBPSADBW", "VDIVNEPBF16",
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"VDIVPD", "VDIVPH", "VDIVPS", "VDIVSD", "VDIVSH", "VDIVSS", "VDPBF16PS",
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"PREFETCHM", "PREFETCHNTA", "PREFETCHRST2", "PREFETCHT0", "PREFETCHT1",
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"PREFETCHT2", "PREFETCHW", "PREFETCHWT1", "PSADBW", "PSHUFB",
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"PSHUFD", "PSHUFHW", "PSHUFLW", "PSHUFW", "PSIGNB", "PSIGND",
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"PSIGNW", "PSLLD", "PSLLDQ", "PSLLQ", "PSLLW", "PSMASH", "PSRAD",
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"PSRAW", "PSRLD", "PSRLDQ", "PSRLQ", "PSRLW", "PSUBB", "PSUBD",
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"PSUBQ", "PSUBSB", "PSUBSW", "PSUBUSB", "PSUBUSW", "PSUBW", "PSWAPD",
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"PTEST", "PTWRITE", "PUNPCKHBW", "PUNPCKHDQ", "PUNPCKHQDQ", "PUNPCKHWD",
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"PUNPCKLBW", "PUNPCKLDQ", "PUNPCKLQDQ", "PUNPCKLWD", "PUSH",
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"PUSH2", "PUSH2P", "PUSHA", "PUSHAD", "PUSHFD", "PUSHFQ", "PUSHFW",
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"PUSHP", "PVALIDATE", "PXOR", "RCL", "RCPPS", "RCPSS", "RCR",
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"RDFSBASE", "RDGSBASE", "RDMSR", "RDMSRLIST", "RDPID", "RDPKRU",
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"RDPMC", "RDPRU", "RDRAND", "RDSEED", "RDSSPD", "RDSSPQ", "RDTSC",
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"RDTSCP", "RETF", "RETN", "RMPADJUST", "RMPQUERY", "RMPREAD",
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"RMPUPDATE", "ROL", "ROR", "RORX", "ROUNDPD", "ROUNDPS", "ROUNDSD",
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"ROUNDSS", "RSM", "RSQRTPS", "RSQRTSS", "RSTORSSP", "SAHF", "SAL",
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"SALC", "SAR", "SARX", "SAVEPREVSSP", "SBB", "SCASB", "SCASD",
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"SCASQ", "SCASW", "SEAMCALL", "SEAMOPS", "SEAMRET", "SENDUIPI",
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"SERIALIZE", "SETBE", "SETC", "SETL", "SETLE", "SETNBE", "SETNC",
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"SETNL", "SETNLE", "SETNO", "SETNP", "SETNS", "SETNZ", "SETO",
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"SETP", "SETS", "SETSSBSY", "SETZ", "SFENCE", "SGDT", "SHA1MSG1",
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"SHA1MSG2", "SHA1NEXTE", "SHA1RNDS4", "SHA256MSG1", "SHA256MSG2",
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"SHA256RNDS2", "SHL", "SHLD", "SHLX", "SHR", "SHRD", "SHRX",
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"SHUFPD", "SHUFPS", "SIDT", "SKINIT", "SLDT", "SLWPCB", "SMSW",
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"SPFLT", "SQRTPD", "SQRTPS", "SQRTSD", "SQRTSS", "STAC", "STC",
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"STD", "STGI", "STI", "STMXCSR", "STOSB", "STOSD", "STOSQ", "STOSW",
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"STR", "STTILECFG", "STUI", "SUB", "SUBPD", "SUBPS", "SUBSD",
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"SUBSS", "SWAPGS", "SYSCALL", "SYSENTER", "SYSEXIT", "SYSRET",
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"T1MSKC", "T2RPNTLVWZ0", "T2RPNTLVWZ0RS", "T2RPNTLVWZ0RST1",
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"T2RPNTLVWZ0T1", "T2RPNTLVWZ1", "T2RPNTLVWZ1RS", "T2RPNTLVWZ1RST1",
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"T2RPNTLVWZ1T1", "TCMMIMFP16PS", "TCMMRLFP16PS", "TCONJTCMMIMFP16PS",
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"TCONJTFP16", "TCVTROWD2PS", "TCVTROWPS2PBF16H", "TCVTROWPS2PBF16L",
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"TCVTROWPS2PHH", "TCVTROWPS2PHL", "TDCALL", "TDPBF16PS", "TDPBF8PS",
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"TDPBHF8PS", "TDPBSSD", "TDPBSUD", "TDPBUSD", "TDPBUUD", "TDPFP16PS",
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"TDPHBF8PS", "TDPHF8PS", "TEST", "TESTUI", "TILELOADD", "TILELOADDRS",
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"TILELOADDRST1", "TILELOADDT1", "TILEMOVROW", "TILERELEASE",
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"TILESTORED", "TILEZERO", "TLBSYNC", "TMMULTF32PS", "TPAUSE",
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"TTCMMIMFP16PS", "TTCMMRLFP16PS", "TTDPBF16PS", "TTDPFP16PS",
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"TTMMULTF32PS", "TTRANSPOSED", "TZCNT", "TZMSK", "UCOMISD", "UCOMISS",
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"UD0", "UD1", "UD2", "UIRET", "UMONITOR", "UMWAIT", "UNPCKHPD",
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"UNPCKHPS", "UNPCKLPD", "UNPCKLPS", "URDMSR", "UWRMSR", "V4FMADDPS",
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"V4FMADDSS", "V4FNMADDPS", "V4FNMADDSS", "VADDNEPBF16", "VADDPD",
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"VADDPH", "VADDPS", "VADDSD", "VADDSH", "VADDSS", "VADDSUBPD",
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"VADDSUBPS", "VAESDEC", "VAESDECLAST", "VAESENC", "VAESENCLAST",
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"VAESIMC", "VAESKEYGENASSIST", "VALIGND", "VALIGNQ", "VANDNPD",
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"VANDNPS", "VANDPD", "VANDPS", "VBCSTNEBF162PS", "VBCSTNESH2PS",
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"VBLENDMPD", "VBLENDMPS", "VBLENDPD", "VBLENDPS", "VBLENDVPD",
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"VBLENDVPS", "VBROADCASTF128", "VBROADCASTF32X2", "VBROADCASTF32X4",
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"VBROADCASTF32X8", "VBROADCASTF64X2", "VBROADCASTF64X4", "VBROADCASTI128",
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"VBROADCASTI32X2", "VBROADCASTI32X4", "VBROADCASTI32X8", "VBROADCASTI64X2",
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"VBROADCASTI64X4", "VBROADCASTSD", "VBROADCASTSS", "VCMPPBF16",
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"VCMPPD", "VCMPPH", "VCMPPS", "VCMPSD", "VCMPSH", "VCMPSS", "VCOMISD",
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"VCOMISH", "VCOMISS", "VCOMPRESSPD", "VCOMPRESSPS", "VCOMSBF16",
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"VCOMXSD", "VCOMXSH", "VCOMXSS", "VCVT2PS2PHX", "VCVTBIASPH2BF8",
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"VCVTBIASPH2BF8S", "VCVTBIASPH2HF8", "VCVTBIASPH2HF8S", "VCVTDQ2PD",
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"VCVTDQ2PH", "VCVTDQ2PS", "VCVTHF82PH", "VCVTNE2PH2BF8", "VCVTNE2PH2BF8S",
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"VCVTNE2PH2HF8", "VCVTNE2PH2HF8S", "VCVTNE2PS2BF16", "VCVTNEBF162IBS",
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"VCVTNEBF162IUBS", "VCVTNEEBF162PS", "VCVTNEEPH2PS", "VCVTNEOBF162PS",
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"VCVTNEOPH2PS", "VCVTNEPH2BF8", "VCVTNEPH2BF8S", "VCVTNEPH2HF8",
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"VCVTNEPH2HF8S", "VCVTNEPS2BF16", "VCVTPD2DQ", "VCVTPD2PH", "VCVTPD2PS",
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"VCVTPD2QQ", "VCVTPD2UDQ", "VCVTPD2UQQ", "VCVTPH2DQ", "VCVTPH2IBS",
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"VCVTPH2IUBS", "VCVTPH2PD", "VCVTPH2PS", "VCVTPH2PSX", "VCVTPH2QQ",
|
||||
"VCVTPH2UDQ", "VCVTPH2UQQ", "VCVTPH2UW", "VCVTPH2W", "VCVTPS2DQ",
|
||||
"VCVTPS2IBS", "VCVTPS2IUBS", "VCVTPS2PD", "VCVTPS2PH", "VCVTPS2PHX",
|
||||
"VCVTPS2QQ", "VCVTPS2UDQ", "VCVTPS2UQQ", "VCVTQQ2PD", "VCVTQQ2PH",
|
||||
"VCVTQQ2PS", "VCVTSD2SH", "VCVTSD2SI", "VCVTSD2SS", "VCVTSD2USI",
|
||||
"VCVTSH2SD", "VCVTSH2SI", "VCVTSH2SS", "VCVTSH2USI", "VCVTSI2SD",
|
||||
"VCVTSI2SH", "VCVTSI2SS", "VCVTSS2SD", "VCVTSS2SH", "VCVTSS2SI",
|
||||
"VCVTSS2USI", "VCVTTNEBF162IBS", "VCVTTNEBF162IUBS", "VCVTTPD2DQ",
|
||||
"VCVTTPD2DQS", "VCVTTPD2QQ", "VCVTTPD2QQS", "VCVTTPD2UDQ", "VCVTTPD2UDQS",
|
||||
"VCVTTPD2UQQ", "VCVTTPD2UQQS", "VCVTTPH2DQ", "VCVTTPH2IBS", "VCVTTPH2IUBS",
|
||||
"VCVTTPH2QQ", "VCVTTPH2UDQ", "VCVTTPH2UQQ", "VCVTTPH2UW", "VCVTTPH2W",
|
||||
"VCVTTPS2DQ", "VCVTTPS2DQS", "VCVTTPS2IBS", "VCVTTPS2IUBS", "VCVTTPS2QQ",
|
||||
"VCVTTPS2QQS", "VCVTTPS2UDQ", "VCVTTPS2UDQS", "VCVTTPS2UQQ",
|
||||
"VCVTTPS2UQQS", "VCVTTSD2SI", "VCVTTSD2SIS", "VCVTTSD2USI", "VCVTTSD2USIS",
|
||||
"VCVTTSH2SI", "VCVTTSH2USI", "VCVTTSS2SI", "VCVTTSS2SIS", "VCVTTSS2USI",
|
||||
"VCVTTSS2USIS", "VCVTUDQ2PD", "VCVTUDQ2PH", "VCVTUDQ2PS", "VCVTUQQ2PD",
|
||||
"VCVTUQQ2PH", "VCVTUQQ2PS", "VCVTUSI2SD", "VCVTUSI2SH", "VCVTUSI2SS",
|
||||
"VCVTUW2PH", "VCVTW2PH", "VDBPSADBW", "VDIVNEPBF16", "VDIVPD",
|
||||
"VDIVPH", "VDIVPS", "VDIVSD", "VDIVSH", "VDIVSS", "VDPBF16PS",
|
||||
"VDPPD", "VDPPHPS", "VDPPS", "VERR", "VERW", "VEXP2PD", "VEXP2PS",
|
||||
"VEXPANDPD", "VEXPANDPS", "VEXTRACTF128", "VEXTRACTF32X4", "VEXTRACTF32X8",
|
||||
"VEXTRACTF64X2", "VEXTRACTF64X4", "VEXTRACTI128", "VEXTRACTI32X4",
|
||||
@ -243,101 +251,102 @@ const char *gMnemonics[1868] =
|
||||
"VMOVDQA64", "VMOVDQU", "VMOVDQU16", "VMOVDQU32", "VMOVDQU64",
|
||||
"VMOVDQU8", "VMOVHLPS", "VMOVHPD", "VMOVHPS", "VMOVLHPS", "VMOVLPD",
|
||||
"VMOVLPS", "VMOVMSKPD", "VMOVMSKPS", "VMOVNTDQ", "VMOVNTDQA",
|
||||
"VMOVNTPD", "VMOVNTPS", "VMOVQ", "VMOVSD", "VMOVSH", "VMOVSHDUP",
|
||||
"VMOVSLDUP", "VMOVSS", "VMOVUPD", "VMOVUPS", "VMOVW", "VMPSADBW",
|
||||
"VMPTRLD", "VMPTRST", "VMREAD", "VMRESUME", "VMRUN", "VMSAVE",
|
||||
"VMULNEPBF16", "VMULPD", "VMULPH", "VMULPS", "VMULSD", "VMULSH",
|
||||
"VMULSS", "VMWRITE", "VMXOFF", "VMXON", "VORPD", "VORPS", "VP2INTERSECTD",
|
||||
"VP2INTERSECTQ", "VP4DPWSSD", "VP4DPWSSDS", "VPABSB", "VPABSD",
|
||||
"VPABSQ", "VPABSW", "VPACKSSDW", "VPACKSSWB", "VPACKUSDW", "VPACKUSWB",
|
||||
"VPADDB", "VPADDD", "VPADDQ", "VPADDSB", "VPADDSW", "VPADDUSB",
|
||||
"VPADDUSW", "VPADDW", "VPALIGNR", "VPAND", "VPANDD", "VPANDN",
|
||||
"VPANDND", "VPANDNQ", "VPANDQ", "VPAVGB", "VPAVGW", "VPBLENDD",
|
||||
"VPBLENDMB", "VPBLENDMD", "VPBLENDMQ", "VPBLENDMW", "VPBLENDVB",
|
||||
"VPBLENDW", "VPBROADCASTB", "VPBROADCASTD", "VPBROADCASTMB2Q",
|
||||
"VPBROADCASTMW2D", "VPBROADCASTQ", "VPBROADCASTW", "VPCLMULQDQ",
|
||||
"VPCMOV", "VPCMPB", "VPCMPD", "VPCMPEQB", "VPCMPEQD", "VPCMPEQQ",
|
||||
"VPCMPEQW", "VPCMPESTRI", "VPCMPESTRM", "VPCMPGTB", "VPCMPGTD",
|
||||
"VPCMPGTQ", "VPCMPGTW", "VPCMPISTRI", "VPCMPISTRM", "VPCMPQ",
|
||||
"VPCMPUB", "VPCMPUD", "VPCMPUQ", "VPCMPUW", "VPCMPW", "VPCOMB",
|
||||
"VPCOMD", "VPCOMPRESSB", "VPCOMPRESSD", "VPCOMPRESSQ", "VPCOMPRESSW",
|
||||
"VPCOMQ", "VPCOMUB", "VPCOMUD", "VPCOMUQ", "VPCOMUW", "VPCOMW",
|
||||
"VPCONFLICTD", "VPCONFLICTQ", "VPDPBSSD", "VPDPBSSDS", "VPDPBSUD",
|
||||
"VPDPBSUDS", "VPDPBUSD", "VPDPBUSDS", "VPDPBUUD", "VPDPBUUDS",
|
||||
"VPDPWSSD", "VPDPWSSDS", "VPDPWSUD", "VPDPWSUDS", "VPDPWUSD",
|
||||
"VPDPWUSDS", "VPDPWUUD", "VPDPWUUDS", "VPERM2F128", "VPERM2I128",
|
||||
"VPERMB", "VPERMD", "VPERMI2B", "VPERMI2D", "VPERMI2PD", "VPERMI2PS",
|
||||
"VPERMI2Q", "VPERMI2W", "VPERMIL2PD", "VPERMIL2PS", "VPERMILPD",
|
||||
"VPERMILPS", "VPERMPD", "VPERMPS", "VPERMQ", "VPERMT2B", "VPERMT2D",
|
||||
"VPERMT2PD", "VPERMT2PS", "VPERMT2Q", "VPERMT2W", "VPERMW", "VPEXPANDB",
|
||||
"VPEXPANDD", "VPEXPANDQ", "VPEXPANDW", "VPEXTRB", "VPEXTRD",
|
||||
"VPEXTRQ", "VPEXTRW", "VPGATHERDD", "VPGATHERDQ", "VPGATHERQD",
|
||||
"VPGATHERQQ", "VPHADDBD", "VPHADDBQ", "VPHADDBW", "VPHADDD",
|
||||
"VPHADDDQ", "VPHADDSW", "VPHADDUBD", "VPHADDUBQ", "VPHADDUBW",
|
||||
"VPHADDUDQ", "VPHADDUWD", "VPHADDUWQ", "VPHADDW", "VPHADDWD",
|
||||
"VPHADDWQ", "VPHMINPOSUW", "VPHSUBBW", "VPHSUBD", "VPHSUBDQ",
|
||||
"VPHSUBSW", "VPHSUBW", "VPHSUBWD", "VPINSRB", "VPINSRD", "VPINSRQ",
|
||||
"VPINSRW", "VPLZCNTD", "VPLZCNTQ", "VPMACSDD", "VPMACSDQH", "VPMACSDQL",
|
||||
"VPMACSSDD", "VPMACSSDQH", "VPMACSSDQL", "VPMACSSWD", "VPMACSSWW",
|
||||
"VPMACSWD", "VPMACSWW", "VPMADCSSWD", "VPMADCSWD", "VPMADD52HUQ",
|
||||
"VPMADD52LUQ", "VPMADDUBSW", "VPMADDWD", "VPMASKMOVD", "VPMASKMOVQ",
|
||||
"VPMAXSB", "VPMAXSD", "VPMAXSQ", "VPMAXSW", "VPMAXUB", "VPMAXUD",
|
||||
"VPMAXUQ", "VPMAXUW", "VPMINSB", "VPMINSD", "VPMINSQ", "VPMINSW",
|
||||
"VPMINUB", "VPMINUD", "VPMINUQ", "VPMINUW", "VPMOVB2M", "VPMOVD2M",
|
||||
"VPMOVDB", "VPMOVDW", "VPMOVM2B", "VPMOVM2D", "VPMOVM2Q", "VPMOVM2W",
|
||||
"VPMOVMSKB", "VPMOVQ2M", "VPMOVQB", "VPMOVQD", "VPMOVQW", "VPMOVSDB",
|
||||
"VPMOVSDW", "VPMOVSQB", "VPMOVSQD", "VPMOVSQW", "VPMOVSWB", "VPMOVSXBD",
|
||||
"VPMOVSXBQ", "VPMOVSXBW", "VPMOVSXDQ", "VPMOVSXWD", "VPMOVSXWQ",
|
||||
"VPMOVUSDB", "VPMOVUSDW", "VPMOVUSQB", "VPMOVUSQD", "VPMOVUSQW",
|
||||
"VPMOVUSWB", "VPMOVW2M", "VPMOVWB", "VPMOVZXBD", "VPMOVZXBQ",
|
||||
"VPMOVZXBW", "VPMOVZXDQ", "VPMOVZXWD", "VPMOVZXWQ", "VPMULDQ",
|
||||
"VPMULHRSW", "VPMULHUW", "VPMULHW", "VPMULLD", "VPMULLQ", "VPMULLW",
|
||||
"VPMULTISHIFTQB", "VPMULUDQ", "VPOPCNTB", "VPOPCNTD", "VPOPCNTQ",
|
||||
"VPOPCNTW", "VPOR", "VPORD", "VPORQ", "VPPERM", "VPROLD", "VPROLQ",
|
||||
"VPROLVD", "VPROLVQ", "VPRORD", "VPRORQ", "VPRORVD", "VPRORVQ",
|
||||
"VPROTB", "VPROTD", "VPROTQ", "VPROTW", "VPSADBW", "VPSCATTERDD",
|
||||
"VPSCATTERDQ", "VPSCATTERQD", "VPSCATTERQQ", "VPSHAB", "VPSHAD",
|
||||
"VPSHAQ", "VPSHAW", "VPSHLB", "VPSHLD", "VPSHLDD", "VPSHLDQ",
|
||||
"VPSHLDVD", "VPSHLDVQ", "VPSHLDVW", "VPSHLDW", "VPSHLQ", "VPSHLW",
|
||||
"VPSHRDD", "VPSHRDQ", "VPSHRDVD", "VPSHRDVQ", "VPSHRDVW", "VPSHRDW",
|
||||
"VPSHUFB", "VPSHUFBITQMB", "VPSHUFD", "VPSHUFHW", "VPSHUFLW",
|
||||
"VPSIGNB", "VPSIGND", "VPSIGNW", "VPSLLD", "VPSLLDQ", "VPSLLQ",
|
||||
"VPSLLVD", "VPSLLVQ", "VPSLLVW", "VPSLLW", "VPSRAD", "VPSRAQ",
|
||||
"VPSRAVD", "VPSRAVQ", "VPSRAVW", "VPSRAW", "VPSRLD", "VPSRLDQ",
|
||||
"VPSRLQ", "VPSRLVD", "VPSRLVQ", "VPSRLVW", "VPSRLW", "VPSUBB",
|
||||
"VPSUBD", "VPSUBQ", "VPSUBSB", "VPSUBSW", "VPSUBUSB", "VPSUBUSW",
|
||||
"VPSUBW", "VPTERNLOGD", "VPTERNLOGQ", "VPTEST", "VPTESTMB", "VPTESTMD",
|
||||
"VPTESTMQ", "VPTESTMW", "VPTESTNMB", "VPTESTNMD", "VPTESTNMQ",
|
||||
"VPTESTNMW", "VPUNPCKHBW", "VPUNPCKHDQ", "VPUNPCKHQDQ", "VPUNPCKHWD",
|
||||
"VPUNPCKLBW", "VPUNPCKLDQ", "VPUNPCKLQDQ", "VPUNPCKLWD", "VPXOR",
|
||||
"VPXORD", "VPXORQ", "VRANGEPD", "VRANGEPS", "VRANGESD", "VRANGESS",
|
||||
"VRCP14PD", "VRCP14PS", "VRCP14SD", "VRCP14SS", "VRCP28PD", "VRCP28PS",
|
||||
"VRCP28SD", "VRCP28SS", "VRCPPBF16", "VRCPPH", "VRCPPS", "VRCPSH",
|
||||
"VRCPSS", "VREDUCENEPBF16", "VREDUCEPD", "VREDUCEPH", "VREDUCEPS",
|
||||
"VREDUCESD", "VREDUCESH", "VREDUCESS", "VRNDSCALENEPBF16", "VRNDSCALEPD",
|
||||
"VRNDSCALEPH", "VRNDSCALEPS", "VRNDSCALESD", "VRNDSCALESH", "VRNDSCALESS",
|
||||
"VROUNDPD", "VROUNDPS", "VROUNDSD", "VROUNDSS", "VRSQRT14PD",
|
||||
"VRSQRT14PS", "VRSQRT14SD", "VRSQRT14SS", "VRSQRT28PD", "VRSQRT28PS",
|
||||
"VRSQRT28SD", "VRSQRT28SS", "VRSQRTPBF16", "VRSQRTPH", "VRSQRTPS",
|
||||
"VRSQRTSH", "VRSQRTSS", "VSCALEFPBF16", "VSCALEFPD", "VSCALEFPH",
|
||||
"VSCALEFPS", "VSCALEFSD", "VSCALEFSH", "VSCALEFSS", "VSCATTERDPD",
|
||||
"VSCATTERDPS", "VSCATTERPF0DPD", "VSCATTERPF0DPS", "VSCATTERPF0QPD",
|
||||
"VSCATTERPF0QPS", "VSCATTERPF1DPD", "VSCATTERPF1DPS", "VSCATTERPF1QPD",
|
||||
"VSCATTERPF1QPS", "VSCATTERQPD", "VSCATTERQPS", "VSHA512MSG1",
|
||||
"VSHA512MSG2", "VSHA512RNDS2", "VSHUFF32X4", "VSHUFF64X2", "VSHUFI32X4",
|
||||
"VSHUFI64X2", "VSHUFPD", "VSHUFPS", "VSM3MSG1", "VSM3MSG2", "VSM3RNDS2",
|
||||
"VSM4KEY4", "VSM4RNDS4", "VSQRTNEPBF16", "VSQRTPD", "VSQRTPH",
|
||||
"VSQRTPS", "VSQRTSD", "VSQRTSH", "VSQRTSS", "VSTMXCSR", "VSUBNEPBF16",
|
||||
"VSUBPD", "VSUBPH", "VSUBPS", "VSUBSD", "VSUBSH", "VSUBSS", "VTESTPD",
|
||||
"VTESTPS", "VUCOMISD", "VUCOMISH", "VUCOMISS", "VUCOMXSD", "VUCOMXSH",
|
||||
"VUCOMXSS", "VUNPCKHPD", "VUNPCKHPS", "VUNPCKLPD", "VUNPCKLPS",
|
||||
"VXORPD", "VXORPS", "VZEROALL", "VZEROUPPER", "WAIT", "WBINVD",
|
||||
"WBNOINVD", "WRFSBASE", "WRGSBASE", "WRMSR", "WRMSRLIST", "WRMSRNS",
|
||||
"WRPKRU", "WRSSD", "WRSSQ", "WRUSSD", "WRUSSQ", "XABORT", "XADD",
|
||||
"XBEGIN", "XCHG", "XEND", "XGETBV", "XLATB", "XOR", "XORPD",
|
||||
"XORPS", "XRESLDTRK", "XRSTOR", "XRSTOR64", "XRSTORS", "XRSTORS64",
|
||||
"XSAVE", "XSAVE64", "XSAVEC", "XSAVEC64", "XSAVEOPT", "XSAVEOPT64",
|
||||
"XSAVES", "XSAVES64", "XSETBV", "XSUSLDTRK", "XTEST",
|
||||
"VMOVNTPD", "VMOVNTPS", "VMOVQ", "VMOVRSB", "VMOVRSD", "VMOVRSQ",
|
||||
"VMOVRSW", "VMOVSD", "VMOVSH", "VMOVSHDUP", "VMOVSLDUP", "VMOVSS",
|
||||
"VMOVUPD", "VMOVUPS", "VMOVW", "VMPSADBW", "VMPTRLD", "VMPTRST",
|
||||
"VMREAD", "VMRESUME", "VMRUN", "VMSAVE", "VMULNEPBF16", "VMULPD",
|
||||
"VMULPH", "VMULPS", "VMULSD", "VMULSH", "VMULSS", "VMWRITE",
|
||||
"VMXOFF", "VMXON", "VORPD", "VORPS", "VP2INTERSECTD", "VP2INTERSECTQ",
|
||||
"VP4DPWSSD", "VP4DPWSSDS", "VPABSB", "VPABSD", "VPABSQ", "VPABSW",
|
||||
"VPACKSSDW", "VPACKSSWB", "VPACKUSDW", "VPACKUSWB", "VPADDB",
|
||||
"VPADDD", "VPADDQ", "VPADDSB", "VPADDSW", "VPADDUSB", "VPADDUSW",
|
||||
"VPADDW", "VPALIGNR", "VPAND", "VPANDD", "VPANDN", "VPANDND",
|
||||
"VPANDNQ", "VPANDQ", "VPAVGB", "VPAVGW", "VPBLENDD", "VPBLENDMB",
|
||||
"VPBLENDMD", "VPBLENDMQ", "VPBLENDMW", "VPBLENDVB", "VPBLENDW",
|
||||
"VPBROADCASTB", "VPBROADCASTD", "VPBROADCASTMB2Q", "VPBROADCASTMW2D",
|
||||
"VPBROADCASTQ", "VPBROADCASTW", "VPCLMULQDQ", "VPCMOV", "VPCMPB",
|
||||
"VPCMPD", "VPCMPEQB", "VPCMPEQD", "VPCMPEQQ", "VPCMPEQW", "VPCMPESTRI",
|
||||
"VPCMPESTRM", "VPCMPGTB", "VPCMPGTD", "VPCMPGTQ", "VPCMPGTW",
|
||||
"VPCMPISTRI", "VPCMPISTRM", "VPCMPQ", "VPCMPUB", "VPCMPUD", "VPCMPUQ",
|
||||
"VPCMPUW", "VPCMPW", "VPCOMB", "VPCOMD", "VPCOMPRESSB", "VPCOMPRESSD",
|
||||
"VPCOMPRESSQ", "VPCOMPRESSW", "VPCOMQ", "VPCOMUB", "VPCOMUD",
|
||||
"VPCOMUQ", "VPCOMUW", "VPCOMW", "VPCONFLICTD", "VPCONFLICTQ",
|
||||
"VPDPBSSD", "VPDPBSSDS", "VPDPBSUD", "VPDPBSUDS", "VPDPBUSD",
|
||||
"VPDPBUSDS", "VPDPBUUD", "VPDPBUUDS", "VPDPWSSD", "VPDPWSSDS",
|
||||
"VPDPWSUD", "VPDPWSUDS", "VPDPWUSD", "VPDPWUSDS", "VPDPWUUD",
|
||||
"VPDPWUUDS", "VPERM2F128", "VPERM2I128", "VPERMB", "VPERMD",
|
||||
"VPERMI2B", "VPERMI2D", "VPERMI2PD", "VPERMI2PS", "VPERMI2Q",
|
||||
"VPERMI2W", "VPERMIL2PD", "VPERMIL2PS", "VPERMILPD", "VPERMILPS",
|
||||
"VPERMPD", "VPERMPS", "VPERMQ", "VPERMT2B", "VPERMT2D", "VPERMT2PD",
|
||||
"VPERMT2PS", "VPERMT2Q", "VPERMT2W", "VPERMW", "VPEXPANDB", "VPEXPANDD",
|
||||
"VPEXPANDQ", "VPEXPANDW", "VPEXTRB", "VPEXTRD", "VPEXTRQ", "VPEXTRW",
|
||||
"VPGATHERDD", "VPGATHERDQ", "VPGATHERQD", "VPGATHERQQ", "VPHADDBD",
|
||||
"VPHADDBQ", "VPHADDBW", "VPHADDD", "VPHADDDQ", "VPHADDSW", "VPHADDUBD",
|
||||
"VPHADDUBQ", "VPHADDUBW", "VPHADDUDQ", "VPHADDUWD", "VPHADDUWQ",
|
||||
"VPHADDW", "VPHADDWD", "VPHADDWQ", "VPHMINPOSUW", "VPHSUBBW",
|
||||
"VPHSUBD", "VPHSUBDQ", "VPHSUBSW", "VPHSUBW", "VPHSUBWD", "VPINSRB",
|
||||
"VPINSRD", "VPINSRQ", "VPINSRW", "VPLZCNTD", "VPLZCNTQ", "VPMACSDD",
|
||||
"VPMACSDQH", "VPMACSDQL", "VPMACSSDD", "VPMACSSDQH", "VPMACSSDQL",
|
||||
"VPMACSSWD", "VPMACSSWW", "VPMACSWD", "VPMACSWW", "VPMADCSSWD",
|
||||
"VPMADCSWD", "VPMADD52HUQ", "VPMADD52LUQ", "VPMADDUBSW", "VPMADDWD",
|
||||
"VPMASKMOVD", "VPMASKMOVQ", "VPMAXSB", "VPMAXSD", "VPMAXSQ",
|
||||
"VPMAXSW", "VPMAXUB", "VPMAXUD", "VPMAXUQ", "VPMAXUW", "VPMINSB",
|
||||
"VPMINSD", "VPMINSQ", "VPMINSW", "VPMINUB", "VPMINUD", "VPMINUQ",
|
||||
"VPMINUW", "VPMOVB2M", "VPMOVD2M", "VPMOVDB", "VPMOVDW", "VPMOVM2B",
|
||||
"VPMOVM2D", "VPMOVM2Q", "VPMOVM2W", "VPMOVMSKB", "VPMOVQ2M",
|
||||
"VPMOVQB", "VPMOVQD", "VPMOVQW", "VPMOVSDB", "VPMOVSDW", "VPMOVSQB",
|
||||
"VPMOVSQD", "VPMOVSQW", "VPMOVSWB", "VPMOVSXBD", "VPMOVSXBQ",
|
||||
"VPMOVSXBW", "VPMOVSXDQ", "VPMOVSXWD", "VPMOVSXWQ", "VPMOVUSDB",
|
||||
"VPMOVUSDW", "VPMOVUSQB", "VPMOVUSQD", "VPMOVUSQW", "VPMOVUSWB",
|
||||
"VPMOVW2M", "VPMOVWB", "VPMOVZXBD", "VPMOVZXBQ", "VPMOVZXBW",
|
||||
"VPMOVZXDQ", "VPMOVZXWD", "VPMOVZXWQ", "VPMULDQ", "VPMULHRSW",
|
||||
"VPMULHUW", "VPMULHW", "VPMULLD", "VPMULLQ", "VPMULLW", "VPMULTISHIFTQB",
|
||||
"VPMULUDQ", "VPOPCNTB", "VPOPCNTD", "VPOPCNTQ", "VPOPCNTW", "VPOR",
|
||||
"VPORD", "VPORQ", "VPPERM", "VPROLD", "VPROLQ", "VPROLVD", "VPROLVQ",
|
||||
"VPRORD", "VPRORQ", "VPRORVD", "VPRORVQ", "VPROTB", "VPROTD",
|
||||
"VPROTQ", "VPROTW", "VPSADBW", "VPSCATTERDD", "VPSCATTERDQ",
|
||||
"VPSCATTERQD", "VPSCATTERQQ", "VPSHAB", "VPSHAD", "VPSHAQ", "VPSHAW",
|
||||
"VPSHLB", "VPSHLD", "VPSHLDD", "VPSHLDQ", "VPSHLDVD", "VPSHLDVQ",
|
||||
"VPSHLDVW", "VPSHLDW", "VPSHLQ", "VPSHLW", "VPSHRDD", "VPSHRDQ",
|
||||
"VPSHRDVD", "VPSHRDVQ", "VPSHRDVW", "VPSHRDW", "VPSHUFB", "VPSHUFBITQMB",
|
||||
"VPSHUFD", "VPSHUFHW", "VPSHUFLW", "VPSIGNB", "VPSIGND", "VPSIGNW",
|
||||
"VPSLLD", "VPSLLDQ", "VPSLLQ", "VPSLLVD", "VPSLLVQ", "VPSLLVW",
|
||||
"VPSLLW", "VPSRAD", "VPSRAQ", "VPSRAVD", "VPSRAVQ", "VPSRAVW",
|
||||
"VPSRAW", "VPSRLD", "VPSRLDQ", "VPSRLQ", "VPSRLVD", "VPSRLVQ",
|
||||
"VPSRLVW", "VPSRLW", "VPSUBB", "VPSUBD", "VPSUBQ", "VPSUBSB",
|
||||
"VPSUBSW", "VPSUBUSB", "VPSUBUSW", "VPSUBW", "VPTERNLOGD", "VPTERNLOGQ",
|
||||
"VPTEST", "VPTESTMB", "VPTESTMD", "VPTESTMQ", "VPTESTMW", "VPTESTNMB",
|
||||
"VPTESTNMD", "VPTESTNMQ", "VPTESTNMW", "VPUNPCKHBW", "VPUNPCKHDQ",
|
||||
"VPUNPCKHQDQ", "VPUNPCKHWD", "VPUNPCKLBW", "VPUNPCKLDQ", "VPUNPCKLQDQ",
|
||||
"VPUNPCKLWD", "VPXOR", "VPXORD", "VPXORQ", "VRANGEPD", "VRANGEPS",
|
||||
"VRANGESD", "VRANGESS", "VRCP14PD", "VRCP14PS", "VRCP14SD", "VRCP14SS",
|
||||
"VRCP28PD", "VRCP28PS", "VRCP28SD", "VRCP28SS", "VRCPPBF16",
|
||||
"VRCPPH", "VRCPPS", "VRCPSH", "VRCPSS", "VREDUCENEPBF16", "VREDUCEPD",
|
||||
"VREDUCEPH", "VREDUCEPS", "VREDUCESD", "VREDUCESH", "VREDUCESS",
|
||||
"VRNDSCALENEPBF16", "VRNDSCALEPD", "VRNDSCALEPH", "VRNDSCALEPS",
|
||||
"VRNDSCALESD", "VRNDSCALESH", "VRNDSCALESS", "VROUNDPD", "VROUNDPS",
|
||||
"VROUNDSD", "VROUNDSS", "VRSQRT14PD", "VRSQRT14PS", "VRSQRT14SD",
|
||||
"VRSQRT14SS", "VRSQRT28PD", "VRSQRT28PS", "VRSQRT28SD", "VRSQRT28SS",
|
||||
"VRSQRTPBF16", "VRSQRTPH", "VRSQRTPS", "VRSQRTSH", "VRSQRTSS",
|
||||
"VSCALEFPBF16", "VSCALEFPD", "VSCALEFPH", "VSCALEFPS", "VSCALEFSD",
|
||||
"VSCALEFSH", "VSCALEFSS", "VSCATTERDPD", "VSCATTERDPS", "VSCATTERPF0DPD",
|
||||
"VSCATTERPF0DPS", "VSCATTERPF0QPD", "VSCATTERPF0QPS", "VSCATTERPF1DPD",
|
||||
"VSCATTERPF1DPS", "VSCATTERPF1QPD", "VSCATTERPF1QPS", "VSCATTERQPD",
|
||||
"VSCATTERQPS", "VSHA512MSG1", "VSHA512MSG2", "VSHA512RNDS2",
|
||||
"VSHUFF32X4", "VSHUFF64X2", "VSHUFI32X4", "VSHUFI64X2", "VSHUFPD",
|
||||
"VSHUFPS", "VSM3MSG1", "VSM3MSG2", "VSM3RNDS2", "VSM4KEY4", "VSM4RNDS4",
|
||||
"VSQRTNEPBF16", "VSQRTPD", "VSQRTPH", "VSQRTPS", "VSQRTSD", "VSQRTSH",
|
||||
"VSQRTSS", "VSTMXCSR", "VSUBNEPBF16", "VSUBPD", "VSUBPH", "VSUBPS",
|
||||
"VSUBSD", "VSUBSH", "VSUBSS", "VTESTPD", "VTESTPS", "VUCOMISD",
|
||||
"VUCOMISH", "VUCOMISS", "VUCOMXSD", "VUCOMXSH", "VUCOMXSS", "VUNPCKHPD",
|
||||
"VUNPCKHPS", "VUNPCKLPD", "VUNPCKLPS", "VXORPD", "VXORPS", "VZEROALL",
|
||||
"VZEROUPPER", "WAIT", "WBINVD", "WBNOINVD", "WRFSBASE", "WRGSBASE",
|
||||
"WRMSR", "WRMSRLIST", "WRMSRNS", "WRPKRU", "WRSSD", "WRSSQ",
|
||||
"WRUSSD", "WRUSSQ", "XABORT", "XADD", "XBEGIN", "XCHG", "XEND",
|
||||
"XGETBV", "XLATB", "XOR", "XORPD", "XORPS", "XRESLDTRK", "XRSTOR",
|
||||
"XRSTOR64", "XRSTORS", "XRSTORS64", "XSAVE", "XSAVE64", "XSAVEC",
|
||||
"XSAVEC64", "XSAVEOPT", "XSAVEOPT64", "XSAVES", "XSAVES64", "XSETBV",
|
||||
"XSUSLDTRK", "XTEST",
|
||||
};
|
||||
|
||||
#endif // !BDDISASM_NO_MNEMONIC
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -309,103 +309,103 @@ const ND_TABLE_OPCODE gXopMap_mmmmm_0a_opcode =
|
||||
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_e3_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[ 3599] // VPHSUBDQ Vdq,Wdq
|
||||
(const void *)&gInstructions[ 3644] // VPHSUBDQ Vdq,Wdq
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_e2_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[ 3602] // VPHSUBWD Vdq,Wdq
|
||||
(const void *)&gInstructions[ 3647] // VPHSUBWD Vdq,Wdq
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_e1_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[ 3597] // VPHSUBBW Vdq,Wdq
|
||||
(const void *)&gInstructions[ 3642] // VPHSUBBW Vdq,Wdq
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_db_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[ 3590] // VPHADDUDQ Vdq,Wdq
|
||||
(const void *)&gInstructions[ 3635] // VPHADDUDQ Vdq,Wdq
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_d7_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[ 3592] // VPHADDUWQ Vdq,Wdq
|
||||
(const void *)&gInstructions[ 3637] // VPHADDUWQ Vdq,Wdq
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_d6_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[ 3591] // VPHADDUWD Vdq,Wdq
|
||||
(const void *)&gInstructions[ 3636] // VPHADDUWD Vdq,Wdq
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_d3_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[ 3588] // VPHADDUBQ Vdq,Wdq
|
||||
(const void *)&gInstructions[ 3633] // VPHADDUBQ Vdq,Wdq
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_d2_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[ 3587] // VPHADDUBD Vdq,Wdq
|
||||
(const void *)&gInstructions[ 3632] // VPHADDUBD Vdq,Wdq
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_d1_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[ 3589] // VPHADDUBW Vdq,Wdq
|
||||
(const void *)&gInstructions[ 3634] // VPHADDUBW Vdq,Wdq
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_cb_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[ 3585] // VPHADDDQ Vdq,Wdq
|
||||
(const void *)&gInstructions[ 3630] // VPHADDDQ Vdq,Wdq
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_c7_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[ 3595] // VPHADDWQ Vdq,Wdq
|
||||
(const void *)&gInstructions[ 3640] // VPHADDWQ Vdq,Wdq
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_c6_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[ 3594] // VPHADDWD Vdq,Wdq
|
||||
(const void *)&gInstructions[ 3639] // VPHADDWD Vdq,Wdq
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_c3_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[ 3582] // VPHADDBQ Vdq,Wdq
|
||||
(const void *)&gInstructions[ 3627] // VPHADDBQ Vdq,Wdq
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_c2_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[ 3581] // VPHADDBD Vdq,Wdq
|
||||
(const void *)&gInstructions[ 3626] // VPHADDBD Vdq,Wdq
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_c1_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[ 3583] // VPHADDBW Vdq,Wdq
|
||||
(const void *)&gInstructions[ 3628] // VPHADDBW Vdq,Wdq
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_9b_w_01_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[ 3788] // VPSHAQ Vdq,Hdq,Wdq
|
||||
(const void *)&gInstructions[ 3833] // VPSHAQ Vdq,Hdq,Wdq
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_9b_w_00_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[ 3787] // VPSHAQ Vdq,Wdq,Hdq
|
||||
(const void *)&gInstructions[ 3832] // VPSHAQ Vdq,Wdq,Hdq
|
||||
};
|
||||
|
||||
const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_9b_w =
|
||||
@ -420,13 +420,13 @@ const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_9b_w =
|
||||
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_9a_w_01_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[ 3786] // VPSHAD Vdq,Hdq,Wdq
|
||||
(const void *)&gInstructions[ 3831] // VPSHAD Vdq,Hdq,Wdq
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_9a_w_00_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[ 3785] // VPSHAD Vdq,Wdq,Hdq
|
||||
(const void *)&gInstructions[ 3830] // VPSHAD Vdq,Wdq,Hdq
|
||||
};
|
||||
|
||||
const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_9a_w =
|
||||
@ -441,13 +441,13 @@ const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_9a_w =
|
||||
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_99_w_01_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[ 3790] // VPSHAW Vdq,Hdq,Wdq
|
||||
(const void *)&gInstructions[ 3835] // VPSHAW Vdq,Hdq,Wdq
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_99_w_00_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[ 3789] // VPSHAW Vdq,Wdq,Hdq
|
||||
(const void *)&gInstructions[ 3834] // VPSHAW Vdq,Wdq,Hdq
|
||||
};
|
||||
|
||||
const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_99_w =
|
||||
@ -462,13 +462,13 @@ const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_99_w =
|
||||
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_98_w_01_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[ 3784] // VPSHAB Vdq,Hdq,Wdq
|
||||
(const void *)&gInstructions[ 3829] // VPSHAB Vdq,Hdq,Wdq
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_98_w_00_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[ 3783] // VPSHAB Vdq,Wdq,Hdq
|
||||
(const void *)&gInstructions[ 3828] // VPSHAB Vdq,Wdq,Hdq
|
||||
};
|
||||
|
||||
const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_98_w =
|
||||
@ -483,13 +483,13 @@ const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_98_w =
|
||||
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_97_w_01_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[ 3803] // VPSHLQ Vdq,Hdq,Wdq
|
||||
(const void *)&gInstructions[ 3848] // VPSHLQ Vdq,Hdq,Wdq
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_97_w_00_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[ 3802] // VPSHLQ Vdq,Wdq,Hdq
|
||||
(const void *)&gInstructions[ 3847] // VPSHLQ Vdq,Wdq,Hdq
|
||||
};
|
||||
|
||||
const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_97_w =
|
||||
@ -504,13 +504,13 @@ const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_97_w =
|
||||
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_96_w_01_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[ 3794] // VPSHLB Vdq,Hdq,Wdq
|
||||
(const void *)&gInstructions[ 3839] // VPSHLB Vdq,Hdq,Wdq
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_96_w_00_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[ 3795] // VPSHLD Vdq,Wdq,Hdq
|
||||
(const void *)&gInstructions[ 3840] // VPSHLD Vdq,Wdq,Hdq
|
||||
};
|
||||
|
||||
const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_96_w =
|
||||
@ -525,13 +525,13 @@ const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_96_w =
|
||||
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_95_w_01_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[ 3793] // VPSHLB Vdq,Hdq,Wdq
|
||||
(const void *)&gInstructions[ 3838] // VPSHLB Vdq,Hdq,Wdq
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_95_w_00_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[ 3804] // VPSHLW Vdq,Wdq,Hdq
|
||||
(const void *)&gInstructions[ 3849] // VPSHLW Vdq,Wdq,Hdq
|
||||
};
|
||||
|
||||
const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_95_w =
|
||||
@ -546,13 +546,13 @@ const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_95_w =
|
||||
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_94_w_01_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[ 3792] // VPSHLB Vdq,Hdq,Wdq
|
||||
(const void *)&gInstructions[ 3837] // VPSHLB Vdq,Hdq,Wdq
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_94_w_00_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[ 3791] // VPSHLB Vdq,Wdq,Hdq
|
||||
(const void *)&gInstructions[ 3836] // VPSHLB Vdq,Wdq,Hdq
|
||||
};
|
||||
|
||||
const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_94_w =
|
||||
@ -567,13 +567,13 @@ const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_94_w =
|
||||
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_93_w_01_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[ 3773] // VPROTQ Vdq,Hdq,Wdq
|
||||
(const void *)&gInstructions[ 3818] // VPROTQ Vdq,Hdq,Wdq
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_93_w_00_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[ 3772] // VPROTQ Vdq,Wdq,Hdq
|
||||
(const void *)&gInstructions[ 3817] // VPROTQ Vdq,Wdq,Hdq
|
||||
};
|
||||
|
||||
const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_93_w =
|
||||
@ -588,13 +588,13 @@ const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_93_w =
|
||||
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_92_w_01_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[ 3770] // VPROTD Vdq,Hdq,Wdq
|
||||
(const void *)&gInstructions[ 3815] // VPROTD Vdq,Hdq,Wdq
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_92_w_00_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[ 3769] // VPROTD Vdq,Wdq,Hdq
|
||||
(const void *)&gInstructions[ 3814] // VPROTD Vdq,Wdq,Hdq
|
||||
};
|
||||
|
||||
const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_92_w =
|
||||
@ -609,13 +609,13 @@ const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_92_w =
|
||||
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_91_w_01_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[ 3776] // VPROTW Vdq,Hdq,Wdq
|
||||
(const void *)&gInstructions[ 3821] // VPROTW Vdq,Hdq,Wdq
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_91_w_00_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[ 3775] // VPROTW Vdq,Wdq,Hdq
|
||||
(const void *)&gInstructions[ 3820] // VPROTW Vdq,Wdq,Hdq
|
||||
};
|
||||
|
||||
const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_91_w =
|
||||
@ -630,13 +630,13 @@ const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_91_w =
|
||||
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_90_w_01_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[ 3767] // VPROTB Vdq,Hdq,Wdq
|
||||
(const void *)&gInstructions[ 3812] // VPROTB Vdq,Hdq,Wdq
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_90_w_00_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[ 3766] // VPROTB Vdq,Wdq,Hdq
|
||||
(const void *)&gInstructions[ 3811] // VPROTB Vdq,Wdq,Hdq
|
||||
};
|
||||
|
||||
const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_90_w =
|
||||
@ -651,31 +651,31 @@ const ND_TABLE_EX_W gXopMap_mmmmm_09_opcode_90_w =
|
||||
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_83_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[ 3127] // VFRCZSD Vdq,Wsd
|
||||
(const void *)&gInstructions[ 3168] // VFRCZSD Vdq,Wsd
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_82_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[ 3128] // VFRCZSS Vdq,Wss
|
||||
(const void *)&gInstructions[ 3169] // VFRCZSS Vdq,Wss
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_81_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[ 3125] // VFRCZPD Vx,Wx
|
||||
(const void *)&gInstructions[ 3166] // VFRCZPD Vx,Wx
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_80_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[ 3126] // VFRCZPS Vx,Wx
|
||||
(const void *)&gInstructions[ 3167] // VFRCZPS Vx,Wx
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_12_modrmreg_01_modrmmod_01_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[ 2496] // SLWPCB Ry
|
||||
(const void *)&gInstructions[ 2502] // SLWPCB Ry
|
||||
};
|
||||
|
||||
const ND_TABLE_MODRM_MOD gXopMap_mmmmm_09_opcode_12_modrmreg_01_modrmmod =
|
||||
@ -747,7 +747,7 @@ const ND_TABLE_MODRM_REG gXopMap_mmmmm_09_opcode_02_modrmreg =
|
||||
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_01_modrmreg_07_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[ 2586] // T1MSKC By,Ey
|
||||
(const void *)&gInstructions[ 2592] // T1MSKC By,Ey
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_01_modrmreg_06_leaf =
|
||||
@ -765,7 +765,7 @@ const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_01_modrmreg_05_leaf =
|
||||
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_01_modrmreg_04_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[ 2620] // TZMSK By,Ey
|
||||
(const void *)&gInstructions[ 2661] // TZMSK By,Ey
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_09_opcode_01_modrmreg_03_leaf =
|
||||
@ -1067,97 +1067,97 @@ const ND_TABLE_OPCODE gXopMap_mmmmm_09_opcode =
|
||||
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_ef_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[ 3474] // VPCOMUQ Vdq,Hdq,Wdq,Ib
|
||||
(const void *)&gInstructions[ 3519] // VPCOMUQ Vdq,Hdq,Wdq,Ib
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_ee_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[ 3473] // VPCOMUD Vdq,Hdq,Wdq,Ib
|
||||
(const void *)&gInstructions[ 3518] // VPCOMUD Vdq,Hdq,Wdq,Ib
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_ed_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[ 3475] // VPCOMUW Vdq,Hdq,Wdq,Ib
|
||||
(const void *)&gInstructions[ 3520] // VPCOMUW Vdq,Hdq,Wdq,Ib
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_ec_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[ 3472] // VPCOMUB Vdq,Hdq,Wdq,Ib
|
||||
(const void *)&gInstructions[ 3517] // VPCOMUB Vdq,Hdq,Wdq,Ib
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_cf_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[ 3471] // VPCOMQ Vdq,Hdq,Wdq,Ib
|
||||
(const void *)&gInstructions[ 3516] // VPCOMQ Vdq,Hdq,Wdq,Ib
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_ce_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[ 3466] // VPCOMD Vdq,Hdq,Wdq,Ib
|
||||
(const void *)&gInstructions[ 3511] // VPCOMD Vdq,Hdq,Wdq,Ib
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_cd_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[ 3476] // VPCOMW Vdq,Hdq,Wdq,Ib
|
||||
(const void *)&gInstructions[ 3521] // VPCOMW Vdq,Hdq,Wdq,Ib
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_cc_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[ 3465] // VPCOMB Vdq,Hdq,Wdq,Ib
|
||||
(const void *)&gInstructions[ 3510] // VPCOMB Vdq,Hdq,Wdq,Ib
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_c3_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[ 3771] // VPROTQ Vdq,Wdq,Ib
|
||||
(const void *)&gInstructions[ 3816] // VPROTQ Vdq,Wdq,Ib
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_c2_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[ 3768] // VPROTD Vdq,Wdq,Ib
|
||||
(const void *)&gInstructions[ 3813] // VPROTD Vdq,Wdq,Ib
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_c1_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[ 3774] // VPROTW Vdq,Wdq,Ib
|
||||
(const void *)&gInstructions[ 3819] // VPROTW Vdq,Wdq,Ib
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_c0_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[ 3765] // VPROTB Vdq,Wdq,Ib
|
||||
(const void *)&gInstructions[ 3810] // VPROTB Vdq,Wdq,Ib
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_b6_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[ 3628] // VPMADCSWD Vdq,Hdq,Wdq,Ldq
|
||||
(const void *)&gInstructions[ 3673] // VPMADCSWD Vdq,Hdq,Wdq,Ldq
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_a6_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[ 3627] // VPMADCSSWD Vdq,Hdq,Wdq,Ldq
|
||||
(const void *)&gInstructions[ 3672] // VPMADCSSWD Vdq,Hdq,Wdq,Ldq
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_a3_w_01_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[ 3756] // VPPERM Vx,Hx,Lx,Wx
|
||||
(const void *)&gInstructions[ 3801] // VPPERM Vx,Hx,Lx,Wx
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_a3_w_00_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[ 3755] // VPPERM Vx,Hx,Wx,Lx
|
||||
(const void *)&gInstructions[ 3800] // VPPERM Vx,Hx,Wx,Lx
|
||||
};
|
||||
|
||||
const ND_TABLE_EX_W gXopMap_mmmmm_08_opcode_a3_w =
|
||||
@ -1172,13 +1172,13 @@ const ND_TABLE_EX_W gXopMap_mmmmm_08_opcode_a3_w =
|
||||
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_a2_w_01_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[ 3436] // VPCMOV Vx,Hx,Lx,Wx
|
||||
(const void *)&gInstructions[ 3481] // VPCMOV Vx,Hx,Lx,Wx
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_a2_w_00_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[ 3435] // VPCMOV Vx,Hx,Wx,Lx
|
||||
(const void *)&gInstructions[ 3480] // VPCMOV Vx,Hx,Wx,Lx
|
||||
};
|
||||
|
||||
const ND_TABLE_EX_W gXopMap_mmmmm_08_opcode_a2_w =
|
||||
@ -1193,61 +1193,61 @@ const ND_TABLE_EX_W gXopMap_mmmmm_08_opcode_a2_w =
|
||||
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_9f_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[ 3618] // VPMACSDQH Vdq,Hdq,Wdq,Ldq
|
||||
(const void *)&gInstructions[ 3663] // VPMACSDQH Vdq,Hdq,Wdq,Ldq
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_9e_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[ 3617] // VPMACSDD Vdq,Hdq,Wdq,Ldq
|
||||
(const void *)&gInstructions[ 3662] // VPMACSDD Vdq,Hdq,Wdq,Ldq
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_97_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[ 3619] // VPMACSDQL Vdq,Hdq,Wdq,Ldq
|
||||
(const void *)&gInstructions[ 3664] // VPMACSDQL Vdq,Hdq,Wdq,Ldq
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_96_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[ 3625] // VPMACSWD Vdq,Hdq,Wdq,Ldq
|
||||
(const void *)&gInstructions[ 3670] // VPMACSWD Vdq,Hdq,Wdq,Ldq
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_95_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[ 3626] // VPMACSWW Vdq,Hdq,Wdq,Ldq
|
||||
(const void *)&gInstructions[ 3671] // VPMACSWW Vdq,Hdq,Wdq,Ldq
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_8f_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[ 3621] // VPMACSSDQH Vdq,Hdq,Wdq,Ldq
|
||||
(const void *)&gInstructions[ 3666] // VPMACSSDQH Vdq,Hdq,Wdq,Ldq
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_8e_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[ 3620] // VPMACSSDD Vdq,Hdq,Wdq,Ldq
|
||||
(const void *)&gInstructions[ 3665] // VPMACSSDD Vdq,Hdq,Wdq,Ldq
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_87_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[ 3622] // VPMACSSDQL Vdq,Hdq,Wdq,Ldq
|
||||
(const void *)&gInstructions[ 3667] // VPMACSSDQL Vdq,Hdq,Wdq,Ldq
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_86_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[ 3623] // VPMACSSWD Vdq,Hdq,Wdq,Ldq
|
||||
(const void *)&gInstructions[ 3668] // VPMACSSWD Vdq,Hdq,Wdq,Ldq
|
||||
};
|
||||
|
||||
const ND_TABLE_INSTRUCTION gXopMap_mmmmm_08_opcode_85_leaf =
|
||||
{
|
||||
ND_ILUT_INSTRUCTION,
|
||||
(const void *)&gInstructions[ 3624] // VPMACSSWW Vdq,Hdq,Wdq,Ldq
|
||||
(const void *)&gInstructions[ 3669] // VPMACSSWW Vdq,Hdq,Wdq,Ldq
|
||||
};
|
||||
|
||||
const ND_TABLE_OPCODE gXopMap_mmmmm_08_opcode =
|
||||
|
||||
@ -227,6 +227,7 @@ typedef struct _ND_IDBE
|
||||
ND_UINT8 ExcType; // SSE/VEX/EVEX/OPMASK/AMX/APX exception type.
|
||||
ND_UINT8 FpuFlags; // FPU status word C0, C1, C2 & C3 access type.
|
||||
ND_UINT8 EvexMode; // EVEX prefix extension type.
|
||||
ND_UINT8 SimdExc; // SIMD Floating-Point Exceptions.
|
||||
|
||||
// Per-flag access. Undefined flags will have their bit set in both the "Set" and "Cleared" mask, since a flag
|
||||
// cannot be both cleared and set.
|
||||
|
||||
@ -705,5 +705,33 @@
|
||||
"f_test": "x86/avx10/avx102_64.test",
|
||||
"options": "-b64",
|
||||
"command": "decode"
|
||||
},
|
||||
{
|
||||
"f_source": "x86/movrs/movrs_64.asm",
|
||||
"f_result": "x86/movrs/movrs_64.result",
|
||||
"f_test": "x86/movrs/movrs_64.test",
|
||||
"options": "-b64",
|
||||
"command": "decode"
|
||||
},
|
||||
{
|
||||
"f_source": "x86/movrs/vmovrs_64.asm",
|
||||
"f_result": "x86/movrs/vmovrs_64.result",
|
||||
"f_test": "x86/movrs/vmovrs_64.test",
|
||||
"options": "-b64",
|
||||
"command": "decode"
|
||||
},
|
||||
{
|
||||
"f_source": "x86/sm/sm4_evex_64.asm",
|
||||
"f_result": "x86/sm/sm4_evex_64.result",
|
||||
"f_test": "x86/sm/sm4_evex_64.test",
|
||||
"options": "-b64",
|
||||
"command": "decode"
|
||||
},
|
||||
{
|
||||
"f_source": "x86/amx/amx_evex_64.asm",
|
||||
"f_result": "x86/amx/amx_evex_64.result",
|
||||
"f_test": "x86/amx/amx_evex_64.test",
|
||||
"options": "-b64",
|
||||
"command": "decode"
|
||||
}
|
||||
]
|
||||
@ -25,4 +25,30 @@
|
||||
db 0xc4, 0xe2, 0x7b, 0x5C, 0xF4 ; TDPFP16PS tmm6, tmm4, tmm0
|
||||
|
||||
db 0xc4, 0xe2, 0x78, 0x6C, 0xF4 ; TCMMRLFP16PS tmm6, tmm4, tmm0
|
||||
db 0xc4, 0xe2, 0x79, 0x6C, 0xF4 ; TCMMIMFP16PS tmm6, tmm4, tmm
|
||||
db 0xc4, 0xe2, 0x79, 0x6C, 0xF4 ; TCMMIMFP16PS tmm6, tmm4, tmm
|
||||
|
||||
db 0xc4, 0xe2, 0x78, 0x48, 0xcf ; TTMMULTF32PS tmm1, tmm7, tmm0
|
||||
db 0xc4, 0xe2, 0x79, 0x48, 0xcf ; TMMULTF32PS tmm1, tmm7, tmm0
|
||||
db 0xc4, 0xe2, 0x79, 0x4a, 0x04, 0x11 ; TILELOADDRST1 tmm0, [rcx+rdx]
|
||||
db 0xc4, 0xe2, 0x7b, 0x4a, 0x04, 0x11 ; TILELOADDRS tmm0, [rcx+rdx]
|
||||
db 0xc4, 0xe2, 0x7a, 0x5f, 0xcd ; TTRANSPOSED tmm1, tmm5
|
||||
db 0xc4, 0xe2, 0x78, 0x6b, 0xcd ; TCONJTCMMIMFP16PS tmm1, tmm5, tmm0
|
||||
db 0xc4, 0xe2, 0x78, 0x6b, 0xcd ; TCONJTCMMIMFP16PS tmm1, tmm5, tmm0
|
||||
db 0xc4, 0xe2, 0x79, 0x6b, 0xcd ; TCONJTFP16 tmm1, tmm5
|
||||
db 0xc4, 0xe2, 0x7a, 0x6b, 0xcd ; TTCMMRLFP16PS tmm1, tmm5, tmm0
|
||||
db 0xc4, 0xe2, 0x7b, 0x6b, 0xcd ; TTCMMIMFP16PS tmm1, tmm5, tmm0
|
||||
db 0xc4, 0xe2, 0x7a, 0x6c, 0xcd ; TTDPBF16PS tmm1, tmm5, tmm0
|
||||
db 0xc4, 0xe2, 0x7b, 0x6c, 0xcd ; TTDPFP16PS tmm1, tmm5, tmm0
|
||||
db 0xc4, 0xe2, 0x78, 0x6e, 0x04, 0x11 ; T2RPNTLVWZ0 tmm0+1, [rcx+rdx]
|
||||
db 0xc4, 0xe2, 0x79, 0x6e, 0x04, 0x11 ; T2RPNTLVWZ1 tmm0+1, [rcx+rdx]
|
||||
db 0xc4, 0xe2, 0x78, 0x6f, 0x04, 0x11 ; T2RPNTLVWZ0T1 tmm0+1, [rcx+rdx]
|
||||
db 0xc4, 0xe2, 0x79, 0x6f, 0x04, 0x11 ; T2RPNTLVWZ1T1 tmm0+1, [rcx+rdx]
|
||||
|
||||
db 0xc4, 0xe5, 0x78, 0xf8, 0x04, 0x11 ; T2RPNTLVWZ0RS tmm0+1, [rcx+rdx]
|
||||
db 0xc4, 0xe5, 0x79, 0xf8, 0x04, 0x11 ; T2RPNTLVWZ1RS tmm0+1, [rcx+rdx]
|
||||
db 0xc4, 0xe5, 0x78, 0xf9, 0x04, 0x11 ; T2RPNTLVWZ0RST1 tmm0+1, [rcx+rdx]
|
||||
db 0xc4, 0xe5, 0x79, 0xf9, 0x04, 0x11 ; T2RPNTLVWZ1RST1 tmm0+1, [rcx+rdx]
|
||||
db 0xc4, 0xe5, 0x78, 0xfd, 0xcd ; TDPBF8PS tmm1, tmm5, tmm0
|
||||
db 0xc4, 0xe5, 0x79, 0xfd, 0xcd ; TDPHF8PS tmm1, tmm5, tmm0
|
||||
db 0xc4, 0xe5, 0x7a, 0xfd, 0xcd ; TDPHBF8PS tmm1, tmm5, tmm0
|
||||
db 0xc4, 0xe5, 0x7b, 0xfd, 0xcd ; TDPBHF8PS tmm1, tmm5, tmm0
|
||||
|
||||
@ -331,3 +331,433 @@
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: M, RegType: Tile, RegSize: 1024, RegId: 4, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: V, RegType: Tile, RegSize: 1024, RegId: 0, RegCount: 1
|
||||
|
||||
0000000000000071 c4e27848cf TTMMULTF32PS tmm1, tmm7, tmm0
|
||||
DSIZE: 32, ASIZE: 64, VLEN: -
|
||||
ISA Set: AMX-TRANSPOSE, Ins cat: AMX, CET tracked: no
|
||||
CPUID leaf: 0x0000001e, sub-leaf: 0x00000001, reg: eax, bit: 5
|
||||
Exception class: AMX, exception type: AMX-E10
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: no, Compat: no, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: no, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: RW, Type: Register, Size: 1024, RawSize: 1024, Encoding: R, RegType: Tile, RegSize: 1024, RegId: 1, RegCount: 1
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: M, RegType: Tile, RegSize: 1024, RegId: 7, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: V, RegType: Tile, RegSize: 1024, RegId: 0, RegCount: 1
|
||||
|
||||
0000000000000076 c4e27948cf TMMULTF32PS tmm1, tmm7, tmm0
|
||||
DSIZE: 32, ASIZE: 64, VLEN: -
|
||||
ISA Set: AMX-TF32, Ins cat: AMX, CET tracked: no
|
||||
CPUID leaf: 0x0000001e, sub-leaf: 0x00000001, reg: eax, bit: 6
|
||||
Exception class: AMX, exception type: AMX-E4
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: no, Compat: no, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: no, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: RW, Type: Register, Size: 1024, RawSize: 1024, Encoding: R, RegType: Tile, RegSize: 1024, RegId: 1, RegCount: 1
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: M, RegType: Tile, RegSize: 1024, RegId: 7, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: V, RegType: Tile, RegSize: 1024, RegId: 0, RegCount: 1
|
||||
|
||||
000000000000007B c4e2794a0411 TILELOADDRST1 tmm0, [rcx+rdx]
|
||||
DSIZE: 32, ASIZE: 64, VLEN: -
|
||||
ISA Set: AMX-MOVRS, Ins cat: AMX, CET tracked: no
|
||||
CPUID leaf: 0x0000001e, sub-leaf: 0x00000001, reg: eax, bit: 8
|
||||
Exception class: AMX, exception type: AMX-E3
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: no, Compat: no, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: no, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 1024, RawSize: 1024, Encoding: R, RegType: Tile, RegSize: 1024, RegId: 0, RegCount: 1
|
||||
Operand: 1, Acc: R-, Type: Memory, Size: 1024, RawSize: 1024, Encoding: M, Sibmem Addressing: yes,
|
||||
Segment: 3, Base: 1, Index: 2 * 1,
|
||||
|
||||
0000000000000081 c4e27b4a0411 TILELOADDRS tmm0, [rcx+rdx]
|
||||
DSIZE: 32, ASIZE: 64, VLEN: -
|
||||
ISA Set: AMX-MOVRS, Ins cat: AMX, CET tracked: no
|
||||
CPUID leaf: 0x0000001e, sub-leaf: 0x00000001, reg: eax, bit: 8
|
||||
Exception class: AMX, exception type: AMX-E3
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: no, Compat: no, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: no, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 1024, RawSize: 1024, Encoding: R, RegType: Tile, RegSize: 1024, RegId: 0, RegCount: 1
|
||||
Operand: 1, Acc: R-, Type: Memory, Size: 1024, RawSize: 1024, Encoding: M, Sibmem Addressing: yes,
|
||||
Segment: 3, Base: 1, Index: 2 * 1,
|
||||
|
||||
0000000000000087 c4e27a5fcd TTRANSPOSED tmm1, tmm5
|
||||
DSIZE: 32, ASIZE: 64, VLEN: -
|
||||
ISA Set: AMX-TRANSPOSE, Ins cat: AMX, CET tracked: no
|
||||
CPUID leaf: 0x0000001e, sub-leaf: 0x00000001, reg: eax, bit: 5
|
||||
Exception class: AMX, exception type: AMX-E9
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: no, Compat: no, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: no, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 1024, RawSize: 1024, Encoding: R, RegType: Tile, RegSize: 1024, RegId: 1, RegCount: 1
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: M, RegType: Tile, RegSize: 1024, RegId: 5, RegCount: 1
|
||||
|
||||
000000000000008C c4e2786bcd TCONJTCMMIMFP16PS tmm1, tmm5, tmm0
|
||||
DSIZE: 32, ASIZE: 64, VLEN: -
|
||||
ISA Set: AMX-TRANSPOSE, Ins cat: AMX, CET tracked: no
|
||||
CPUID leaf: 0x0000001e, sub-leaf: 0x00000001, reg: eax, bit: 5
|
||||
Exception class: AMX, exception type: AMX-E10
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: no, Compat: no, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: no, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: RW, Type: Register, Size: 1024, RawSize: 1024, Encoding: R, RegType: Tile, RegSize: 1024, RegId: 1, RegCount: 1
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: M, RegType: Tile, RegSize: 1024, RegId: 5, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: V, RegType: Tile, RegSize: 1024, RegId: 0, RegCount: 1
|
||||
|
||||
0000000000000091 c4e2786bcd TCONJTCMMIMFP16PS tmm1, tmm5, tmm0
|
||||
DSIZE: 32, ASIZE: 64, VLEN: -
|
||||
ISA Set: AMX-TRANSPOSE, Ins cat: AMX, CET tracked: no
|
||||
CPUID leaf: 0x0000001e, sub-leaf: 0x00000001, reg: eax, bit: 5
|
||||
Exception class: AMX, exception type: AMX-E10
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: no, Compat: no, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: no, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: RW, Type: Register, Size: 1024, RawSize: 1024, Encoding: R, RegType: Tile, RegSize: 1024, RegId: 1, RegCount: 1
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: M, RegType: Tile, RegSize: 1024, RegId: 5, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: V, RegType: Tile, RegSize: 1024, RegId: 0, RegCount: 1
|
||||
|
||||
0000000000000096 c4e2796bcd TCONJTFP16 tmm1, tmm5
|
||||
DSIZE: 32, ASIZE: 64, VLEN: -
|
||||
ISA Set: AMX-TRANSPOSE, Ins cat: AMX, CET tracked: no
|
||||
CPUID leaf: 0x0000001e, sub-leaf: 0x00000001, reg: eax, bit: 5
|
||||
Exception class: AMX, exception type: AMX-E9
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: no, Compat: no, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: no, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 1024, RawSize: 1024, Encoding: R, RegType: Tile, RegSize: 1024, RegId: 1, RegCount: 1
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: M, RegType: Tile, RegSize: 1024, RegId: 5, RegCount: 1
|
||||
|
||||
000000000000009B c4e27a6bcd TTCMMRLFP16PS tmm1, tmm5, tmm0
|
||||
DSIZE: 32, ASIZE: 64, VLEN: -
|
||||
ISA Set: AMX-TRANSPOSE, Ins cat: AMX, CET tracked: no
|
||||
CPUID leaf: 0x0000001e, sub-leaf: 0x00000001, reg: eax, bit: 5
|
||||
Exception class: AMX, exception type: AMX-E10
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: no, Compat: no, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: no, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: RW, Type: Register, Size: 1024, RawSize: 1024, Encoding: R, RegType: Tile, RegSize: 1024, RegId: 1, RegCount: 1
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: M, RegType: Tile, RegSize: 1024, RegId: 5, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: V, RegType: Tile, RegSize: 1024, RegId: 0, RegCount: 1
|
||||
|
||||
00000000000000A0 c4e27b6bcd TTCMMIMFP16PS tmm1, tmm5, tmm0
|
||||
DSIZE: 32, ASIZE: 64, VLEN: -
|
||||
ISA Set: AMX-TRANSPOSE, Ins cat: AMX, CET tracked: no
|
||||
CPUID leaf: 0x0000001e, sub-leaf: 0x00000001, reg: eax, bit: 5
|
||||
Exception class: AMX, exception type: AMX-E10
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: no, Compat: no, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: no, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: RW, Type: Register, Size: 1024, RawSize: 1024, Encoding: R, RegType: Tile, RegSize: 1024, RegId: 1, RegCount: 1
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: M, RegType: Tile, RegSize: 1024, RegId: 5, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: V, RegType: Tile, RegSize: 1024, RegId: 0, RegCount: 1
|
||||
|
||||
00000000000000A5 c4e27a6ccd TTDPBF16PS tmm1, tmm5, tmm0
|
||||
DSIZE: 32, ASIZE: 64, VLEN: -
|
||||
ISA Set: AMX-TRANSPOSE, Ins cat: AMX, CET tracked: no
|
||||
CPUID leaf: 0x0000001e, sub-leaf: 0x00000001, reg: eax, bit: 5
|
||||
Exception class: AMX, exception type: AMX-E10
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: no, Compat: no, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: no, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: RW, Type: Register, Size: 1024, RawSize: 1024, Encoding: R, RegType: Tile, RegSize: 1024, RegId: 1, RegCount: 1
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: M, RegType: Tile, RegSize: 1024, RegId: 5, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: V, RegType: Tile, RegSize: 1024, RegId: 0, RegCount: 1
|
||||
|
||||
00000000000000AA c4e27b6ccd TTDPFP16PS tmm1, tmm5, tmm0
|
||||
DSIZE: 32, ASIZE: 64, VLEN: -
|
||||
ISA Set: AMX-TRANSPOSE, Ins cat: AMX, CET tracked: no
|
||||
CPUID leaf: 0x0000001e, sub-leaf: 0x00000001, reg: eax, bit: 5
|
||||
Exception class: AMX, exception type: AMX-E10
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: no, Compat: no, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: no, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: RW, Type: Register, Size: 1024, RawSize: 1024, Encoding: R, RegType: Tile, RegSize: 1024, RegId: 1, RegCount: 1
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: M, RegType: Tile, RegSize: 1024, RegId: 5, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: V, RegType: Tile, RegSize: 1024, RegId: 0, RegCount: 1
|
||||
|
||||
00000000000000AF c4e2786e0411 T2RPNTLVWZ0 tmm0+1, [rcx+rdx]
|
||||
DSIZE: 32, ASIZE: 64, VLEN: -
|
||||
ISA Set: AMX-TRANSPOSE, Ins cat: AMX, CET tracked: no
|
||||
CPUID leaf: 0x0000001e, sub-leaf: 0x00000001, reg: eax, bit: 5
|
||||
Exception class: AMX, exception type: AMX-E11
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: no, Compat: no, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: no, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 1024, RawSize: 1024, Encoding: R, RegType: Tile, RegSize: 1024, RegId: 0, RegCount: 2
|
||||
Operand: 1, Acc: R-, Type: Memory, Size: 1024, RawSize: 1024, Encoding: M, Sibmem Addressing: yes,
|
||||
Segment: 3, Base: 1, Index: 2 * 1,
|
||||
|
||||
00000000000000B5 c4e2796e0411 T2RPNTLVWZ1 tmm0+1, [rcx+rdx]
|
||||
DSIZE: 32, ASIZE: 64, VLEN: -
|
||||
ISA Set: AMX-TRANSPOSE, Ins cat: AMX, CET tracked: no
|
||||
CPUID leaf: 0x0000001e, sub-leaf: 0x00000001, reg: eax, bit: 5
|
||||
Exception class: AMX, exception type: AMX-E11
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: no, Compat: no, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: no, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 1024, RawSize: 1024, Encoding: R, RegType: Tile, RegSize: 1024, RegId: 0, RegCount: 2
|
||||
Operand: 1, Acc: R-, Type: Memory, Size: 1024, RawSize: 1024, Encoding: M, Sibmem Addressing: yes,
|
||||
Segment: 3, Base: 1, Index: 2 * 1,
|
||||
|
||||
00000000000000BB c4e2786f0411 T2RPNTLVWZ0T1 tmm0+1, [rcx+rdx]
|
||||
DSIZE: 32, ASIZE: 64, VLEN: -
|
||||
ISA Set: AMX-TRANSPOSE, Ins cat: AMX, CET tracked: no
|
||||
CPUID leaf: 0x0000001e, sub-leaf: 0x00000001, reg: eax, bit: 5
|
||||
Exception class: AMX, exception type: AMX-E11
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: no, Compat: no, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: no, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 1024, RawSize: 1024, Encoding: R, RegType: Tile, RegSize: 1024, RegId: 0, RegCount: 2
|
||||
Operand: 1, Acc: R-, Type: Memory, Size: 1024, RawSize: 1024, Encoding: M, Sibmem Addressing: yes,
|
||||
Segment: 3, Base: 1, Index: 2 * 1,
|
||||
|
||||
00000000000000C1 c4e2796f0411 T2RPNTLVWZ1T1 tmm0+1, [rcx+rdx]
|
||||
DSIZE: 32, ASIZE: 64, VLEN: -
|
||||
ISA Set: AMX-TRANSPOSE, Ins cat: AMX, CET tracked: no
|
||||
CPUID leaf: 0x0000001e, sub-leaf: 0x00000001, reg: eax, bit: 5
|
||||
Exception class: AMX, exception type: AMX-E11
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: no, Compat: no, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: no, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 1024, RawSize: 1024, Encoding: R, RegType: Tile, RegSize: 1024, RegId: 0, RegCount: 2
|
||||
Operand: 1, Acc: R-, Type: Memory, Size: 1024, RawSize: 1024, Encoding: M, Sibmem Addressing: yes,
|
||||
Segment: 3, Base: 1, Index: 2 * 1,
|
||||
|
||||
00000000000000C7 c4e578f80411 T2RPNTLVWZ0RS tmm0+1, [rcx+rdx]
|
||||
DSIZE: 32, ASIZE: 64, VLEN: -
|
||||
ISA Set: AMX-TRANSPOSE, Ins cat: AMX, CET tracked: no
|
||||
CPUID leaf: 0x0000001e, sub-leaf: 0x00000001, reg: eax, bit: 5
|
||||
Exception class: AMX, exception type: AMX-E11
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: no, Compat: no, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: no, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 1024, RawSize: 1024, Encoding: R, RegType: Tile, RegSize: 1024, RegId: 0, RegCount: 2
|
||||
Operand: 1, Acc: R-, Type: Memory, Size: 1024, RawSize: 1024, Encoding: M, Sibmem Addressing: yes,
|
||||
Segment: 3, Base: 1, Index: 2 * 1,
|
||||
|
||||
00000000000000CD c4e579f80411 T2RPNTLVWZ1RS tmm0+1, [rcx+rdx]
|
||||
DSIZE: 32, ASIZE: 64, VLEN: -
|
||||
ISA Set: AMX-TRANSPOSE, Ins cat: AMX, CET tracked: no
|
||||
CPUID leaf: 0x0000001e, sub-leaf: 0x00000001, reg: eax, bit: 5
|
||||
Exception class: AMX, exception type: AMX-E11
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: no, Compat: no, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: no, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 1024, RawSize: 1024, Encoding: R, RegType: Tile, RegSize: 1024, RegId: 0, RegCount: 2
|
||||
Operand: 1, Acc: R-, Type: Memory, Size: 1024, RawSize: 1024, Encoding: M, Sibmem Addressing: yes,
|
||||
Segment: 3, Base: 1, Index: 2 * 1,
|
||||
|
||||
00000000000000D3 c4e578f90411 T2RPNTLVWZ0RST1 tmm0+1, [rcx+rdx]
|
||||
DSIZE: 32, ASIZE: 64, VLEN: -
|
||||
ISA Set: AMX-TRANSPOSE, Ins cat: AMX, CET tracked: no
|
||||
CPUID leaf: 0x0000001e, sub-leaf: 0x00000001, reg: eax, bit: 5
|
||||
Exception class: AMX, exception type: AMX-E11
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: no, Compat: no, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: no, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 1024, RawSize: 1024, Encoding: R, RegType: Tile, RegSize: 1024, RegId: 0, RegCount: 2
|
||||
Operand: 1, Acc: R-, Type: Memory, Size: 1024, RawSize: 1024, Encoding: M, Sibmem Addressing: yes,
|
||||
Segment: 3, Base: 1, Index: 2 * 1,
|
||||
|
||||
00000000000000D9 c4e579f90411 T2RPNTLVWZ1RST1 tmm0+1, [rcx+rdx]
|
||||
DSIZE: 32, ASIZE: 64, VLEN: -
|
||||
ISA Set: AMX-TRANSPOSE, Ins cat: AMX, CET tracked: no
|
||||
CPUID leaf: 0x0000001e, sub-leaf: 0x00000001, reg: eax, bit: 5
|
||||
Exception class: AMX, exception type: AMX-E11
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: no, Compat: no, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: no, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 1024, RawSize: 1024, Encoding: R, RegType: Tile, RegSize: 1024, RegId: 0, RegCount: 2
|
||||
Operand: 1, Acc: R-, Type: Memory, Size: 1024, RawSize: 1024, Encoding: M, Sibmem Addressing: yes,
|
||||
Segment: 3, Base: 1, Index: 2 * 1,
|
||||
|
||||
00000000000000DF c4e578fdcd TDPBF8PS tmm1, tmm5, tmm0
|
||||
DSIZE: 32, ASIZE: 64, VLEN: -
|
||||
ISA Set: AMX-FP8, Ins cat: AMX, CET tracked: no
|
||||
CPUID leaf: 0x0000001e, sub-leaf: 0x00000001, reg: eax, bit: 4
|
||||
Exception class: AMX, exception type: AMX-E4
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: no, Compat: no, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: no, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: RW, Type: Register, Size: 1024, RawSize: 1024, Encoding: R, RegType: Tile, RegSize: 1024, RegId: 1, RegCount: 1
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: M, RegType: Tile, RegSize: 1024, RegId: 5, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: V, RegType: Tile, RegSize: 1024, RegId: 0, RegCount: 1
|
||||
|
||||
00000000000000E4 c4e579fdcd TDPHF8PS tmm1, tmm5, tmm0
|
||||
DSIZE: 32, ASIZE: 64, VLEN: -
|
||||
ISA Set: AMX-FP8, Ins cat: AMX, CET tracked: no
|
||||
CPUID leaf: 0x0000001e, sub-leaf: 0x00000001, reg: eax, bit: 4
|
||||
Exception class: AMX, exception type: AMX-E4
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: no, Compat: no, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: no, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: RW, Type: Register, Size: 1024, RawSize: 1024, Encoding: R, RegType: Tile, RegSize: 1024, RegId: 1, RegCount: 1
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: M, RegType: Tile, RegSize: 1024, RegId: 5, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: V, RegType: Tile, RegSize: 1024, RegId: 0, RegCount: 1
|
||||
|
||||
00000000000000E9 c4e57afdcd TDPHBF8PS tmm1, tmm5, tmm0
|
||||
DSIZE: 32, ASIZE: 64, VLEN: -
|
||||
ISA Set: AMX-FP8, Ins cat: AMX, CET tracked: no
|
||||
CPUID leaf: 0x0000001e, sub-leaf: 0x00000001, reg: eax, bit: 4
|
||||
Exception class: AMX, exception type: AMX-E4
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: no, Compat: no, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: no, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: RW, Type: Register, Size: 1024, RawSize: 1024, Encoding: R, RegType: Tile, RegSize: 1024, RegId: 1, RegCount: 1
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: M, RegType: Tile, RegSize: 1024, RegId: 5, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: V, RegType: Tile, RegSize: 1024, RegId: 0, RegCount: 1
|
||||
|
||||
00000000000000EE c4e57bfdcd TDPBHF8PS tmm1, tmm5, tmm0
|
||||
DSIZE: 32, ASIZE: 64, VLEN: -
|
||||
ISA Set: AMX-FP8, Ins cat: AMX, CET tracked: no
|
||||
CPUID leaf: 0x0000001e, sub-leaf: 0x00000001, reg: eax, bit: 4
|
||||
Exception class: AMX, exception type: AMX-E4
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: no, Compat: no, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: no, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: RW, Type: Register, Size: 1024, RawSize: 1024, Encoding: R, RegType: Tile, RegSize: 1024, RegId: 1, RegCount: 1
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: M, RegType: Tile, RegSize: 1024, RegId: 5, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: V, RegType: Tile, RegSize: 1024, RegId: 0, RegCount: 1
|
||||
|
||||
|
||||
Binary file not shown.
228
bddisasm_test/x86/amx/amx_evex_64.result
Normal file
228
bddisasm_test/x86/amx/amx_evex_64.result
Normal file
@ -0,0 +1,228 @@
|
||||
0000000000000000 62f27e484ade TCVTROWD2PS zmm3, tmm6, eax
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 512
|
||||
ISA Set: AMX-AVX512, Ins cat: AMX, CET tracked: no
|
||||
CPUID leaf: 0x0000001e, sub-leaf: 0x00000001, reg: eax, bit: 7
|
||||
EVEX Tuple Type: None
|
||||
Exception class: APX, exception type: AMX-EVEX-E8
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: no, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 3, RegCount: 1
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: M, RegType: Tile, RegSize: 1024, RegId: 6, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1
|
||||
|
||||
0000000000000006 62f37e4807debd TCVTROWD2PS zmm3, tmm6, 0xbd
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 512
|
||||
ISA Set: AMX-AVX512, Ins cat: AMX, CET tracked: no
|
||||
CPUID leaf: 0x0000001e, sub-leaf: 0x00000001, reg: eax, bit: 7
|
||||
EVEX Tuple Type: None
|
||||
Exception class: APX, exception type: AMX-EVEX-E7
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: no, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 3, RegCount: 1
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: M, RegType: Tile, RegSize: 1024, RegId: 6, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I
|
||||
|
||||
000000000000000D 62f27f486dde TCVTROWPS2PBF16H zmm3, tmm6, eax
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 512
|
||||
ISA Set: AMX-AVX512, Ins cat: AMX, CET tracked: no
|
||||
CPUID leaf: 0x0000001e, sub-leaf: 0x00000001, reg: eax, bit: 7
|
||||
EVEX Tuple Type: None
|
||||
Exception class: APX, exception type: AMX-EVEX-E8
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: no, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 3, RegCount: 1
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: M, RegType: Tile, RegSize: 1024, RegId: 6, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1
|
||||
|
||||
0000000000000013 62f37f4807debd TCVTROWPS2PBF16H zmm3, tmm6, 0xbd
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 512
|
||||
ISA Set: AMX-AVX512, Ins cat: AMX, CET tracked: no
|
||||
CPUID leaf: 0x0000001e, sub-leaf: 0x00000001, reg: eax, bit: 7
|
||||
EVEX Tuple Type: None
|
||||
Exception class: APX, exception type: AMX-EVEX-E7
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: no, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 3, RegCount: 1
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: M, RegType: Tile, RegSize: 1024, RegId: 6, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I
|
||||
|
||||
000000000000001A 62f27e486dde TCVTROWPS2PBF16L zmm3, tmm6, eax
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 512
|
||||
ISA Set: AMX-AVX512, Ins cat: AMX, CET tracked: no
|
||||
CPUID leaf: 0x0000001e, sub-leaf: 0x00000001, reg: eax, bit: 7
|
||||
EVEX Tuple Type: None
|
||||
Exception class: APX, exception type: AMX-EVEX-E8
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: no, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 3, RegCount: 1
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: M, RegType: Tile, RegSize: 1024, RegId: 6, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1
|
||||
|
||||
0000000000000020 62f37e4877debd TCVTROWPS2PBF16L zmm3, tmm6, 0xbd
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 512
|
||||
ISA Set: AMX-AVX512, Ins cat: AMX, CET tracked: no
|
||||
CPUID leaf: 0x0000001e, sub-leaf: 0x00000001, reg: eax, bit: 7
|
||||
EVEX Tuple Type: None
|
||||
Exception class: APX, exception type: AMX-EVEX-E7
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: no, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 3, RegCount: 1
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: M, RegType: Tile, RegSize: 1024, RegId: 6, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I
|
||||
|
||||
0000000000000027 62f27c486dde TCVTROWPS2PHH zmm3, tmm6, eax
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 512
|
||||
ISA Set: AMX-AVX512, Ins cat: AMX, CET tracked: no
|
||||
CPUID leaf: 0x0000001e, sub-leaf: 0x00000001, reg: eax, bit: 7
|
||||
EVEX Tuple Type: None
|
||||
Exception class: APX, exception type: AMX-EVEX-E8
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: no, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 3, RegCount: 1
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: M, RegType: Tile, RegSize: 1024, RegId: 6, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1
|
||||
|
||||
000000000000002D 62f37c4807debd TCVTROWPS2PHH zmm3, tmm6, 0xbd
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 512
|
||||
ISA Set: AMX-AVX512, Ins cat: AMX, CET tracked: no
|
||||
CPUID leaf: 0x0000001e, sub-leaf: 0x00000001, reg: eax, bit: 7
|
||||
EVEX Tuple Type: None
|
||||
Exception class: APX, exception type: AMX-EVEX-E7
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: no, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 3, RegCount: 1
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: M, RegType: Tile, RegSize: 1024, RegId: 6, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I
|
||||
|
||||
0000000000000034 62f27d486dde TCVTROWPS2PHL zmm3, tmm6, eax
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 512
|
||||
ISA Set: AMX-AVX512, Ins cat: AMX, CET tracked: no
|
||||
CPUID leaf: 0x0000001e, sub-leaf: 0x00000001, reg: eax, bit: 7
|
||||
EVEX Tuple Type: None
|
||||
Exception class: APX, exception type: AMX-EVEX-E8
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: no, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 3, RegCount: 1
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: M, RegType: Tile, RegSize: 1024, RegId: 6, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1
|
||||
|
||||
000000000000003A 62f37f4877debd TCVTROWPS2PHL zmm3, tmm6, 0xbd
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 512
|
||||
ISA Set: AMX-AVX512, Ins cat: AMX, CET tracked: no
|
||||
CPUID leaf: 0x0000001e, sub-leaf: 0x00000001, reg: eax, bit: 7
|
||||
EVEX Tuple Type: None
|
||||
Exception class: APX, exception type: AMX-EVEX-E7
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: no, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 3, RegCount: 1
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: M, RegType: Tile, RegSize: 1024, RegId: 6, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I
|
||||
|
||||
0000000000000041 62f27d484ade TILEMOVROW zmm3, tmm6, eax
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 512
|
||||
ISA Set: AMX-AVX512, Ins cat: AMX, CET tracked: no
|
||||
CPUID leaf: 0x0000001e, sub-leaf: 0x00000001, reg: eax, bit: 7
|
||||
EVEX Tuple Type: None
|
||||
Exception class: APX, exception type: AMX-EVEX-E8
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: no, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 3, RegCount: 1
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: M, RegType: Tile, RegSize: 1024, RegId: 6, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: V, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1
|
||||
|
||||
0000000000000047 62f37d4807debd TILEMOVROW zmm3, tmm6, 0xbd
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 512
|
||||
ISA Set: AMX-AVX512, Ins cat: AMX, CET tracked: no
|
||||
CPUID leaf: 0x0000001e, sub-leaf: 0x00000001, reg: eax, bit: 7
|
||||
EVEX Tuple Type: None
|
||||
Exception class: APX, exception type: AMX-EVEX-E7
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: no, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 3, RegCount: 1
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 1024, RawSize: 1024, Encoding: M, RegType: Tile, RegSize: 1024, RegId: 6, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Immediate, Size: 1, RawSize: 1, Encoding: I
|
||||
|
||||
1
bddisasm_test/x86/amx/amx_evex_64.test
Normal file
1
bddisasm_test/x86/amx/amx_evex_64.test
Normal file
@ -0,0 +1 @@
|
||||
b<EFBFBD>HJﾞb<EFBFBD>Hﾞｽb<EFBDBD>Hmﾞb<EFBE9E>Hﾞｽb<EFBDBD>Hmﾞb<EFBE9E>Hwﾞｽb<EFBDBD>Hmﾞb<EFBE9E>Hﾞｽb<EFBDBD>Hmﾞb<EFBE9E>Hwﾞｽb<EFBDBD>HJﾞb<EFBE9E>Hﾞｽ
|
||||
File diff suppressed because it is too large
Load Diff
@ -3,6 +3,7 @@
|
||||
ISA Set: F16C, Ins cat: CONVERT, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: ecx, bit: 29
|
||||
Exception class: SSE/VEX, exception type: 11
|
||||
SIMD Exceptions: I
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -20,6 +21,7 @@
|
||||
ISA Set: F16C, Ins cat: CONVERT, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: ecx, bit: 29
|
||||
Exception class: SSE/VEX, exception type: 11
|
||||
SIMD Exceptions: I
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -37,6 +39,7 @@
|
||||
ISA Set: F16C, Ins cat: CONVERT, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: ecx, bit: 29
|
||||
Exception class: SSE/VEX, exception type: 11
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -55,6 +58,7 @@
|
||||
ISA Set: F16C, Ins cat: CONVERT, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: ecx, bit: 29
|
||||
Exception class: SSE/VEX, exception type: 11
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -73,6 +77,7 @@
|
||||
ISA Set: F16C, Ins cat: CONVERT, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: ecx, bit: 29
|
||||
Exception class: SSE/VEX, exception type: 11
|
||||
SIMD Exceptions: I
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -91,6 +96,7 @@
|
||||
ISA Set: F16C, Ins cat: CONVERT, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: ecx, bit: 29
|
||||
Exception class: SSE/VEX, exception type: 11
|
||||
SIMD Exceptions: I
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -109,6 +115,7 @@
|
||||
ISA Set: F16C, Ins cat: CONVERT, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: ecx, bit: 29
|
||||
Exception class: SSE/VEX, exception type: 11
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -128,6 +135,7 @@
|
||||
ISA Set: F16C, Ins cat: CONVERT, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: ecx, bit: 29
|
||||
Exception class: SSE/VEX, exception type: 11
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
|
||||
@ -2,6 +2,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -20,6 +21,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -38,6 +40,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -56,6 +59,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -74,6 +78,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -92,6 +97,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -110,6 +116,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -128,6 +135,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -146,6 +154,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -164,6 +173,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -182,6 +192,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -200,6 +211,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -218,6 +230,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -236,6 +249,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -254,6 +268,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -272,6 +287,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -290,6 +306,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -308,6 +325,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -326,6 +344,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -344,6 +363,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -362,6 +382,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -380,6 +401,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -398,6 +420,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -416,6 +439,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -434,6 +458,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -452,6 +477,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -470,6 +496,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -488,6 +515,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -506,6 +534,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -524,6 +553,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -542,6 +572,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -560,6 +591,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -578,6 +610,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -596,6 +629,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -614,6 +648,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -632,6 +667,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -650,6 +686,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -668,6 +705,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -686,6 +724,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -704,6 +743,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -722,6 +762,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -741,6 +782,7 @@
|
||||
DSIZE: 64, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -760,6 +802,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -779,6 +822,7 @@
|
||||
DSIZE: 64, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -798,6 +842,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -817,6 +862,7 @@
|
||||
DSIZE: 64, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -836,6 +882,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -855,6 +902,7 @@
|
||||
DSIZE: 64, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -874,6 +922,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -893,6 +942,7 @@
|
||||
DSIZE: 64, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -912,6 +962,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -931,6 +982,7 @@
|
||||
DSIZE: 64, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -950,6 +1002,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -969,6 +1022,7 @@
|
||||
DSIZE: 64, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -988,6 +1042,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -1007,6 +1062,7 @@
|
||||
DSIZE: 64, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -1026,6 +1082,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -1045,6 +1102,7 @@
|
||||
DSIZE: 64, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -1064,6 +1122,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -1083,6 +1142,7 @@
|
||||
DSIZE: 64, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -1102,6 +1162,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -1121,6 +1182,7 @@
|
||||
DSIZE: 64, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -1140,6 +1202,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -1159,6 +1222,7 @@
|
||||
DSIZE: 64, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -1178,6 +1242,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -1197,6 +1262,7 @@
|
||||
DSIZE: 64, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -1216,6 +1282,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -1235,6 +1302,7 @@
|
||||
DSIZE: 64, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -1254,6 +1322,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -1273,6 +1342,7 @@
|
||||
DSIZE: 64, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -1292,6 +1362,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -1311,6 +1382,7 @@
|
||||
DSIZE: 64, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -1330,6 +1402,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -1349,6 +1422,7 @@
|
||||
DSIZE: 64, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -1368,6 +1442,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -1387,6 +1462,7 @@
|
||||
DSIZE: 64, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -1406,6 +1482,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -1425,6 +1502,7 @@
|
||||
DSIZE: 64, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -1444,6 +1522,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -1463,6 +1542,7 @@
|
||||
DSIZE: 64, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -1482,6 +1562,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 256
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -1500,6 +1581,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 256
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -1518,6 +1600,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 256
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -1536,6 +1619,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 256
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -1554,6 +1638,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 256
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -1572,6 +1657,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 256
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -1590,6 +1676,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 256
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -1608,6 +1695,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 256
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -1626,6 +1714,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 256
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -1644,6 +1733,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 256
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -1662,6 +1752,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 256
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -1680,6 +1771,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 256
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -1698,6 +1790,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 256
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -1716,6 +1809,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 256
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -1734,6 +1828,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 256
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -1752,6 +1847,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 256
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -1770,6 +1866,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 256
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -1788,6 +1885,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 256
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -1806,6 +1904,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 256
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -1824,6 +1923,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 256
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -1842,6 +1942,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 256
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -1860,6 +1961,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 256
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -1878,6 +1980,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 256
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -1896,6 +1999,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 256
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -1914,6 +2018,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 256
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -1933,6 +2038,7 @@
|
||||
DSIZE: 64, ASIZE: 64, VLEN: 256
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -1952,6 +2058,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 256
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -1971,6 +2078,7 @@
|
||||
DSIZE: 64, ASIZE: 64, VLEN: 256
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -1990,6 +2098,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 256
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -2009,6 +2118,7 @@
|
||||
DSIZE: 64, ASIZE: 64, VLEN: 256
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -2028,6 +2138,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 256
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -2047,6 +2158,7 @@
|
||||
DSIZE: 64, ASIZE: 64, VLEN: 256
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -2066,6 +2178,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 256
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -2085,6 +2198,7 @@
|
||||
DSIZE: 64, ASIZE: 64, VLEN: 256
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -2104,6 +2218,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 256
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -2123,6 +2238,7 @@
|
||||
DSIZE: 64, ASIZE: 64, VLEN: 256
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -2142,6 +2258,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 256
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -2161,6 +2278,7 @@
|
||||
DSIZE: 64, ASIZE: 64, VLEN: 256
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -2180,6 +2298,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 256
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -2199,6 +2318,7 @@
|
||||
DSIZE: 64, ASIZE: 64, VLEN: 256
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -2218,6 +2338,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 256
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -2237,6 +2358,7 @@
|
||||
DSIZE: 64, ASIZE: 64, VLEN: 256
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -2256,6 +2378,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 256
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -2275,6 +2398,7 @@
|
||||
DSIZE: 64, ASIZE: 64, VLEN: 256
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -2294,6 +2418,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 256
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -2313,6 +2438,7 @@
|
||||
DSIZE: 64, ASIZE: 64, VLEN: 256
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -2332,6 +2458,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 256
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -2351,6 +2478,7 @@
|
||||
DSIZE: 64, ASIZE: 64, VLEN: 256
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -4,6 +4,7 @@
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17
|
||||
EVEX Tuple Type: Full
|
||||
Exception class: EVEX, exception type: E2
|
||||
SIMD Exceptions: IP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -23,6 +24,7 @@
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 17
|
||||
EVEX Tuple Type: Full
|
||||
Exception class: EVEX, exception type: E2
|
||||
SIMD Exceptions: IP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because one or more lines are too long
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
9
bddisasm_test/x86/movrs/movrs_64.asm
Normal file
9
bddisasm_test/x86/movrs/movrs_64.asm
Normal file
@ -0,0 +1,9 @@
|
||||
bits 64
|
||||
|
||||
db 0x0F, 0x38, 0x8B, 0x00
|
||||
db 0x48, 0x0F, 0x38, 0x8B, 0x10
|
||||
db 0x66, 0x0F, 0x38, 0x8B, 0x10
|
||||
db 0x0F, 0x38, 0x8A, 0x00
|
||||
db 0x48, 0x0F, 0x38, 0x8A, 0x10
|
||||
db 0x66, 0x0F, 0x38, 0x8A, 0x10
|
||||
db 0x0F, 0x18, 0x20
|
||||
118
bddisasm_test/x86/movrs/movrs_64.result
Normal file
118
bddisasm_test/x86/movrs/movrs_64.result
Normal file
@ -0,0 +1,118 @@
|
||||
0000000000000000 0f388b00 MOVRS eax, dword ptr [rax]
|
||||
DSIZE: 32, ASIZE: 64, VLEN: -
|
||||
ISA Set: MOVRS, Ins cat: DATAXFER, CET tracked: no
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 31
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: no, Compat: no, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 4, RawSize: 4, Encoding: R, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1
|
||||
Operand: 1, Acc: R-, Type: Memory, Size: 4, RawSize: 4, Encoding: M,
|
||||
Segment: 3, Base: 0,
|
||||
|
||||
0000000000000004 480f388b10 MOVRS rdx, qword ptr [rax]
|
||||
DSIZE: 64, ASIZE: 64, VLEN: -
|
||||
ISA Set: MOVRS, Ins cat: DATAXFER, CET tracked: no
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 31
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: no, Compat: no, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 2, RegCount: 1
|
||||
Operand: 1, Acc: R-, Type: Memory, Size: 8, RawSize: 8, Encoding: M,
|
||||
Segment: 3, Base: 0,
|
||||
|
||||
0000000000000009 660f388b10 MOVRS dx, word ptr [rax]
|
||||
DSIZE: 16, ASIZE: 64, VLEN: -
|
||||
ISA Set: MOVRS, Ins cat: DATAXFER, CET tracked: no
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 31
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: no, Compat: no, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 2, RawSize: 2, Encoding: R, RegType: General Purpose, RegSize: 2, RegId: 2, RegCount: 1
|
||||
Operand: 1, Acc: R-, Type: Memory, Size: 2, RawSize: 2, Encoding: M,
|
||||
Segment: 3, Base: 0,
|
||||
|
||||
000000000000000E 0f388a00 MOVRS al, byte ptr [rax]
|
||||
DSIZE: 32, ASIZE: 64, VLEN: -
|
||||
ISA Set: MOVRS, Ins cat: DATAXFER, CET tracked: no
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 31
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: no, Compat: no, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 0, RegCount: 1
|
||||
Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M,
|
||||
Segment: 3, Base: 0,
|
||||
|
||||
0000000000000012 480f388a10 MOVRS dl, byte ptr [rax]
|
||||
DSIZE: 64, ASIZE: 64, VLEN: -
|
||||
ISA Set: MOVRS, Ins cat: DATAXFER, CET tracked: no
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 31
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: no, Compat: no, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 2, RegCount: 1
|
||||
Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M,
|
||||
Segment: 3, Base: 0,
|
||||
|
||||
0000000000000017 660f388a10 MOVRS dl, byte ptr [rax]
|
||||
DSIZE: 16, ASIZE: 64, VLEN: -
|
||||
ISA Set: MOVRS, Ins cat: DATAXFER, CET tracked: no
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 31
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: no, Compat: no, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 1, RawSize: 1, Encoding: R, RegType: General Purpose, RegSize: 1, RegId: 2, RegCount: 1
|
||||
Operand: 1, Acc: R-, Type: Memory, Size: 1, RawSize: 1, Encoding: M,
|
||||
Segment: 3, Base: 0,
|
||||
|
||||
000000000000001C 0f1820 PREFETCHRST2 byte ptr [rax]
|
||||
DSIZE: 32, ASIZE: 64, VLEN: -
|
||||
ISA Set: MOVRS, Ins cat: PREFETCH, CET tracked: no
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 31
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: P, Type: Memory, Size: 1, RawSize: 1, Encoding: M,
|
||||
Segment: 3, Base: 0,
|
||||
|
||||
BIN
bddisasm_test/x86/movrs/movrs_64.test
Normal file
BIN
bddisasm_test/x86/movrs/movrs_64.test
Normal file
Binary file not shown.
756
bddisasm_test/x86/movrs/vmovrs_64.result
Normal file
756
bddisasm_test/x86/movrs/vmovrs_64.result
Normal file
@ -0,0 +1,756 @@
|
||||
0000000000000000 62fd7f086f1e VMOVRSB xmm3, xmmword ptr [r22]
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: MOVRS, Ins cat: DATAXFER, CET tracked: no
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 31
|
||||
EVEX Tuple Type: Full Mem
|
||||
Exception class: EVEX, exception type: E4
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 3, RegCount: 1
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M,
|
||||
Segment: 3, Base: 22,
|
||||
|
||||
0000000000000006 62fd7f286f1e VMOVRSB ymm3, ymmword ptr [r22]
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 256
|
||||
ISA Set: MOVRS, Ins cat: DATAXFER, CET tracked: no
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 31
|
||||
EVEX Tuple Type: Full Mem
|
||||
Exception class: EVEX, exception type: E4
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 3, RegCount: 1
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M,
|
||||
Segment: 3, Base: 22,
|
||||
|
||||
000000000000000C 62fd7f486f1e VMOVRSB zmm3, zmmword ptr [r22]
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 512
|
||||
ISA Set: MOVRS, Ins cat: DATAXFER, CET tracked: no
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 31
|
||||
EVEX Tuple Type: Full Mem
|
||||
Exception class: EVEX, exception type: E4
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 3, RegCount: 1
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M,
|
||||
Segment: 3, Base: 22,
|
||||
|
||||
0000000000000012 62fd7f0f6f1e VMOVRSB xmm3{k7}, xmmword ptr [r22]
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: MOVRS, Ins cat: DATAXFER, CET tracked: no
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 31
|
||||
EVEX Tuple Type: Full Mem
|
||||
Exception class: EVEX, exception type: E4
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 3, RegCount: 1
|
||||
Decorator: Mask k7
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 7, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M,
|
||||
Segment: 3, Base: 22,
|
||||
|
||||
0000000000000018 62fd7f2f6f1e VMOVRSB ymm3{k7}, ymmword ptr [r22]
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 256
|
||||
ISA Set: MOVRS, Ins cat: DATAXFER, CET tracked: no
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 31
|
||||
EVEX Tuple Type: Full Mem
|
||||
Exception class: EVEX, exception type: E4
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 3, RegCount: 1
|
||||
Decorator: Mask k7
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 7, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M,
|
||||
Segment: 3, Base: 22,
|
||||
|
||||
000000000000001E 62fd7f4f6f1e VMOVRSB zmm3{k7}, zmmword ptr [r22]
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 512
|
||||
ISA Set: MOVRS, Ins cat: DATAXFER, CET tracked: no
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 31
|
||||
EVEX Tuple Type: Full Mem
|
||||
Exception class: EVEX, exception type: E4
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 3, RegCount: 1
|
||||
Decorator: Mask k7
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 7, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M,
|
||||
Segment: 3, Base: 22,
|
||||
|
||||
0000000000000024 62fd7f8f6f1e VMOVRSB xmm3{k7}{z}, xmmword ptr [r22]
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: MOVRS, Ins cat: DATAXFER, CET tracked: no
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 31
|
||||
EVEX Tuple Type: Full Mem
|
||||
Exception class: EVEX, exception type: E4
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 3, RegCount: 1
|
||||
Decorator: Mask k7
|
||||
Decorator: Zero (no merging)
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 7, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M,
|
||||
Segment: 3, Base: 22,
|
||||
|
||||
000000000000002A 62fd7faf6f1e VMOVRSB ymm3{k7}{z}, ymmword ptr [r22]
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 256
|
||||
ISA Set: MOVRS, Ins cat: DATAXFER, CET tracked: no
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 31
|
||||
EVEX Tuple Type: Full Mem
|
||||
Exception class: EVEX, exception type: E4
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 3, RegCount: 1
|
||||
Decorator: Mask k7
|
||||
Decorator: Zero (no merging)
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 7, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M,
|
||||
Segment: 3, Base: 22,
|
||||
|
||||
0000000000000030 62fd7fcf6f1e VMOVRSB zmm3{k7}{z}, zmmword ptr [r22]
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 512
|
||||
ISA Set: MOVRS, Ins cat: DATAXFER, CET tracked: no
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 31
|
||||
EVEX Tuple Type: Full Mem
|
||||
Exception class: EVEX, exception type: E4
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 3, RegCount: 1
|
||||
Decorator: Mask k7
|
||||
Decorator: Zero (no merging)
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 7, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M,
|
||||
Segment: 3, Base: 22,
|
||||
|
||||
0000000000000036 62fd7e086f1e VMOVRSD xmm3, xmmword ptr [r22]
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: MOVRS, Ins cat: DATAXFER, CET tracked: no
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 31
|
||||
EVEX Tuple Type: Full Mem
|
||||
Exception class: EVEX, exception type: E4
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 3, RegCount: 1
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M,
|
||||
Segment: 3, Base: 22,
|
||||
|
||||
000000000000003C 62fd7e286f1e VMOVRSD ymm3, ymmword ptr [r22]
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 256
|
||||
ISA Set: MOVRS, Ins cat: DATAXFER, CET tracked: no
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 31
|
||||
EVEX Tuple Type: Full Mem
|
||||
Exception class: EVEX, exception type: E4
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 3, RegCount: 1
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M,
|
||||
Segment: 3, Base: 22,
|
||||
|
||||
0000000000000042 62fd7e486f1e VMOVRSD zmm3, zmmword ptr [r22]
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 512
|
||||
ISA Set: MOVRS, Ins cat: DATAXFER, CET tracked: no
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 31
|
||||
EVEX Tuple Type: Full Mem
|
||||
Exception class: EVEX, exception type: E4
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 3, RegCount: 1
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M,
|
||||
Segment: 3, Base: 22,
|
||||
|
||||
0000000000000048 62fd7e0f6f1e VMOVRSD xmm3{k7}, xmmword ptr [r22]
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: MOVRS, Ins cat: DATAXFER, CET tracked: no
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 31
|
||||
EVEX Tuple Type: Full Mem
|
||||
Exception class: EVEX, exception type: E4
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 3, RegCount: 1
|
||||
Decorator: Mask k7
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 7, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M,
|
||||
Segment: 3, Base: 22,
|
||||
|
||||
000000000000004E 62fd7e2f6f1e VMOVRSD ymm3{k7}, ymmword ptr [r22]
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 256
|
||||
ISA Set: MOVRS, Ins cat: DATAXFER, CET tracked: no
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 31
|
||||
EVEX Tuple Type: Full Mem
|
||||
Exception class: EVEX, exception type: E4
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 3, RegCount: 1
|
||||
Decorator: Mask k7
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 7, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M,
|
||||
Segment: 3, Base: 22,
|
||||
|
||||
0000000000000054 62fd7e4f6f1e VMOVRSD zmm3{k7}, zmmword ptr [r22]
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 512
|
||||
ISA Set: MOVRS, Ins cat: DATAXFER, CET tracked: no
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 31
|
||||
EVEX Tuple Type: Full Mem
|
||||
Exception class: EVEX, exception type: E4
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 3, RegCount: 1
|
||||
Decorator: Mask k7
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 7, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M,
|
||||
Segment: 3, Base: 22,
|
||||
|
||||
000000000000005A 62fd7e8f6f1e VMOVRSD xmm3{k7}{z}, xmmword ptr [r22]
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: MOVRS, Ins cat: DATAXFER, CET tracked: no
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 31
|
||||
EVEX Tuple Type: Full Mem
|
||||
Exception class: EVEX, exception type: E4
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 3, RegCount: 1
|
||||
Decorator: Mask k7
|
||||
Decorator: Zero (no merging)
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 7, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M,
|
||||
Segment: 3, Base: 22,
|
||||
|
||||
0000000000000060 62fd7eaf6f1e VMOVRSD ymm3{k7}{z}, ymmword ptr [r22]
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 256
|
||||
ISA Set: MOVRS, Ins cat: DATAXFER, CET tracked: no
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 31
|
||||
EVEX Tuple Type: Full Mem
|
||||
Exception class: EVEX, exception type: E4
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 3, RegCount: 1
|
||||
Decorator: Mask k7
|
||||
Decorator: Zero (no merging)
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 7, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M,
|
||||
Segment: 3, Base: 22,
|
||||
|
||||
0000000000000066 62fd7ecf6f1e VMOVRSD zmm3{k7}{z}, zmmword ptr [r22]
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 512
|
||||
ISA Set: MOVRS, Ins cat: DATAXFER, CET tracked: no
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 31
|
||||
EVEX Tuple Type: Full Mem
|
||||
Exception class: EVEX, exception type: E4
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 3, RegCount: 1
|
||||
Decorator: Mask k7
|
||||
Decorator: Zero (no merging)
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 7, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M,
|
||||
Segment: 3, Base: 22,
|
||||
|
||||
000000000000006C 62fdfe086f1e VMOVRSQ xmm3, xmmword ptr [r22]
|
||||
DSIZE: 64, ASIZE: 64, VLEN: 128
|
||||
ISA Set: MOVRS, Ins cat: DATAXFER, CET tracked: no
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 31
|
||||
EVEX Tuple Type: Full Mem
|
||||
Exception class: EVEX, exception type: E4
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 3, RegCount: 1
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M,
|
||||
Segment: 3, Base: 22,
|
||||
|
||||
0000000000000072 62fdfe286f1e VMOVRSQ ymm3, ymmword ptr [r22]
|
||||
DSIZE: 64, ASIZE: 64, VLEN: 256
|
||||
ISA Set: MOVRS, Ins cat: DATAXFER, CET tracked: no
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 31
|
||||
EVEX Tuple Type: Full Mem
|
||||
Exception class: EVEX, exception type: E4
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 3, RegCount: 1
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M,
|
||||
Segment: 3, Base: 22,
|
||||
|
||||
0000000000000078 62fdfe486f1e VMOVRSQ zmm3, zmmword ptr [r22]
|
||||
DSIZE: 64, ASIZE: 64, VLEN: 512
|
||||
ISA Set: MOVRS, Ins cat: DATAXFER, CET tracked: no
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 31
|
||||
EVEX Tuple Type: Full Mem
|
||||
Exception class: EVEX, exception type: E4
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 3, RegCount: 1
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M,
|
||||
Segment: 3, Base: 22,
|
||||
|
||||
000000000000007E 62fdfe0f6f1e VMOVRSQ xmm3{k7}, xmmword ptr [r22]
|
||||
DSIZE: 64, ASIZE: 64, VLEN: 128
|
||||
ISA Set: MOVRS, Ins cat: DATAXFER, CET tracked: no
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 31
|
||||
EVEX Tuple Type: Full Mem
|
||||
Exception class: EVEX, exception type: E4
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 3, RegCount: 1
|
||||
Decorator: Mask k7
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 7, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M,
|
||||
Segment: 3, Base: 22,
|
||||
|
||||
0000000000000084 62fdfe2f6f1e VMOVRSQ ymm3{k7}, ymmword ptr [r22]
|
||||
DSIZE: 64, ASIZE: 64, VLEN: 256
|
||||
ISA Set: MOVRS, Ins cat: DATAXFER, CET tracked: no
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 31
|
||||
EVEX Tuple Type: Full Mem
|
||||
Exception class: EVEX, exception type: E4
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 3, RegCount: 1
|
||||
Decorator: Mask k7
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 7, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M,
|
||||
Segment: 3, Base: 22,
|
||||
|
||||
000000000000008A 62fdfe4f6f1e VMOVRSQ zmm3{k7}, zmmword ptr [r22]
|
||||
DSIZE: 64, ASIZE: 64, VLEN: 512
|
||||
ISA Set: MOVRS, Ins cat: DATAXFER, CET tracked: no
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 31
|
||||
EVEX Tuple Type: Full Mem
|
||||
Exception class: EVEX, exception type: E4
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 3, RegCount: 1
|
||||
Decorator: Mask k7
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 7, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M,
|
||||
Segment: 3, Base: 22,
|
||||
|
||||
0000000000000090 62fdfe8f6f1e VMOVRSQ xmm3{k7}{z}, xmmword ptr [r22]
|
||||
DSIZE: 64, ASIZE: 64, VLEN: 128
|
||||
ISA Set: MOVRS, Ins cat: DATAXFER, CET tracked: no
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 31
|
||||
EVEX Tuple Type: Full Mem
|
||||
Exception class: EVEX, exception type: E4
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 3, RegCount: 1
|
||||
Decorator: Mask k7
|
||||
Decorator: Zero (no merging)
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 7, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M,
|
||||
Segment: 3, Base: 22,
|
||||
|
||||
0000000000000096 62fdfeaf6f1e VMOVRSQ ymm3{k7}{z}, ymmword ptr [r22]
|
||||
DSIZE: 64, ASIZE: 64, VLEN: 256
|
||||
ISA Set: MOVRS, Ins cat: DATAXFER, CET tracked: no
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 31
|
||||
EVEX Tuple Type: Full Mem
|
||||
Exception class: EVEX, exception type: E4
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 3, RegCount: 1
|
||||
Decorator: Mask k7
|
||||
Decorator: Zero (no merging)
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 7, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M,
|
||||
Segment: 3, Base: 22,
|
||||
|
||||
000000000000009C 62fdfecf6f1e VMOVRSQ zmm3{k7}{z}, zmmword ptr [r22]
|
||||
DSIZE: 64, ASIZE: 64, VLEN: 512
|
||||
ISA Set: MOVRS, Ins cat: DATAXFER, CET tracked: no
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 31
|
||||
EVEX Tuple Type: Full Mem
|
||||
Exception class: EVEX, exception type: E4
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 3, RegCount: 1
|
||||
Decorator: Mask k7
|
||||
Decorator: Zero (no merging)
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 7, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M,
|
||||
Segment: 3, Base: 22,
|
||||
|
||||
00000000000000A2 62fdff086f1e VMOVRSW xmm3, xmmword ptr [r22]
|
||||
DSIZE: 64, ASIZE: 64, VLEN: 128
|
||||
ISA Set: MOVRS, Ins cat: DATAXFER, CET tracked: no
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 31
|
||||
EVEX Tuple Type: Full Mem
|
||||
Exception class: EVEX, exception type: E4
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 3, RegCount: 1
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M,
|
||||
Segment: 3, Base: 22,
|
||||
|
||||
00000000000000A8 62fdff286f1e VMOVRSW ymm3, ymmword ptr [r22]
|
||||
DSIZE: 64, ASIZE: 64, VLEN: 256
|
||||
ISA Set: MOVRS, Ins cat: DATAXFER, CET tracked: no
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 31
|
||||
EVEX Tuple Type: Full Mem
|
||||
Exception class: EVEX, exception type: E4
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 3, RegCount: 1
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M,
|
||||
Segment: 3, Base: 22,
|
||||
|
||||
00000000000000AE 62fdff486f1e VMOVRSW zmm3, zmmword ptr [r22]
|
||||
DSIZE: 64, ASIZE: 64, VLEN: 512
|
||||
ISA Set: MOVRS, Ins cat: DATAXFER, CET tracked: no
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 31
|
||||
EVEX Tuple Type: Full Mem
|
||||
Exception class: EVEX, exception type: E4
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 3, RegCount: 1
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 0, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M,
|
||||
Segment: 3, Base: 22,
|
||||
|
||||
00000000000000B4 62fdff0f6f1e VMOVRSW xmm3{k7}, xmmword ptr [r22]
|
||||
DSIZE: 64, ASIZE: 64, VLEN: 128
|
||||
ISA Set: MOVRS, Ins cat: DATAXFER, CET tracked: no
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 31
|
||||
EVEX Tuple Type: Full Mem
|
||||
Exception class: EVEX, exception type: E4
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 3, RegCount: 1
|
||||
Decorator: Mask k7
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 7, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M,
|
||||
Segment: 3, Base: 22,
|
||||
|
||||
00000000000000BA 62fdff2f6f1e VMOVRSW ymm3{k7}, ymmword ptr [r22]
|
||||
DSIZE: 64, ASIZE: 64, VLEN: 256
|
||||
ISA Set: MOVRS, Ins cat: DATAXFER, CET tracked: no
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 31
|
||||
EVEX Tuple Type: Full Mem
|
||||
Exception class: EVEX, exception type: E4
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 3, RegCount: 1
|
||||
Decorator: Mask k7
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 7, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M,
|
||||
Segment: 3, Base: 22,
|
||||
|
||||
00000000000000C0 62fdff4f6f1e VMOVRSW zmm3{k7}, zmmword ptr [r22]
|
||||
DSIZE: 64, ASIZE: 64, VLEN: 512
|
||||
ISA Set: MOVRS, Ins cat: DATAXFER, CET tracked: no
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 31
|
||||
EVEX Tuple Type: Full Mem
|
||||
Exception class: EVEX, exception type: E4
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 3, RegCount: 1
|
||||
Decorator: Mask k7
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 7, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M,
|
||||
Segment: 3, Base: 22,
|
||||
|
||||
00000000000000C6 62fdff8f6f1e VMOVRSW xmm3{k7}{z}, xmmword ptr [r22]
|
||||
DSIZE: 64, ASIZE: 64, VLEN: 128
|
||||
ISA Set: MOVRS, Ins cat: DATAXFER, CET tracked: no
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 31
|
||||
EVEX Tuple Type: Full Mem
|
||||
Exception class: EVEX, exception type: E4
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 3, RegCount: 1
|
||||
Decorator: Mask k7
|
||||
Decorator: Zero (no merging)
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 7, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M,
|
||||
Segment: 3, Base: 22,
|
||||
|
||||
00000000000000CC 62fdffaf6f1e VMOVRSW ymm3{k7}{z}, ymmword ptr [r22]
|
||||
DSIZE: 64, ASIZE: 64, VLEN: 256
|
||||
ISA Set: MOVRS, Ins cat: DATAXFER, CET tracked: no
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 31
|
||||
EVEX Tuple Type: Full Mem
|
||||
Exception class: EVEX, exception type: E4
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 3, RegCount: 1
|
||||
Decorator: Mask k7
|
||||
Decorator: Zero (no merging)
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 7, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M,
|
||||
Segment: 3, Base: 22,
|
||||
|
||||
00000000000000D2 62fdffcf6f1e VMOVRSW zmm3{k7}{z}, zmmword ptr [r22]
|
||||
DSIZE: 64, ASIZE: 64, VLEN: 512
|
||||
ISA Set: MOVRS, Ins cat: DATAXFER, CET tracked: no
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 31
|
||||
EVEX Tuple Type: Full Mem
|
||||
Exception class: EVEX, exception type: E4
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 3, RegCount: 1
|
||||
Decorator: Mask k7
|
||||
Decorator: Zero (no merging)
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: A, RegType: Mask, RegSize: 8, RegId: 7, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M,
|
||||
Segment: 3, Base: 22,
|
||||
|
||||
1
bddisasm_test/x86/movrs/vmovrs_64.test
Normal file
1
bddisasm_test/x86/movrs/vmovrs_64.test
Normal file
@ -0,0 +1 @@
|
||||
býo bý(o býHo býo bý/o býOo bý<C3BD>o bý¯o býÏo bý~o bý~(o bý~Ho bý~o bý~/o bý~Oo bý~<7E>o bý~¯o bý~Ïo býþo býþ(o býþHo býþo býþ/o býþOo býþ<C3BD>o býþ¯o býþÏo býÿo býÿ(o býÿHo býÿo býÿ/o býÿOo býÿ<C3BD>o býÿ¯o býÿÏo
|
||||
@ -1,5 +1,16 @@
|
||||
bits 64
|
||||
|
||||
db 0xF2, 0x0F, 0x01, 0xC6 ; RDMSRLIST
|
||||
db 0xF3, 0x0F, 0x01, 0xC6 ; WRMSRLIST
|
||||
db 0x0F, 0x01, 0xC6 ; WRMSRNS
|
||||
; RDMSR rax, 0xbdbdbdbd
|
||||
db 0xc4, 0xe7, 0x7b, 0xf6, 0xc0, 0xbd, 0xbd, 0xbd, 0xbd
|
||||
; RDMSR rax, 0xbdbdbdbd
|
||||
db 0x62, 0xf7, 0x7f, 0x08, 0xf6, 0xc0, 0xbd, 0xbd, 0xbd, 0xbd
|
||||
; RDMSRLIST
|
||||
db 0xF2, 0x0F, 0x01, 0xC6
|
||||
; WRMSRNS
|
||||
db 0x0F, 0x01, 0xC6
|
||||
; WRMSRNS 0xbdbdbdbd, rax
|
||||
db 0xc4, 0xe7, 0x7a, 0xf6, 0xc0, 0xbd, 0xbd, 0xbd, 0xbd
|
||||
; WRMSRNS 0xbdbdbdbd, rax
|
||||
db 0x62, 0xf7, 0x7e, 0x08, 0xf6, 0xc0, 0xbd, 0xbd, 0xbd, 0xbd
|
||||
; WRMSRLIST
|
||||
db 0xF3, 0x0F, 0x01, 0xC6
|
||||
|
||||
@ -1,4 +1,39 @@
|
||||
0000000000000000 f20f01c6 RDMSRLIST
|
||||
0000000000000000 c4e77bf6c0bdbdbdbd RDMSR rax, 0xbdbdbdbd
|
||||
DSIZE: 32, ASIZE: 64, VLEN: -
|
||||
ISA Set: MSR_IMM, Ins cat: SYSTEM, CET tracked: no
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: ecx, bit: 5
|
||||
Valid modes
|
||||
R0: yes, R1: no, R2: no, R3: no
|
||||
Real: no, V8086: no, Prot: no, Compat: no, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: no, SGX off: yes, TSX on: yes, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1
|
||||
Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I
|
||||
Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: E, RegType: Model Specific, RegSize: 8, RegId: 0xffffffff, RegCount: 1
|
||||
|
||||
0000000000000009 62f77f08f6c0bdbdbdbd RDMSR rax, 0xbdbdbdbd
|
||||
DSIZE: 32, ASIZE: 64, VLEN: -
|
||||
ISA Set: MSR_IMM, Ins cat: SYSTEM, CET tracked: no
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: ecx, bit: 5
|
||||
EVEX Tuple Type: None
|
||||
Valid modes
|
||||
R0: yes, R1: no, R2: no, R3: no
|
||||
Real: no, V8086: no, Prot: no, Compat: no, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: no, SGX off: yes, TSX on: yes, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1
|
||||
Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I
|
||||
Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: E, RegType: Model Specific, RegSize: 8, RegId: 0xffffffff, RegCount: 1
|
||||
|
||||
0000000000000013 f20f01c6 RDMSRLIST
|
||||
DSIZE: 32, ASIZE: 64, VLEN: -
|
||||
ISA Set: MSRLIST, Ins cat: SYSTEM, CET tracked: no
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 27
|
||||
@ -17,7 +52,60 @@
|
||||
Base: 7,
|
||||
Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1
|
||||
|
||||
0000000000000004 f30f01c6 WRMSRLIST
|
||||
0000000000000017 0f01c6 WRMSRNS
|
||||
DSIZE: 32, ASIZE: 64, VLEN: -
|
||||
ISA Set: WRMSRNS, Ins cat: SYSTEM, CET tracked: no
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 19
|
||||
Valid modes
|
||||
R0: yes, R1: no, R2: no, R3: no
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: no, SGX off: yes, TSX on: yes, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1
|
||||
Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: E, RegType: Model Specific, RegSize: 8, RegId: 0xffffffff, RegCount: 1
|
||||
|
||||
000000000000001A c4e77af6c0bdbdbdbd WRMSRNS 0xbdbdbdbd, rax
|
||||
DSIZE: 32, ASIZE: 64, VLEN: -
|
||||
ISA Set: MSR_IMM, Ins cat: SYSTEM, CET tracked: no
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: ecx, bit: 5
|
||||
Valid modes
|
||||
R0: yes, R1: no, R2: no, R3: no
|
||||
Real: no, V8086: no, Prot: no, Compat: no, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: no, SGX off: yes, TSX on: yes, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1
|
||||
Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: E, RegType: Model Specific, RegSize: 8, RegId: 0xffffffff, RegCount: 1
|
||||
|
||||
0000000000000023 62f77e08f6c0bdbdbdbd WRMSRNS 0xbdbdbdbd, rax
|
||||
DSIZE: 32, ASIZE: 64, VLEN: -
|
||||
ISA Set: MSR_IMM, Ins cat: SYSTEM, CET tracked: no
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: ecx, bit: 5
|
||||
EVEX Tuple Type: None
|
||||
Valid modes
|
||||
R0: yes, R1: no, R2: no, R3: no
|
||||
Real: no, V8086: no, Prot: no, Compat: no, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: no, SGX off: yes, TSX on: yes, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1
|
||||
Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: E, RegType: Model Specific, RegSize: 8, RegId: 0xffffffff, RegCount: 1
|
||||
|
||||
000000000000002D f30f01c6 WRMSRLIST
|
||||
DSIZE: 32, ASIZE: 64, VLEN: -
|
||||
ISA Set: MSRLIST, Ins cat: SYSTEM, CET tracked: no
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 27
|
||||
@ -36,21 +124,3 @@
|
||||
Base: 7,
|
||||
Operand: 2, Acc: RW, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1
|
||||
|
||||
0000000000000008 0f01c6 WRMSRNS
|
||||
DSIZE: 32, ASIZE: 64, VLEN: -
|
||||
ISA Set: WRMSRNS, Ins cat: SYSTEM, CET tracked: no
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 19
|
||||
Valid modes
|
||||
R0: yes, R1: no, R2: no, R3: no
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: no, SGX off: yes, TSX on: yes, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 0, RegCount: 1
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 2, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Register, Size: 4, RawSize: 4, Encoding: S, RegType: General Purpose, RegSize: 4, RegId: 1, RegCount: 1
|
||||
Operand: 3, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: E, RegType: Model Specific, RegSize: 8, RegId: 0xffffffff, RegCount: 1
|
||||
|
||||
|
||||
@ -1 +1 @@
|
||||
<EFBFBD><EFBFBD><EFBFBD><01><01>
|
||||
<EFBFBD><EFBFBD>{<7B><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>b<EFBFBD><08><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><01><EFBFBD><EFBFBD><EFBFBD>z<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>b<EFBFBD>~<08><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><01>
|
||||
@ -2,6 +2,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: SSE, Ins cat: CONVERT, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: edx, bit: 25
|
||||
SIMD Exceptions: IP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -18,6 +19,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: SSE2, Ins cat: CONVERT, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: edx, bit: 26
|
||||
SIMD Exceptions: IP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -34,6 +36,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: SSE, Ins cat: CONVERT, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: edx, bit: 25
|
||||
SIMD Exceptions: IP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -50,6 +53,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: SSE2, Ins cat: CONVERT, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: edx, bit: 26
|
||||
SIMD Exceptions: IP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -1132,6 +1136,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: SSE, Ins cat: CONVERT, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: edx, bit: 25
|
||||
SIMD Exceptions: IP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -1148,6 +1153,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: SSE2, Ins cat: CONVERT, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: edx, bit: 26
|
||||
SIMD Exceptions: IP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -1164,6 +1170,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: SSE, Ins cat: CONVERT, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: edx, bit: 25
|
||||
SIMD Exceptions: IP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -1180,6 +1187,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: SSE2, Ins cat: CONVERT, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: edx, bit: 26
|
||||
SIMD Exceptions: IP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
|
||||
@ -211,6 +211,7 @@
|
||||
ISA Set: SSE2, Ins cat: CONVERT, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: edx, bit: 26
|
||||
Exception class: SSE/VEX, exception type: 3
|
||||
SIMD Exceptions: P
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -228,6 +229,7 @@
|
||||
ISA Set: SSE2, Ins cat: CONVERT, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: edx, bit: 26
|
||||
Exception class: SSE/VEX, exception type: 3
|
||||
SIMD Exceptions: P
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -263,6 +265,7 @@
|
||||
ISA Set: SSE2, Ins cat: CONVERT, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: edx, bit: 26
|
||||
Exception class: SSE/VEX, exception type: 3
|
||||
SIMD Exceptions: IP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -280,6 +283,7 @@
|
||||
ISA Set: SSE2, Ins cat: CONVERT, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: edx, bit: 26
|
||||
Exception class: SSE/VEX, exception type: 3
|
||||
SIMD Exceptions: IP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -297,6 +301,7 @@
|
||||
ISA Set: SSE2, Ins cat: CONVERT, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: edx, bit: 26
|
||||
Exception class: SSE/VEX, exception type: 3
|
||||
SIMD Exceptions: IP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -314,6 +319,7 @@
|
||||
ISA Set: SSE2, Ins cat: CONVERT, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: edx, bit: 26
|
||||
Exception class: SSE/VEX, exception type: 3
|
||||
SIMD Exceptions: IP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -331,6 +337,7 @@
|
||||
ISA Set: SSE2, Ins cat: SSE2, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: edx, bit: 26
|
||||
Exception class: SSE/VEX, exception type: 3
|
||||
SIMD Exceptions: ID
|
||||
FLAGS access
|
||||
CF: m, PF: m, ZF: m,
|
||||
Valid modes
|
||||
@ -351,6 +358,7 @@
|
||||
ISA Set: SSE2, Ins cat: SSE2, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: edx, bit: 26
|
||||
Exception class: SSE/VEX, exception type: 3
|
||||
SIMD Exceptions: ID
|
||||
FLAGS access
|
||||
CF: m, PF: m, ZF: m,
|
||||
Valid modes
|
||||
@ -388,6 +396,7 @@
|
||||
ISA Set: SSE2, Ins cat: SSE, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: edx, bit: 26
|
||||
Exception class: SSE/VEX, exception type: 2
|
||||
SIMD Exceptions: IDP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -405,6 +414,7 @@
|
||||
ISA Set: SSE2, Ins cat: SSE, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: edx, bit: 26
|
||||
Exception class: SSE/VEX, exception type: 3
|
||||
SIMD Exceptions: IDP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -490,6 +500,7 @@
|
||||
ISA Set: SSE2, Ins cat: SSE, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: edx, bit: 26
|
||||
Exception class: SSE/VEX, exception type: 2
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -507,6 +518,7 @@
|
||||
ISA Set: SSE2, Ins cat: SSE, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: edx, bit: 26
|
||||
Exception class: SSE/VEX, exception type: 3
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -524,6 +536,7 @@
|
||||
ISA Set: SSE2, Ins cat: SSE, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: edx, bit: 26
|
||||
Exception class: SSE/VEX, exception type: 2
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -541,6 +554,7 @@
|
||||
ISA Set: SSE2, Ins cat: SSE, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: edx, bit: 26
|
||||
Exception class: SSE/VEX, exception type: 3
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -558,6 +572,7 @@
|
||||
ISA Set: SSE2, Ins cat: CONVERT, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: edx, bit: 26
|
||||
Exception class: SSE/VEX, exception type: 3
|
||||
SIMD Exceptions: ID
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -575,6 +590,7 @@
|
||||
ISA Set: SSE2, Ins cat: CONVERT, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: edx, bit: 26
|
||||
Exception class: SSE/VEX, exception type: 2
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -592,6 +608,7 @@
|
||||
ISA Set: SSE2, Ins cat: CONVERT, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: edx, bit: 26
|
||||
Exception class: SSE/VEX, exception type: 3
|
||||
SIMD Exceptions: ID
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -609,6 +626,7 @@
|
||||
ISA Set: SSE2, Ins cat: CONVERT, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: edx, bit: 26
|
||||
Exception class: SSE/VEX, exception type: 3
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -626,6 +644,7 @@
|
||||
ISA Set: SSE2, Ins cat: CONVERT, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: edx, bit: 26
|
||||
Exception class: SSE/VEX, exception type: 2
|
||||
SIMD Exceptions: P
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -643,6 +662,7 @@
|
||||
ISA Set: SSE2, Ins cat: CONVERT, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: edx, bit: 26
|
||||
Exception class: SSE/VEX, exception type: 2
|
||||
SIMD Exceptions: IP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -660,6 +680,7 @@
|
||||
ISA Set: SSE2, Ins cat: CONVERT, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: edx, bit: 26
|
||||
Exception class: SSE/VEX, exception type: 2
|
||||
SIMD Exceptions: IP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -677,6 +698,7 @@
|
||||
ISA Set: SSE2, Ins cat: SSE, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: edx, bit: 26
|
||||
Exception class: SSE/VEX, exception type: 2
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -694,6 +716,7 @@
|
||||
ISA Set: SSE2, Ins cat: SSE, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: edx, bit: 26
|
||||
Exception class: SSE/VEX, exception type: 3
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -711,6 +734,7 @@
|
||||
ISA Set: SSE2, Ins cat: SSE, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: edx, bit: 26
|
||||
Exception class: SSE/VEX, exception type: 2
|
||||
SIMD Exceptions: ID
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -728,6 +752,7 @@
|
||||
ISA Set: SSE2, Ins cat: SSE, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: edx, bit: 26
|
||||
Exception class: SSE/VEX, exception type: 3
|
||||
SIMD Exceptions: ID
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -745,6 +770,7 @@
|
||||
ISA Set: SSE2, Ins cat: SSE, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: edx, bit: 26
|
||||
Exception class: SSE/VEX, exception type: 2
|
||||
SIMD Exceptions: IDZOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -762,6 +788,7 @@
|
||||
ISA Set: SSE2, Ins cat: SSE, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: edx, bit: 26
|
||||
Exception class: SSE/VEX, exception type: 3
|
||||
SIMD Exceptions: IDZOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -779,6 +806,7 @@
|
||||
ISA Set: SSE2, Ins cat: SSE, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: edx, bit: 26
|
||||
Exception class: SSE/VEX, exception type: 2
|
||||
SIMD Exceptions: ID
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -796,6 +824,7 @@
|
||||
ISA Set: SSE2, Ins cat: SSE, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: edx, bit: 26
|
||||
Exception class: SSE/VEX, exception type: 3
|
||||
SIMD Exceptions: ID
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -1479,6 +1508,7 @@
|
||||
ISA Set: SSE2, Ins cat: SSE, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: edx, bit: 26
|
||||
Exception class: SSE/VEX, exception type: 2
|
||||
SIMD Exceptions: ID
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -1497,6 +1527,7 @@
|
||||
ISA Set: SSE2, Ins cat: SSE, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: edx, bit: 26
|
||||
Exception class: SSE/VEX, exception type: 3
|
||||
SIMD Exceptions: ID
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -1996,6 +2027,7 @@
|
||||
ISA Set: SSE2, Ins cat: CONVERT, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: edx, bit: 26
|
||||
Exception class: SSE/VEX, exception type: 2
|
||||
SIMD Exceptions: IP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -2030,6 +2062,7 @@
|
||||
ISA Set: SSE2, Ins cat: CONVERT, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: edx, bit: 26
|
||||
Exception class: SSE/VEX, exception type: 2
|
||||
SIMD Exceptions: IP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -2657,6 +2690,7 @@
|
||||
ISA Set: SSE2, Ins cat: CONVERT, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: edx, bit: 26
|
||||
Exception class: SSE/VEX, exception type: 3
|
||||
SIMD Exceptions: P
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -2674,6 +2708,7 @@
|
||||
ISA Set: SSE2, Ins cat: CONVERT, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: edx, bit: 26
|
||||
Exception class: SSE/VEX, exception type: 3
|
||||
SIMD Exceptions: P
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -2709,6 +2744,7 @@
|
||||
ISA Set: SSE2, Ins cat: CONVERT, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: edx, bit: 26
|
||||
Exception class: SSE/VEX, exception type: 3
|
||||
SIMD Exceptions: IP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -2727,6 +2763,7 @@
|
||||
ISA Set: SSE2, Ins cat: CONVERT, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: edx, bit: 26
|
||||
Exception class: SSE/VEX, exception type: 3
|
||||
SIMD Exceptions: IP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -2745,6 +2782,7 @@
|
||||
ISA Set: SSE2, Ins cat: CONVERT, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: edx, bit: 26
|
||||
Exception class: SSE/VEX, exception type: 3
|
||||
SIMD Exceptions: IP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -2763,6 +2801,7 @@
|
||||
ISA Set: SSE2, Ins cat: CONVERT, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: edx, bit: 26
|
||||
Exception class: SSE/VEX, exception type: 3
|
||||
SIMD Exceptions: IP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -2781,6 +2820,7 @@
|
||||
ISA Set: SSE2, Ins cat: SSE2, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: edx, bit: 26
|
||||
Exception class: SSE/VEX, exception type: 3
|
||||
SIMD Exceptions: ID
|
||||
FLAGS access
|
||||
CF: m, PF: m, ZF: m,
|
||||
Valid modes
|
||||
@ -2802,6 +2842,7 @@
|
||||
ISA Set: SSE2, Ins cat: SSE2, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: edx, bit: 26
|
||||
Exception class: SSE/VEX, exception type: 3
|
||||
SIMD Exceptions: ID
|
||||
FLAGS access
|
||||
CF: m, PF: m, ZF: m,
|
||||
Valid modes
|
||||
@ -2840,6 +2881,7 @@
|
||||
ISA Set: SSE2, Ins cat: SSE, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: edx, bit: 26
|
||||
Exception class: SSE/VEX, exception type: 2
|
||||
SIMD Exceptions: IDP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -2858,6 +2900,7 @@
|
||||
ISA Set: SSE2, Ins cat: SSE, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: edx, bit: 26
|
||||
Exception class: SSE/VEX, exception type: 3
|
||||
SIMD Exceptions: IDP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -2948,6 +2991,7 @@
|
||||
ISA Set: SSE2, Ins cat: SSE, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: edx, bit: 26
|
||||
Exception class: SSE/VEX, exception type: 2
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -2966,6 +3010,7 @@
|
||||
ISA Set: SSE2, Ins cat: SSE, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: edx, bit: 26
|
||||
Exception class: SSE/VEX, exception type: 3
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -2984,6 +3029,7 @@
|
||||
ISA Set: SSE2, Ins cat: SSE, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: edx, bit: 26
|
||||
Exception class: SSE/VEX, exception type: 2
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -3002,6 +3048,7 @@
|
||||
ISA Set: SSE2, Ins cat: SSE, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: edx, bit: 26
|
||||
Exception class: SSE/VEX, exception type: 3
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -3020,6 +3067,7 @@
|
||||
ISA Set: SSE2, Ins cat: CONVERT, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: edx, bit: 26
|
||||
Exception class: SSE/VEX, exception type: 3
|
||||
SIMD Exceptions: ID
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -3038,6 +3086,7 @@
|
||||
ISA Set: SSE2, Ins cat: CONVERT, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: edx, bit: 26
|
||||
Exception class: SSE/VEX, exception type: 2
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -3056,6 +3105,7 @@
|
||||
ISA Set: SSE2, Ins cat: CONVERT, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: edx, bit: 26
|
||||
Exception class: SSE/VEX, exception type: 3
|
||||
SIMD Exceptions: ID
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -3074,6 +3124,7 @@
|
||||
ISA Set: SSE2, Ins cat: CONVERT, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: edx, bit: 26
|
||||
Exception class: SSE/VEX, exception type: 3
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -3092,6 +3143,7 @@
|
||||
ISA Set: SSE2, Ins cat: CONVERT, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: edx, bit: 26
|
||||
Exception class: SSE/VEX, exception type: 2
|
||||
SIMD Exceptions: P
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -3110,6 +3162,7 @@
|
||||
ISA Set: SSE2, Ins cat: CONVERT, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: edx, bit: 26
|
||||
Exception class: SSE/VEX, exception type: 2
|
||||
SIMD Exceptions: IP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -3128,6 +3181,7 @@
|
||||
ISA Set: SSE2, Ins cat: CONVERT, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: edx, bit: 26
|
||||
Exception class: SSE/VEX, exception type: 2
|
||||
SIMD Exceptions: IP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -3146,6 +3200,7 @@
|
||||
ISA Set: SSE2, Ins cat: SSE, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: edx, bit: 26
|
||||
Exception class: SSE/VEX, exception type: 2
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -3164,6 +3219,7 @@
|
||||
ISA Set: SSE2, Ins cat: SSE, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: edx, bit: 26
|
||||
Exception class: SSE/VEX, exception type: 3
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -3182,6 +3238,7 @@
|
||||
ISA Set: SSE2, Ins cat: SSE, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: edx, bit: 26
|
||||
Exception class: SSE/VEX, exception type: 2
|
||||
SIMD Exceptions: ID
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -3200,6 +3257,7 @@
|
||||
ISA Set: SSE2, Ins cat: SSE, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: edx, bit: 26
|
||||
Exception class: SSE/VEX, exception type: 3
|
||||
SIMD Exceptions: ID
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -3218,6 +3276,7 @@
|
||||
ISA Set: SSE2, Ins cat: SSE, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: edx, bit: 26
|
||||
Exception class: SSE/VEX, exception type: 2
|
||||
SIMD Exceptions: IDZOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -3236,6 +3295,7 @@
|
||||
ISA Set: SSE2, Ins cat: SSE, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: edx, bit: 26
|
||||
Exception class: SSE/VEX, exception type: 3
|
||||
SIMD Exceptions: IDZOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -3254,6 +3314,7 @@
|
||||
ISA Set: SSE2, Ins cat: SSE, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: edx, bit: 26
|
||||
Exception class: SSE/VEX, exception type: 2
|
||||
SIMD Exceptions: ID
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -3272,6 +3333,7 @@
|
||||
ISA Set: SSE2, Ins cat: SSE, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: edx, bit: 26
|
||||
Exception class: SSE/VEX, exception type: 3
|
||||
SIMD Exceptions: ID
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -3981,6 +4043,7 @@
|
||||
ISA Set: SSE2, Ins cat: SSE, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: edx, bit: 26
|
||||
Exception class: SSE/VEX, exception type: 2
|
||||
SIMD Exceptions: ID
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -4000,6 +4063,7 @@
|
||||
ISA Set: SSE2, Ins cat: SSE, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: edx, bit: 26
|
||||
Exception class: SSE/VEX, exception type: 3
|
||||
SIMD Exceptions: ID
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -4521,6 +4585,7 @@
|
||||
ISA Set: SSE2, Ins cat: CONVERT, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: edx, bit: 26
|
||||
Exception class: SSE/VEX, exception type: 2
|
||||
SIMD Exceptions: IP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -4557,6 +4622,7 @@
|
||||
ISA Set: SSE2, Ins cat: CONVERT, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: edx, bit: 26
|
||||
Exception class: SSE/VEX, exception type: 2
|
||||
SIMD Exceptions: IP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
|
||||
@ -54,6 +54,7 @@
|
||||
ISA Set: SSE3, Ins cat: SSE, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: ecx, bit: 0
|
||||
Exception class: SSE/VEX, exception type: 2
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -71,6 +72,7 @@
|
||||
ISA Set: SSE3, Ins cat: SSE, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: ecx, bit: 0
|
||||
Exception class: SSE/VEX, exception type: 2
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -88,6 +90,7 @@
|
||||
ISA Set: SSE3, Ins cat: SSE, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: ecx, bit: 0
|
||||
Exception class: SSE/VEX, exception type: 2
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -105,6 +108,7 @@
|
||||
ISA Set: SSE3, Ins cat: SSE, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: ecx, bit: 0
|
||||
Exception class: SSE/VEX, exception type: 2
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -122,6 +126,7 @@
|
||||
ISA Set: SSE3, Ins cat: SSE, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: ecx, bit: 0
|
||||
Exception class: SSE/VEX, exception type: 2
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -139,6 +144,7 @@
|
||||
ISA Set: SSE3, Ins cat: SSE, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: ecx, bit: 0
|
||||
Exception class: SSE/VEX, exception type: 2
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -501,6 +507,7 @@
|
||||
ISA Set: SSE3, Ins cat: SSE, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: ecx, bit: 0
|
||||
Exception class: SSE/VEX, exception type: 2
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -519,6 +526,7 @@
|
||||
ISA Set: SSE3, Ins cat: SSE, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: ecx, bit: 0
|
||||
Exception class: SSE/VEX, exception type: 2
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -537,6 +545,7 @@
|
||||
ISA Set: SSE3, Ins cat: SSE, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: ecx, bit: 0
|
||||
Exception class: SSE/VEX, exception type: 2
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -555,6 +564,7 @@
|
||||
ISA Set: SSE3, Ins cat: SSE, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: ecx, bit: 0
|
||||
Exception class: SSE/VEX, exception type: 2
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -573,6 +583,7 @@
|
||||
ISA Set: SSE3, Ins cat: SSE, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: ecx, bit: 0
|
||||
Exception class: SSE/VEX, exception type: 2
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -591,6 +602,7 @@
|
||||
ISA Set: SSE3, Ins cat: SSE, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: ecx, bit: 0
|
||||
Exception class: SSE/VEX, exception type: 2
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
|
||||
@ -638,6 +638,7 @@
|
||||
ISA Set: SSE4, Ins cat: SSE, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: ecx, bit: 19
|
||||
Exception class: SSE/VEX, exception type: 2
|
||||
SIMD Exceptions: IP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -656,6 +657,7 @@
|
||||
ISA Set: SSE4, Ins cat: SSE, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: ecx, bit: 19
|
||||
Exception class: SSE/VEX, exception type: 2
|
||||
SIMD Exceptions: IP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -674,6 +676,7 @@
|
||||
ISA Set: SSE4, Ins cat: SSE, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: ecx, bit: 19
|
||||
Exception class: SSE/VEX, exception type: 3
|
||||
SIMD Exceptions: IP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -692,6 +695,7 @@
|
||||
ISA Set: SSE4, Ins cat: SSE, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: ecx, bit: 19
|
||||
Exception class: SSE/VEX, exception type: 3
|
||||
SIMD Exceptions: IP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -1002,6 +1006,7 @@
|
||||
ISA Set: SSE4, Ins cat: SSE, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: ecx, bit: 19
|
||||
Exception class: SSE/VEX, exception type: 2
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -1020,6 +1025,7 @@
|
||||
ISA Set: SSE4, Ins cat: SSE, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: ecx, bit: 19
|
||||
Exception class: SSE/VEX, exception type: 2
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -1813,6 +1819,7 @@
|
||||
ISA Set: SSE4, Ins cat: SSE, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: ecx, bit: 19
|
||||
Exception class: SSE/VEX, exception type: 2
|
||||
SIMD Exceptions: IP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -1832,6 +1839,7 @@
|
||||
ISA Set: SSE4, Ins cat: SSE, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: ecx, bit: 19
|
||||
Exception class: SSE/VEX, exception type: 2
|
||||
SIMD Exceptions: IP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -1851,6 +1859,7 @@
|
||||
ISA Set: SSE4, Ins cat: SSE, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: ecx, bit: 19
|
||||
Exception class: SSE/VEX, exception type: 3
|
||||
SIMD Exceptions: IP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -1870,6 +1879,7 @@
|
||||
ISA Set: SSE4, Ins cat: SSE, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: ecx, bit: 19
|
||||
Exception class: SSE/VEX, exception type: 3
|
||||
SIMD Exceptions: IP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -2184,6 +2194,7 @@
|
||||
ISA Set: SSE4, Ins cat: SSE, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: ecx, bit: 19
|
||||
Exception class: SSE/VEX, exception type: 2
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
@ -2203,6 +2214,7 @@
|
||||
ISA Set: SSE4, Ins cat: SSE, CET tracked: no
|
||||
CPUID leaf: 0x00000001, reg: ecx, bit: 19
|
||||
Exception class: SSE/VEX, exception type: 2
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: yes, V8086: yes, Prot: yes, Compat: yes, Long: yes
|
||||
|
||||
234
bddisasm_test/x86/sm/sm4_evex_64.result
Normal file
234
bddisasm_test/x86/sm/sm4_evex_64.result
Normal file
@ -0,0 +1,234 @@
|
||||
0000000000000000 62fa7e08da1e VSM4KEY4 xmm3, xmm0, xmmword ptr [r22]
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: SM4, Ins cat: SM4, CET tracked: no
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 2
|
||||
EVEX Tuple Type: Full Mem
|
||||
Exception class: EVEX, exception type: E6
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 3, RegCount: 1
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M,
|
||||
Segment: 3, Base: 22,
|
||||
|
||||
0000000000000006 62fa7e28da1e VSM4KEY4 ymm3, ymm0, ymmword ptr [r22]
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 256
|
||||
ISA Set: SM4, Ins cat: SM4, CET tracked: no
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 2
|
||||
EVEX Tuple Type: Full Mem
|
||||
Exception class: EVEX, exception type: E6
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 3, RegCount: 1
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 0, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M,
|
||||
Segment: 3, Base: 22,
|
||||
|
||||
000000000000000C 62fa7e48da1e VSM4KEY4 zmm3, zmm0, zmmword ptr [r22]
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 512
|
||||
ISA Set: SM4, Ins cat: SM4, CET tracked: no
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 2
|
||||
EVEX Tuple Type: Full Mem
|
||||
Exception class: EVEX, exception type: E6
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 3, RegCount: 1
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 0, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M,
|
||||
Segment: 3, Base: 22,
|
||||
|
||||
0000000000000012 62fa7e08dade VSM4KEY4 xmm3, xmm0, xmm6
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: SM4, Ins cat: SM4, CET tracked: no
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 2
|
||||
EVEX Tuple Type: Full Mem
|
||||
Exception class: EVEX, exception type: E6
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 3, RegCount: 1
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 6, RegCount: 1
|
||||
|
||||
0000000000000018 62fa7e28dade VSM4KEY4 ymm3, ymm0, ymm6
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 256
|
||||
ISA Set: SM4, Ins cat: SM4, CET tracked: no
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 2
|
||||
EVEX Tuple Type: Full Mem
|
||||
Exception class: EVEX, exception type: E6
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 3, RegCount: 1
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 0, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 6, RegCount: 1
|
||||
|
||||
000000000000001E 62fa7e48dade VSM4KEY4 zmm3, zmm0, zmm6
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 512
|
||||
ISA Set: SM4, Ins cat: SM4, CET tracked: no
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 2
|
||||
EVEX Tuple Type: Full Mem
|
||||
Exception class: EVEX, exception type: E6
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 3, RegCount: 1
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 0, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 6, RegCount: 1
|
||||
|
||||
0000000000000024 62fa7f08da1e VSM4RNDS4 xmm3, xmm0, xmmword ptr [r22]
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: SM4, Ins cat: SM4, CET tracked: no
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 2
|
||||
EVEX Tuple Type: Full Mem
|
||||
Exception class: EVEX, exception type: E6
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 3, RegCount: 1
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Memory, Size: 16, RawSize: 16, Encoding: M,
|
||||
Segment: 3, Base: 22,
|
||||
|
||||
000000000000002A 62fa7f28da1e VSM4RNDS4 ymm3, ymm0, ymmword ptr [r22]
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 256
|
||||
ISA Set: SM4, Ins cat: SM4, CET tracked: no
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 2
|
||||
EVEX Tuple Type: Full Mem
|
||||
Exception class: EVEX, exception type: E6
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 3, RegCount: 1
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 0, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Memory, Size: 32, RawSize: 32, Encoding: M,
|
||||
Segment: 3, Base: 22,
|
||||
|
||||
0000000000000030 62fa7f48da1e VSM4RNDS4 zmm3, zmm0, zmmword ptr [r22]
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 512
|
||||
ISA Set: SM4, Ins cat: SM4, CET tracked: no
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 2
|
||||
EVEX Tuple Type: Full Mem
|
||||
Exception class: EVEX, exception type: E6
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 3, RegCount: 1
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 0, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Memory, Size: 64, RawSize: 64, Encoding: M,
|
||||
Segment: 3, Base: 22,
|
||||
|
||||
0000000000000036 62fa7f08dade VSM4RNDS4 xmm3, xmm0, xmm6
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: SM4, Ins cat: SM4, CET tracked: no
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 2
|
||||
EVEX Tuple Type: Full Mem
|
||||
Exception class: EVEX, exception type: E6
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 16, RawSize: 16, Encoding: R, RegType: Vector, RegSize: 16, RegId: 3, RegCount: 1
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: V, RegType: Vector, RegSize: 16, RegId: 0, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Register, Size: 16, RawSize: 16, Encoding: M, RegType: Vector, RegSize: 16, RegId: 6, RegCount: 1
|
||||
|
||||
000000000000003C 62fa7f28dade VSM4RNDS4 ymm3, ymm0, ymm6
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 256
|
||||
ISA Set: SM4, Ins cat: SM4, CET tracked: no
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 2
|
||||
EVEX Tuple Type: Full Mem
|
||||
Exception class: EVEX, exception type: E6
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 32, RawSize: 32, Encoding: R, RegType: Vector, RegSize: 32, RegId: 3, RegCount: 1
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: V, RegType: Vector, RegSize: 32, RegId: 0, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Register, Size: 32, RawSize: 32, Encoding: M, RegType: Vector, RegSize: 32, RegId: 6, RegCount: 1
|
||||
|
||||
0000000000000042 62fa7f48dade VSM4RNDS4 zmm3, zmm0, zmm6
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 512
|
||||
ISA Set: SM4, Ins cat: SM4, CET tracked: no
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: eax, bit: 2
|
||||
EVEX Tuple Type: Full Mem
|
||||
Exception class: EVEX, exception type: E6
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 64, RawSize: 64, Encoding: R, RegType: Vector, RegSize: 64, RegId: 3, RegCount: 1
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: V, RegType: Vector, RegSize: 64, RegId: 0, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Register, Size: 64, RawSize: 64, Encoding: M, RegType: Vector, RegSize: 64, RegId: 6, RegCount: 1
|
||||
|
||||
1
bddisasm_test/x86/sm/sm4_evex_64.test
Normal file
1
bddisasm_test/x86/sm/sm4_evex_64.test
Normal file
@ -0,0 +1 @@
|
||||
bњ~к bњ~(к bњ~Hк bњ~коbњ~(коbњ~Hкоbњк bњ(к bњHк bњкоbњ(коbњHко
|
||||
@ -16,4 +16,6 @@
|
||||
db 0xc4, 0x62, 0x7f, 0xda, 0x01 ; VSM4RNDS4 ymm8, ymm0, ymmword ptr [rcx]
|
||||
|
||||
db 0xc4, 0x63, 0x79, 0xde, 0xc7, 0xef ; VSM3RNDS2 xmm8, xmm0, xmm7, 0xef
|
||||
db 0xc4, 0x63, 0x79, 0xde, 0x01, 0xef ; VSM3RNDS2 xmm8, xmm0, xmmword ptr [rcx], 0xef
|
||||
db 0xc4, 0x63, 0x79, 0xde, 0x01, 0xef ; VSM3RNDS2 xmm8, xmm0, xmmword ptr [rcx], 0xef
|
||||
|
||||
|
||||
@ -40,6 +40,7 @@
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16
|
||||
EVEX Tuple Type: Tuple 1 Scalar
|
||||
Exception class: EVEX, exception type: E10NF
|
||||
SIMD Exceptions: P
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -59,6 +60,7 @@
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16
|
||||
EVEX Tuple Type: Tuple 1 Scalar
|
||||
Exception class: EVEX, exception type: E10NF
|
||||
SIMD Exceptions: P
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -78,6 +80,7 @@
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16
|
||||
EVEX Tuple Type: Tuple 1 Fixes
|
||||
Exception class: EVEX, exception type: E3
|
||||
SIMD Exceptions: IP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -96,6 +99,7 @@
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16
|
||||
EVEX Tuple Type: Tuple 1 Fixes
|
||||
Exception class: EVEX, exception type: E3
|
||||
SIMD Exceptions: IP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
|
||||
@ -40,6 +40,7 @@
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16
|
||||
EVEX Tuple Type: Tuple 1 Scalar
|
||||
Exception class: EVEX, exception type: E10NF
|
||||
SIMD Exceptions: P
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -59,6 +60,7 @@
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16
|
||||
EVEX Tuple Type: Tuple 1 Scalar
|
||||
Exception class: EVEX, exception type: E3
|
||||
SIMD Exceptions: P
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -78,6 +80,7 @@
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16
|
||||
EVEX Tuple Type: Tuple 1 Fixes
|
||||
Exception class: EVEX, exception type: E3
|
||||
SIMD Exceptions: IP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
@ -96,6 +99,7 @@
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000000, reg: ebx, bit: 16
|
||||
EVEX Tuple Type: Tuple 1 Fixes
|
||||
Exception class: EVEX, exception type: E3
|
||||
SIMD Exceptions: IP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
|
||||
@ -160,6 +160,7 @@
|
||||
DSIZE: 32, ASIZE: 64, VLEN: 128
|
||||
ISA Set: FMA4, Ins cat: FMA4, CET tracked: no
|
||||
CPUID leaf: 0x80000001, reg: ecx, bit: 16
|
||||
SIMD Exceptions: IDOUP
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: yes, Compat: yes, Long: yes
|
||||
|
||||
@ -1,11 +1,14 @@
|
||||
bits 64
|
||||
|
||||
; UWRMSR 0x44332211, rax
|
||||
db 0xC4, 0xE7, 0x7A, 0xF8, 0xC0, 0x11, 0x22, 0x33, 0x44
|
||||
; URDMSR rax, 0x44332211
|
||||
db 0xC4, 0xE7, 0x7B, 0xF8, 0xC0, 0x11, 0x22, 0x33, 0x44
|
||||
; UWRMSR rcx, rax
|
||||
db 0xF3, 0x0F, 0x38, 0xF8, 0xC1
|
||||
; URDMSR rax, rcx
|
||||
db 0xF2, 0x0F, 0x38, 0xF8, 0xC1
|
||||
|
||||
; URDMSR rax, 0x44332211
|
||||
db 0xC4, 0xE7, 0x7B, 0xF8, 0xC0, 0x11, 0x22, 0x33, 0x44
|
||||
; URDMSR rax, 0xbdbdbdbd
|
||||
db 0x62, 0xf7, 0x7f, 0x08, 0xf8, 0xc0, 0xbd, 0xbd, 0xbd, 0xbd
|
||||
; UWRMSR rcx, rax
|
||||
db 0xF3, 0x0F, 0x38, 0xF8, 0xC1
|
||||
; UWRMSR 0x44332211, rax
|
||||
db 0xC4, 0xE7, 0x7A, 0xF8, 0xC0, 0x11, 0x22, 0x33, 0x44
|
||||
; UWRMSR 0xbdbdbdbd, rax
|
||||
db 0x62, 0xf7, 0x7e, 0x08, 0xf8, 0xc0, 0xbd, 0xbd, 0xbd, 0xbd
|
||||
@ -1,55 +1,4 @@
|
||||
0000000000000000 c4e77af8c011223344 UWRMSR 0x44332211, rax
|
||||
DSIZE: 32, ASIZE: 64, VLEN: -
|
||||
ISA Set: USER_MSR, Ins cat: USER_MSR, CET tracked: no
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 15
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: no, Compat: no, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1
|
||||
Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: E, RegType: Model Specific, RegSize: 8, RegId: 0xffffffff, RegCount: 1
|
||||
|
||||
0000000000000009 c4e77bf8c011223344 URDMSR rax, 0x44332211
|
||||
DSIZE: 32, ASIZE: 64, VLEN: -
|
||||
ISA Set: USER_MSR, Ins cat: USER_MSR, CET tracked: no
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 15
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: no, Compat: no, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1
|
||||
Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I
|
||||
Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: E, RegType: Model Specific, RegSize: 8, RegId: 0xffffffff, RegCount: 1
|
||||
|
||||
0000000000000012 f30f38f8c1 UWRMSR rax, rcx
|
||||
DSIZE: 32, ASIZE: 64, VLEN: -
|
||||
ISA Set: USER_MSR, Ins cat: USER_MSR, CET tracked: no
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 15
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: no, Compat: no, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1
|
||||
Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: E, RegType: Model Specific, RegSize: 8, RegId: 0xffffffff, RegCount: 1
|
||||
|
||||
0000000000000017 f20f38f8c1 URDMSR rcx, rax
|
||||
0000000000000000 f20f38f8c1 URDMSR rcx, rax
|
||||
DSIZE: 32, ASIZE: 64, VLEN: -
|
||||
ISA Set: USER_MSR, Ins cat: USER_MSR, CET tracked: no
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 15
|
||||
@ -66,3 +15,90 @@
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1
|
||||
Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: E, RegType: Model Specific, RegSize: 8, RegId: 0xffffffff, RegCount: 1
|
||||
|
||||
0000000000000005 c4e77bf8c011223344 URDMSR rax, 0x44332211
|
||||
DSIZE: 32, ASIZE: 64, VLEN: -
|
||||
ISA Set: USER_MSR, Ins cat: USER_MSR, CET tracked: no
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 15
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: no, Compat: no, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1
|
||||
Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I
|
||||
Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: E, RegType: Model Specific, RegSize: 8, RegId: 0xffffffff, RegCount: 1
|
||||
|
||||
000000000000000E 62f77f08f8c0bdbdbdbd URDMSR rax, 0xbdbdbdbd
|
||||
DSIZE: 32, ASIZE: 64, VLEN: -
|
||||
ISA Set: APX_F, Ins cat: USER_MSR, CET tracked: no
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21
|
||||
EVEX Tuple Type: None
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: no, Compat: no, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1
|
||||
Operand: 1, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I
|
||||
Operand: 2, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: E, RegType: Model Specific, RegSize: 8, RegId: 0xffffffff, RegCount: 1
|
||||
|
||||
0000000000000018 f30f38f8c1 UWRMSR rax, rcx
|
||||
DSIZE: 32, ASIZE: 64, VLEN: -
|
||||
ISA Set: USER_MSR, Ins cat: USER_MSR, CET tracked: no
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 15
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: no, Compat: no, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: R, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 1, RegCount: 1
|
||||
Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: E, RegType: Model Specific, RegSize: 8, RegId: 0xffffffff, RegCount: 1
|
||||
|
||||
000000000000001D c4e77af8c011223344 UWRMSR 0x44332211, rax
|
||||
DSIZE: 32, ASIZE: 64, VLEN: -
|
||||
ISA Set: USER_MSR, Ins cat: USER_MSR, CET tracked: no
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 15
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: no, Compat: no, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1
|
||||
Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: E, RegType: Model Specific, RegSize: 8, RegId: 0xffffffff, RegCount: 1
|
||||
|
||||
0000000000000026 62f77e08f8c0bdbdbdbd UWRMSR 0xbdbdbdbd, rax
|
||||
DSIZE: 32, ASIZE: 64, VLEN: -
|
||||
ISA Set: APX_F, Ins cat: USER_MSR, CET tracked: no
|
||||
CPUID leaf: 0x00000007, sub-leaf: 0x00000001, reg: edx, bit: 21
|
||||
EVEX Tuple Type: None
|
||||
Valid modes
|
||||
R0: yes, R1: yes, R2: yes, R3: yes
|
||||
Real: no, V8086: no, Prot: no, Compat: no, Long: yes
|
||||
SMM on: yes, SMM off: yes, SGX on: yes, SGX off: yes, TSX on: yes, TSX off: yes
|
||||
VMXRoot: yes, VMXNonRoot: yes, VMXRoot SEAM: yes, VMXNonRoot SEAM: yes, VMX off: yes
|
||||
Valid prefixes
|
||||
REP: no, REPcc: no, LOCK: no
|
||||
HLE: no, XACQUIRE only: no, XRELEASE only: no
|
||||
BND: no, BHINT: no, DNT: no
|
||||
Operand: 0, Acc: R-, Type: Immediate, Size: 4, RawSize: 4, Encoding: I
|
||||
Operand: 1, Acc: R-, Type: Register, Size: 8, RawSize: 8, Encoding: M, RegType: General Purpose, RegSize: 8, RegId: 0, RegCount: 1
|
||||
Operand: 2, Acc: -W, Type: Register, Size: 8, RawSize: 8, Encoding: E, RegType: Model Specific, RegSize: 8, RegId: 0xffffffff, RegCount: 1
|
||||
|
||||
|
||||
@ -1 +1 @@
|
||||
Δηzψΐ"3DΔη{ψΐ"3Dσ8ψΑς8ψΑ
|
||||
<EFBFBD>8<><38><EFBFBD><EFBFBD>{<7B><>"3Db<44><08><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>8<><38><EFBFBD><EFBFBD>z<EFBFBD><7A>"3Db<44>~<08><><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
||||
@ -12,7 +12,7 @@ from setuptools import find_packages, setup, Command, Extension, Distribution
|
||||
from codecs import open
|
||||
|
||||
VERSION = (0, 3, 0)
|
||||
LIBRARY_VERSION = (2, 2, 0)
|
||||
LIBRARY_VERSION = (2, 3, 0)
|
||||
DIR_INCLUDE = '../../inc'
|
||||
|
||||
here = os.path.abspath(os.path.dirname(__file__))
|
||||
|
||||
@ -3,7 +3,9 @@
|
||||
members = [
|
||||
"bddisasm-sys",
|
||||
"bddisasm",
|
||||
"bdshemu-sys",
|
||||
"bdshemu",
|
||||
]
|
||||
|
||||
[workspace.package]
|
||||
version = "0.5.0"
|
||||
version = "0.5.1"
|
||||
|
||||
@ -14,7 +14,8 @@ categories = ["api-bindings", "hardware-support"]
|
||||
keywords = ["disassembler", "decoder", "x86", "amd64", "x86_64"]
|
||||
|
||||
[dependencies]
|
||||
bddisasm-sys = { version = "0.5.0", path = "../bddisasm-sys" }
|
||||
bddisasm-sys = { version = "0.5.1", path = "../bddisasm-sys" }
|
||||
bitflags = "2.6.0"
|
||||
|
||||
[features]
|
||||
std = []
|
||||
|
||||
@ -18,7 +18,7 @@ Add `bddisasm` to your `Cargo.toml`:
|
||||
|
||||
```toml
|
||||
[dependencies]
|
||||
bddisasm = "0.5.0"
|
||||
bddisasm = "0.5.1"
|
||||
```
|
||||
|
||||
## Examples
|
||||
|
||||
@ -14,6 +14,7 @@ use crate::mnemonic::Mnemonic;
|
||||
use crate::operand;
|
||||
use crate::operand::{OpAccess, Operands, OperandsLookup};
|
||||
use crate::rflags::flags_raw;
|
||||
use crate::simd_exceptions::SimdExceptions;
|
||||
use crate::tuple::Tuple;
|
||||
|
||||
use core::convert::TryFrom;
|
||||
@ -312,10 +313,10 @@ impl DecodedInstruction {
|
||||
/// # Arguments
|
||||
///
|
||||
/// * `code` - An [`u8`] slice that holds the code to be decoded. Note that decoding is attempted only from offset
|
||||
/// 0 inside this code chunk.
|
||||
/// 0 inside this code chunk.
|
||||
/// * `mode` - The mode in which to decode the instruction.
|
||||
/// * `ip` - The instruction pointer value to use when formatting the decoded instruction. Does not affect the
|
||||
/// decoding process in any way. If not needed, use [decode](DecodedInstruction::decode) instead.
|
||||
/// decoding process in any way. If not needed, use [decode](DecodedInstruction::decode) instead.
|
||||
///
|
||||
/// # Errors
|
||||
///
|
||||
@ -1361,6 +1362,13 @@ impl DecodedInstruction {
|
||||
FpuFlags::from_raw(self.inner.FpuFlagsAccess).unwrap()
|
||||
}
|
||||
|
||||
/// SIMD Floating-Point Exceptions.
|
||||
#[inline]
|
||||
#[must_use]
|
||||
pub fn simd_exceptions(&self) -> SimdExceptions {
|
||||
SimdExceptions::from_raw(unsafe { self.inner.SimdExceptions.Raw })
|
||||
}
|
||||
|
||||
/// `EVEX` tuple type.
|
||||
///
|
||||
/// # Panics
|
||||
|
||||
@ -23,7 +23,7 @@ impl<'a> Decoder<'a> {
|
||||
/// * `code` - An [`u8`] slice that holds the code to be decoded.
|
||||
/// * `mode` - The mode in which to decode the instruction.
|
||||
/// * `ip` - The instruction pointer value to use when formatting the decoded instruction. Does not affect the
|
||||
/// decoding process in any way.
|
||||
/// decoding process in any way.
|
||||
#[must_use]
|
||||
pub fn new(code: &'a [u8], mode: DecodeMode, ip: u64) -> Self {
|
||||
Self {
|
||||
@ -39,7 +39,7 @@ impl<'a> Decoder<'a> {
|
||||
/// # Returns
|
||||
///
|
||||
/// * `Some(DecodeResult)` - if there are still undecoded bytes in the given code chunk. The decoding may have
|
||||
/// still failed. See `Remarks`.
|
||||
/// still failed. See `Remarks`.
|
||||
/// * `None` - if all the bytes in the given code chunk were decoded.
|
||||
///
|
||||
/// # Remarks
|
||||
|
||||
@ -52,10 +52,10 @@ pub struct FpuFlags {
|
||||
impl FpuFlags {
|
||||
pub(crate) fn from_raw(flags: ffi::ND_FPU_FLAGS) -> Result<Self, DecodeError> {
|
||||
Ok(Self {
|
||||
c0: FpuFlagsAccess::from_raw(flags.C0())?,
|
||||
c1: FpuFlagsAccess::from_raw(flags.C1())?,
|
||||
c2: FpuFlagsAccess::from_raw(flags.C2())?,
|
||||
c3: FpuFlagsAccess::from_raw(flags.C3())?,
|
||||
c0: FpuFlagsAccess::from_raw(unsafe { flags.__bindgen_anon_1.C0() })?,
|
||||
c1: FpuFlagsAccess::from_raw(unsafe { flags.__bindgen_anon_1.C1() })?,
|
||||
c2: FpuFlagsAccess::from_raw(unsafe { flags.__bindgen_anon_1.C2() })?,
|
||||
c3: FpuFlagsAccess::from_raw(unsafe { flags.__bindgen_anon_1.C3() })?,
|
||||
})
|
||||
}
|
||||
}
|
||||
|
||||
@ -15,11 +15,16 @@ pub enum IsaSet {
|
||||
ADX,
|
||||
AES,
|
||||
AMD,
|
||||
AMXAVX512,
|
||||
AMXBF16,
|
||||
AMXCOMPLEX,
|
||||
AMXFP16,
|
||||
AMXFP8,
|
||||
AMXINT8,
|
||||
AMXMOVRS,
|
||||
AMXTF32,
|
||||
AMXTILE,
|
||||
AMXTRANSPOSE,
|
||||
APX_F,
|
||||
AVX,
|
||||
AVX102,
|
||||
@ -86,8 +91,10 @@ pub enum IsaSet {
|
||||
MOVBE,
|
||||
MOVDIR64B,
|
||||
MOVDIRI,
|
||||
MOVRS,
|
||||
MPX,
|
||||
MSRLIST,
|
||||
MSR_IMM,
|
||||
MWAITT,
|
||||
PAUSE,
|
||||
PCLMULQDQ,
|
||||
@ -158,11 +165,16 @@ impl TryFrom<ffi::ND_INS_SET> for IsaSet {
|
||||
ffi::_ND_INS_SET::ND_SET_ADX => Ok(IsaSet::ADX),
|
||||
ffi::_ND_INS_SET::ND_SET_AES => Ok(IsaSet::AES),
|
||||
ffi::_ND_INS_SET::ND_SET_AMD => Ok(IsaSet::AMD),
|
||||
ffi::_ND_INS_SET::ND_SET_AMXAVX512 => Ok(IsaSet::AMXAVX512),
|
||||
ffi::_ND_INS_SET::ND_SET_AMXBF16 => Ok(IsaSet::AMXBF16),
|
||||
ffi::_ND_INS_SET::ND_SET_AMXCOMPLEX => Ok(IsaSet::AMXCOMPLEX),
|
||||
ffi::_ND_INS_SET::ND_SET_AMXFP16 => Ok(IsaSet::AMXFP16),
|
||||
ffi::_ND_INS_SET::ND_SET_AMXFP8 => Ok(IsaSet::AMXFP8),
|
||||
ffi::_ND_INS_SET::ND_SET_AMXINT8 => Ok(IsaSet::AMXINT8),
|
||||
ffi::_ND_INS_SET::ND_SET_AMXMOVRS => Ok(IsaSet::AMXMOVRS),
|
||||
ffi::_ND_INS_SET::ND_SET_AMXTF32 => Ok(IsaSet::AMXTF32),
|
||||
ffi::_ND_INS_SET::ND_SET_AMXTILE => Ok(IsaSet::AMXTILE),
|
||||
ffi::_ND_INS_SET::ND_SET_AMXTRANSPOSE => Ok(IsaSet::AMXTRANSPOSE),
|
||||
ffi::_ND_INS_SET::ND_SET_APX_F => Ok(IsaSet::APX_F),
|
||||
ffi::_ND_INS_SET::ND_SET_AVX => Ok(IsaSet::AVX),
|
||||
ffi::_ND_INS_SET::ND_SET_AVX102 => Ok(IsaSet::AVX102),
|
||||
@ -229,8 +241,10 @@ impl TryFrom<ffi::ND_INS_SET> for IsaSet {
|
||||
ffi::_ND_INS_SET::ND_SET_MOVBE => Ok(IsaSet::MOVBE),
|
||||
ffi::_ND_INS_SET::ND_SET_MOVDIR64B => Ok(IsaSet::MOVDIR64B),
|
||||
ffi::_ND_INS_SET::ND_SET_MOVDIRI => Ok(IsaSet::MOVDIRI),
|
||||
ffi::_ND_INS_SET::ND_SET_MOVRS => Ok(IsaSet::MOVRS),
|
||||
ffi::_ND_INS_SET::ND_SET_MPX => Ok(IsaSet::MPX),
|
||||
ffi::_ND_INS_SET::ND_SET_MSRLIST => Ok(IsaSet::MSRLIST),
|
||||
ffi::_ND_INS_SET::ND_SET_MSR_IMM => Ok(IsaSet::MSR_IMM),
|
||||
ffi::_ND_INS_SET::ND_SET_MWAITT => Ok(IsaSet::MWAITT),
|
||||
ffi::_ND_INS_SET::ND_SET_PAUSE => Ok(IsaSet::PAUSE),
|
||||
ffi::_ND_INS_SET::ND_SET_PCLMULQDQ => Ok(IsaSet::PCLMULQDQ),
|
||||
|
||||
@ -411,6 +411,7 @@ pub enum Mnemonic {
|
||||
MOVNTSS,
|
||||
MOVQ,
|
||||
MOVQ2DQ,
|
||||
MOVRS,
|
||||
MOVS,
|
||||
MOVSD,
|
||||
MOVSHDUP,
|
||||
@ -570,6 +571,7 @@ pub enum Mnemonic {
|
||||
PREFETCHIT1,
|
||||
PREFETCHM,
|
||||
PREFETCHNTA,
|
||||
PREFETCHRST2,
|
||||
PREFETCHT0,
|
||||
PREFETCHT1,
|
||||
PREFETCHT2,
|
||||
@ -720,24 +722,53 @@ pub enum Mnemonic {
|
||||
SYSEXIT,
|
||||
SYSRET,
|
||||
T1MSKC,
|
||||
T2RPNTLVWZ0,
|
||||
T2RPNTLVWZ0RS,
|
||||
T2RPNTLVWZ0RST1,
|
||||
T2RPNTLVWZ0T1,
|
||||
T2RPNTLVWZ1,
|
||||
T2RPNTLVWZ1RS,
|
||||
T2RPNTLVWZ1RST1,
|
||||
T2RPNTLVWZ1T1,
|
||||
TCMMIMFP16PS,
|
||||
TCMMRLFP16PS,
|
||||
TCONJTCMMIMFP16PS,
|
||||
TCONJTFP16,
|
||||
TCVTROWD2PS,
|
||||
TCVTROWPS2PBF16H,
|
||||
TCVTROWPS2PBF16L,
|
||||
TCVTROWPS2PHH,
|
||||
TCVTROWPS2PHL,
|
||||
TDCALL,
|
||||
TDPBF16PS,
|
||||
TDPBF8PS,
|
||||
TDPBHF8PS,
|
||||
TDPBSSD,
|
||||
TDPBSUD,
|
||||
TDPBUSD,
|
||||
TDPBUUD,
|
||||
TDPFP16PS,
|
||||
TDPHBF8PS,
|
||||
TDPHF8PS,
|
||||
TEST,
|
||||
TESTUI,
|
||||
TILELOADD,
|
||||
TILELOADDRS,
|
||||
TILELOADDRST1,
|
||||
TILELOADDT1,
|
||||
TILEMOVROW,
|
||||
TILERELEASE,
|
||||
TILESTORED,
|
||||
TILEZERO,
|
||||
TLBSYNC,
|
||||
TMMULTF32PS,
|
||||
TPAUSE,
|
||||
TTCMMIMFP16PS,
|
||||
TTCMMRLFP16PS,
|
||||
TTDPBF16PS,
|
||||
TTDPFP16PS,
|
||||
TTMMULTF32PS,
|
||||
TTRANSPOSED,
|
||||
TZCNT,
|
||||
TZMSK,
|
||||
UCOMISD,
|
||||
@ -1211,6 +1242,10 @@ pub enum Mnemonic {
|
||||
VMOVNTPD,
|
||||
VMOVNTPS,
|
||||
VMOVQ,
|
||||
VMOVRSB,
|
||||
VMOVRSD,
|
||||
VMOVRSQ,
|
||||
VMOVRSW,
|
||||
VMOVSD,
|
||||
VMOVSH,
|
||||
VMOVSHDUP,
|
||||
@ -2134,6 +2169,7 @@ impl TryFrom<ffi::ND_INS_CLASS> for Mnemonic {
|
||||
ffi::_ND_INS_CLASS::ND_INS_MOVNTSS => Ok(Mnemonic::MOVNTSS),
|
||||
ffi::_ND_INS_CLASS::ND_INS_MOVQ => Ok(Mnemonic::MOVQ),
|
||||
ffi::_ND_INS_CLASS::ND_INS_MOVQ2DQ => Ok(Mnemonic::MOVQ2DQ),
|
||||
ffi::_ND_INS_CLASS::ND_INS_MOVRS => Ok(Mnemonic::MOVRS),
|
||||
ffi::_ND_INS_CLASS::ND_INS_MOVS => Ok(Mnemonic::MOVS),
|
||||
ffi::_ND_INS_CLASS::ND_INS_MOVSD => Ok(Mnemonic::MOVSD),
|
||||
ffi::_ND_INS_CLASS::ND_INS_MOVSHDUP => Ok(Mnemonic::MOVSHDUP),
|
||||
@ -2293,6 +2329,7 @@ impl TryFrom<ffi::ND_INS_CLASS> for Mnemonic {
|
||||
ffi::_ND_INS_CLASS::ND_INS_PREFETCHIT1 => Ok(Mnemonic::PREFETCHIT1),
|
||||
ffi::_ND_INS_CLASS::ND_INS_PREFETCHM => Ok(Mnemonic::PREFETCHM),
|
||||
ffi::_ND_INS_CLASS::ND_INS_PREFETCHNTA => Ok(Mnemonic::PREFETCHNTA),
|
||||
ffi::_ND_INS_CLASS::ND_INS_PREFETCHRST2 => Ok(Mnemonic::PREFETCHRST2),
|
||||
ffi::_ND_INS_CLASS::ND_INS_PREFETCHT0 => Ok(Mnemonic::PREFETCHT0),
|
||||
ffi::_ND_INS_CLASS::ND_INS_PREFETCHT1 => Ok(Mnemonic::PREFETCHT1),
|
||||
ffi::_ND_INS_CLASS::ND_INS_PREFETCHT2 => Ok(Mnemonic::PREFETCHT2),
|
||||
@ -2443,24 +2480,53 @@ impl TryFrom<ffi::ND_INS_CLASS> for Mnemonic {
|
||||
ffi::_ND_INS_CLASS::ND_INS_SYSEXIT => Ok(Mnemonic::SYSEXIT),
|
||||
ffi::_ND_INS_CLASS::ND_INS_SYSRET => Ok(Mnemonic::SYSRET),
|
||||
ffi::_ND_INS_CLASS::ND_INS_T1MSKC => Ok(Mnemonic::T1MSKC),
|
||||
ffi::_ND_INS_CLASS::ND_INS_T2RPNTLVWZ0 => Ok(Mnemonic::T2RPNTLVWZ0),
|
||||
ffi::_ND_INS_CLASS::ND_INS_T2RPNTLVWZ0RS => Ok(Mnemonic::T2RPNTLVWZ0RS),
|
||||
ffi::_ND_INS_CLASS::ND_INS_T2RPNTLVWZ0RST1 => Ok(Mnemonic::T2RPNTLVWZ0RST1),
|
||||
ffi::_ND_INS_CLASS::ND_INS_T2RPNTLVWZ0T1 => Ok(Mnemonic::T2RPNTLVWZ0T1),
|
||||
ffi::_ND_INS_CLASS::ND_INS_T2RPNTLVWZ1 => Ok(Mnemonic::T2RPNTLVWZ1),
|
||||
ffi::_ND_INS_CLASS::ND_INS_T2RPNTLVWZ1RS => Ok(Mnemonic::T2RPNTLVWZ1RS),
|
||||
ffi::_ND_INS_CLASS::ND_INS_T2RPNTLVWZ1RST1 => Ok(Mnemonic::T2RPNTLVWZ1RST1),
|
||||
ffi::_ND_INS_CLASS::ND_INS_T2RPNTLVWZ1T1 => Ok(Mnemonic::T2RPNTLVWZ1T1),
|
||||
ffi::_ND_INS_CLASS::ND_INS_TCMMIMFP16PS => Ok(Mnemonic::TCMMIMFP16PS),
|
||||
ffi::_ND_INS_CLASS::ND_INS_TCMMRLFP16PS => Ok(Mnemonic::TCMMRLFP16PS),
|
||||
ffi::_ND_INS_CLASS::ND_INS_TCONJTCMMIMFP16PS => Ok(Mnemonic::TCONJTCMMIMFP16PS),
|
||||
ffi::_ND_INS_CLASS::ND_INS_TCONJTFP16 => Ok(Mnemonic::TCONJTFP16),
|
||||
ffi::_ND_INS_CLASS::ND_INS_TCVTROWD2PS => Ok(Mnemonic::TCVTROWD2PS),
|
||||
ffi::_ND_INS_CLASS::ND_INS_TCVTROWPS2PBF16H => Ok(Mnemonic::TCVTROWPS2PBF16H),
|
||||
ffi::_ND_INS_CLASS::ND_INS_TCVTROWPS2PBF16L => Ok(Mnemonic::TCVTROWPS2PBF16L),
|
||||
ffi::_ND_INS_CLASS::ND_INS_TCVTROWPS2PHH => Ok(Mnemonic::TCVTROWPS2PHH),
|
||||
ffi::_ND_INS_CLASS::ND_INS_TCVTROWPS2PHL => Ok(Mnemonic::TCVTROWPS2PHL),
|
||||
ffi::_ND_INS_CLASS::ND_INS_TDCALL => Ok(Mnemonic::TDCALL),
|
||||
ffi::_ND_INS_CLASS::ND_INS_TDPBF16PS => Ok(Mnemonic::TDPBF16PS),
|
||||
ffi::_ND_INS_CLASS::ND_INS_TDPBF8PS => Ok(Mnemonic::TDPBF8PS),
|
||||
ffi::_ND_INS_CLASS::ND_INS_TDPBHF8PS => Ok(Mnemonic::TDPBHF8PS),
|
||||
ffi::_ND_INS_CLASS::ND_INS_TDPBSSD => Ok(Mnemonic::TDPBSSD),
|
||||
ffi::_ND_INS_CLASS::ND_INS_TDPBSUD => Ok(Mnemonic::TDPBSUD),
|
||||
ffi::_ND_INS_CLASS::ND_INS_TDPBUSD => Ok(Mnemonic::TDPBUSD),
|
||||
ffi::_ND_INS_CLASS::ND_INS_TDPBUUD => Ok(Mnemonic::TDPBUUD),
|
||||
ffi::_ND_INS_CLASS::ND_INS_TDPFP16PS => Ok(Mnemonic::TDPFP16PS),
|
||||
ffi::_ND_INS_CLASS::ND_INS_TDPHBF8PS => Ok(Mnemonic::TDPHBF8PS),
|
||||
ffi::_ND_INS_CLASS::ND_INS_TDPHF8PS => Ok(Mnemonic::TDPHF8PS),
|
||||
ffi::_ND_INS_CLASS::ND_INS_TEST => Ok(Mnemonic::TEST),
|
||||
ffi::_ND_INS_CLASS::ND_INS_TESTUI => Ok(Mnemonic::TESTUI),
|
||||
ffi::_ND_INS_CLASS::ND_INS_TILELOADD => Ok(Mnemonic::TILELOADD),
|
||||
ffi::_ND_INS_CLASS::ND_INS_TILELOADDRS => Ok(Mnemonic::TILELOADDRS),
|
||||
ffi::_ND_INS_CLASS::ND_INS_TILELOADDRST1 => Ok(Mnemonic::TILELOADDRST1),
|
||||
ffi::_ND_INS_CLASS::ND_INS_TILELOADDT1 => Ok(Mnemonic::TILELOADDT1),
|
||||
ffi::_ND_INS_CLASS::ND_INS_TILEMOVROW => Ok(Mnemonic::TILEMOVROW),
|
||||
ffi::_ND_INS_CLASS::ND_INS_TILERELEASE => Ok(Mnemonic::TILERELEASE),
|
||||
ffi::_ND_INS_CLASS::ND_INS_TILESTORED => Ok(Mnemonic::TILESTORED),
|
||||
ffi::_ND_INS_CLASS::ND_INS_TILEZERO => Ok(Mnemonic::TILEZERO),
|
||||
ffi::_ND_INS_CLASS::ND_INS_TLBSYNC => Ok(Mnemonic::TLBSYNC),
|
||||
ffi::_ND_INS_CLASS::ND_INS_TMMULTF32PS => Ok(Mnemonic::TMMULTF32PS),
|
||||
ffi::_ND_INS_CLASS::ND_INS_TPAUSE => Ok(Mnemonic::TPAUSE),
|
||||
ffi::_ND_INS_CLASS::ND_INS_TTCMMIMFP16PS => Ok(Mnemonic::TTCMMIMFP16PS),
|
||||
ffi::_ND_INS_CLASS::ND_INS_TTCMMRLFP16PS => Ok(Mnemonic::TTCMMRLFP16PS),
|
||||
ffi::_ND_INS_CLASS::ND_INS_TTDPBF16PS => Ok(Mnemonic::TTDPBF16PS),
|
||||
ffi::_ND_INS_CLASS::ND_INS_TTDPFP16PS => Ok(Mnemonic::TTDPFP16PS),
|
||||
ffi::_ND_INS_CLASS::ND_INS_TTMMULTF32PS => Ok(Mnemonic::TTMMULTF32PS),
|
||||
ffi::_ND_INS_CLASS::ND_INS_TTRANSPOSED => Ok(Mnemonic::TTRANSPOSED),
|
||||
ffi::_ND_INS_CLASS::ND_INS_TZCNT => Ok(Mnemonic::TZCNT),
|
||||
ffi::_ND_INS_CLASS::ND_INS_TZMSK => Ok(Mnemonic::TZMSK),
|
||||
ffi::_ND_INS_CLASS::ND_INS_UCOMISD => Ok(Mnemonic::UCOMISD),
|
||||
@ -2934,6 +3000,10 @@ impl TryFrom<ffi::ND_INS_CLASS> for Mnemonic {
|
||||
ffi::_ND_INS_CLASS::ND_INS_VMOVNTPD => Ok(Mnemonic::VMOVNTPD),
|
||||
ffi::_ND_INS_CLASS::ND_INS_VMOVNTPS => Ok(Mnemonic::VMOVNTPS),
|
||||
ffi::_ND_INS_CLASS::ND_INS_VMOVQ => Ok(Mnemonic::VMOVQ),
|
||||
ffi::_ND_INS_CLASS::ND_INS_VMOVRSB => Ok(Mnemonic::VMOVRSB),
|
||||
ffi::_ND_INS_CLASS::ND_INS_VMOVRSD => Ok(Mnemonic::VMOVRSD),
|
||||
ffi::_ND_INS_CLASS::ND_INS_VMOVRSQ => Ok(Mnemonic::VMOVRSQ),
|
||||
ffi::_ND_INS_CLASS::ND_INS_VMOVRSW => Ok(Mnemonic::VMOVRSW),
|
||||
ffi::_ND_INS_CLASS::ND_INS_VMOVSD => Ok(Mnemonic::VMOVSD),
|
||||
ffi::_ND_INS_CLASS::ND_INS_VMOVSH => Ok(Mnemonic::VMOVSH),
|
||||
ffi::_ND_INS_CLASS::ND_INS_VMOVSHDUP => Ok(Mnemonic::VMOVSHDUP),
|
||||
|
||||
@ -906,7 +906,7 @@ impl<'a> OperandsLookup<'a> {
|
||||
/// # Arguments
|
||||
///
|
||||
/// * `index` - The index of the destination operand. First destination operand has index 0, the second one has
|
||||
/// index 1, etc.
|
||||
/// index 1, etc.
|
||||
///
|
||||
/// # Returns
|
||||
///
|
||||
@ -936,7 +936,7 @@ impl<'a> OperandsLookup<'a> {
|
||||
/// # Arguments
|
||||
///
|
||||
/// * `index` - The index of the source operand. First source operand has index 0, the second one has
|
||||
/// index 1, etc.
|
||||
/// index 1, etc.
|
||||
///
|
||||
/// # Returns
|
||||
///
|
||||
|
||||
@ -188,9 +188,14 @@ set_to_string(
|
||||
case ND_SET_AMD: return "AMD";
|
||||
case ND_SET_AMXBF16: return "AMX-BF16";
|
||||
case ND_SET_AMXFP16: return "AMX-FP16";
|
||||
case ND_SET_AMXFP8: return "AMX-FP8";
|
||||
case ND_SET_AMXINT8: return "AMX-INT8";
|
||||
case ND_SET_AMXTILE: return "AMX-TILE";
|
||||
case ND_SET_AMXCOMPLEX: return "AMX-COMPLEX";
|
||||
case ND_SET_AMXTF32: return "AMX-TF32";
|
||||
case ND_SET_AMXAVX512: return "AMX-AVX512";
|
||||
case ND_SET_AMXMOVRS: return "AMX-MOVRS";
|
||||
case ND_SET_AMXTRANSPOSE: return "AMX-TRANSPOSE";
|
||||
case ND_SET_AVX: return "AVX";
|
||||
case ND_SET_AVX102: return "AVX10_2";
|
||||
case ND_SET_AVX2: return "AVX2";
|
||||
@ -256,8 +261,10 @@ set_to_string(
|
||||
case ND_SET_MOVBE: return "MOVBE";
|
||||
case ND_SET_MOVDIR64B: return "MOVDIR64B";
|
||||
case ND_SET_MOVDIRI: return "MOVDIRI";
|
||||
case ND_SET_MOVRS: return "MOVRS";
|
||||
case ND_SET_MPX: return "MPX";
|
||||
case ND_SET_MSRLIST: return "MSRLIST";
|
||||
case ND_SET_MSR_IMM: return "MSR_IMM";
|
||||
case ND_SET_MWAITT: return "MWAITT";
|
||||
case ND_SET_PAUSE: return "PAUSE";
|
||||
case ND_SET_PCLMULQDQ: return "PCLMULQDQ";
|
||||
@ -609,10 +616,20 @@ exception_type_to_string(
|
||||
case ND_EXT_AMX_E4: return "AMX-E4";
|
||||
case ND_EXT_AMX_E5: return "AMX-E5";
|
||||
case ND_EXT_AMX_E6: return "AMX-E6";
|
||||
case ND_EXT_AMX_E7: return "AMX-E7";
|
||||
case ND_EXT_AMX_E8: return "AMX-E8";
|
||||
case ND_EXT_AMX_E9: return "AMX-E9";
|
||||
case ND_EXT_AMX_E10: return "AMX-E10";
|
||||
case ND_EXT_AMX_E11: return "AMX-E11";
|
||||
|
||||
case ND_EXT_AMX_EVEX_E1: return "AMX-EVEX-E1";
|
||||
case ND_EXT_AMX_EVEX_E2: return "AMX-EVEX-E2";
|
||||
case ND_EXT_AMX_EVEX_E3: return "AMX-EVEX-E3";
|
||||
case ND_EXT_AMX_EVEX_E4: return "AMX-EVEX-E4";
|
||||
case ND_EXT_AMX_EVEX_E5: return "AMX-EVEX-E5";
|
||||
case ND_EXT_AMX_EVEX_E6: return "AMX-EVEX-E6";
|
||||
case ND_EXT_AMX_EVEX_E7: return "AMX-EVEX-E7";
|
||||
case ND_EXT_AMX_EVEX_E8: return "AMX-EVEX-E8";
|
||||
|
||||
case ND_EXT_APX_EVEX_BMI: return "APX-EVEX-BMI";
|
||||
case ND_EXT_APX_EVEX_CCMP: return "APX-EVEX-CCMP";
|
||||
@ -865,12 +882,23 @@ print_instruction(
|
||||
Instrux->ExceptionType >= ND_EXT_1 && Instrux->ExceptionType <= ND_EXT_14 ? "SSE/VEX" :
|
||||
Instrux->ExceptionType >= ND_EXT_E1 && Instrux->ExceptionType <= ND_EXT_E12NP ? "EVEX" :
|
||||
Instrux->ExceptionType >= ND_EXT_K20 && Instrux->ExceptionType <= ND_EXT_K21 ? "Opmask" :
|
||||
Instrux->ExceptionType >= ND_EXT_AMX_E1 && Instrux->ExceptionType <= ND_EXT_AMX_E6 ? "AMX" :
|
||||
Instrux->ExceptionType >= ND_EXT_AMX_E1 && Instrux->ExceptionType <= ND_EXT_AMX_E11 ? "AMX" :
|
||||
Instrux->ExceptionType >= ND_EXT_AMX_EVEX_E1 && Instrux->ExceptionType <= ND_EXT_APX_EVEX_USER_MSR ? "APX" : "???");
|
||||
|
||||
printf("exception type: %s\n", exception_type_to_string(Instrux->ExceptionType));
|
||||
}
|
||||
|
||||
if (Instrux->SimdExceptions.Raw != 0)
|
||||
{
|
||||
printf(" SIMD Exceptions: %s%s%s%s%s%s\n",
|
||||
Instrux->SimdExceptions.IE ? "I" : "",
|
||||
Instrux->SimdExceptions.DE ? "D" : "",
|
||||
Instrux->SimdExceptions.ZE ? "Z" : "",
|
||||
Instrux->SimdExceptions.OE ? "O" : "",
|
||||
Instrux->SimdExceptions.UE ? "U" : "",
|
||||
Instrux->SimdExceptions.PE ? "P" : "");
|
||||
}
|
||||
|
||||
if (Instrux->RflAccess != 0)
|
||||
{
|
||||
DWORD fidx, all;
|
||||
|
||||
@ -6,7 +6,7 @@
|
||||
#define BDDISASM_VERSION_H
|
||||
|
||||
#define DISASM_VERSION_MAJOR 2
|
||||
#define DISASM_VERSION_MINOR 2
|
||||
#define DISASM_VERSION_MINOR 3
|
||||
#define DISASM_VERSION_REVISION 0
|
||||
|
||||
#define SHEMU_VERSION_MAJOR DISASM_VERSION_MAJOR
|
||||
|
||||
@ -414,6 +414,7 @@ typedef enum _ND_INS_CLASS
|
||||
ND_INS_MOVNTSS,
|
||||
ND_INS_MOVQ,
|
||||
ND_INS_MOVQ2DQ,
|
||||
ND_INS_MOVRS,
|
||||
ND_INS_MOVS,
|
||||
ND_INS_MOVSD,
|
||||
ND_INS_MOVSHDUP,
|
||||
@ -573,6 +574,7 @@ typedef enum _ND_INS_CLASS
|
||||
ND_INS_PREFETCHIT1,
|
||||
ND_INS_PREFETCHM,
|
||||
ND_INS_PREFETCHNTA,
|
||||
ND_INS_PREFETCHRST2,
|
||||
ND_INS_PREFETCHT0,
|
||||
ND_INS_PREFETCHT1,
|
||||
ND_INS_PREFETCHT2,
|
||||
@ -723,24 +725,53 @@ typedef enum _ND_INS_CLASS
|
||||
ND_INS_SYSEXIT,
|
||||
ND_INS_SYSRET,
|
||||
ND_INS_T1MSKC,
|
||||
ND_INS_T2RPNTLVWZ0,
|
||||
ND_INS_T2RPNTLVWZ0RS,
|
||||
ND_INS_T2RPNTLVWZ0RST1,
|
||||
ND_INS_T2RPNTLVWZ0T1,
|
||||
ND_INS_T2RPNTLVWZ1,
|
||||
ND_INS_T2RPNTLVWZ1RS,
|
||||
ND_INS_T2RPNTLVWZ1RST1,
|
||||
ND_INS_T2RPNTLVWZ1T1,
|
||||
ND_INS_TCMMIMFP16PS,
|
||||
ND_INS_TCMMRLFP16PS,
|
||||
ND_INS_TCONJTCMMIMFP16PS,
|
||||
ND_INS_TCONJTFP16,
|
||||
ND_INS_TCVTROWD2PS,
|
||||
ND_INS_TCVTROWPS2PBF16H,
|
||||
ND_INS_TCVTROWPS2PBF16L,
|
||||
ND_INS_TCVTROWPS2PHH,
|
||||
ND_INS_TCVTROWPS2PHL,
|
||||
ND_INS_TDCALL,
|
||||
ND_INS_TDPBF16PS,
|
||||
ND_INS_TDPBF8PS,
|
||||
ND_INS_TDPBHF8PS,
|
||||
ND_INS_TDPBSSD,
|
||||
ND_INS_TDPBSUD,
|
||||
ND_INS_TDPBUSD,
|
||||
ND_INS_TDPBUUD,
|
||||
ND_INS_TDPFP16PS,
|
||||
ND_INS_TDPHBF8PS,
|
||||
ND_INS_TDPHF8PS,
|
||||
ND_INS_TEST,
|
||||
ND_INS_TESTUI,
|
||||
ND_INS_TILELOADD,
|
||||
ND_INS_TILELOADDRS,
|
||||
ND_INS_TILELOADDRST1,
|
||||
ND_INS_TILELOADDT1,
|
||||
ND_INS_TILEMOVROW,
|
||||
ND_INS_TILERELEASE,
|
||||
ND_INS_TILESTORED,
|
||||
ND_INS_TILEZERO,
|
||||
ND_INS_TLBSYNC,
|
||||
ND_INS_TMMULTF32PS,
|
||||
ND_INS_TPAUSE,
|
||||
ND_INS_TTCMMIMFP16PS,
|
||||
ND_INS_TTCMMRLFP16PS,
|
||||
ND_INS_TTDPBF16PS,
|
||||
ND_INS_TTDPFP16PS,
|
||||
ND_INS_TTMMULTF32PS,
|
||||
ND_INS_TTRANSPOSED,
|
||||
ND_INS_TZCNT,
|
||||
ND_INS_TZMSK,
|
||||
ND_INS_UCOMISD,
|
||||
@ -1214,6 +1245,10 @@ typedef enum _ND_INS_CLASS
|
||||
ND_INS_VMOVNTPD,
|
||||
ND_INS_VMOVNTPS,
|
||||
ND_INS_VMOVQ,
|
||||
ND_INS_VMOVRSB,
|
||||
ND_INS_VMOVRSD,
|
||||
ND_INS_VMOVRSQ,
|
||||
ND_INS_VMOVRSW,
|
||||
ND_INS_VMOVSD,
|
||||
ND_INS_VMOVSH,
|
||||
ND_INS_VMOVSHDUP,
|
||||
@ -1738,11 +1773,16 @@ typedef enum _ND_INS_SET
|
||||
ND_SET_ADX,
|
||||
ND_SET_AES,
|
||||
ND_SET_AMD,
|
||||
ND_SET_AMXAVX512,
|
||||
ND_SET_AMXBF16,
|
||||
ND_SET_AMXCOMPLEX,
|
||||
ND_SET_AMXFP16,
|
||||
ND_SET_AMXFP8,
|
||||
ND_SET_AMXINT8,
|
||||
ND_SET_AMXMOVRS,
|
||||
ND_SET_AMXTF32,
|
||||
ND_SET_AMXTILE,
|
||||
ND_SET_AMXTRANSPOSE,
|
||||
ND_SET_APX_F,
|
||||
ND_SET_AVX,
|
||||
ND_SET_AVX102,
|
||||
@ -1809,8 +1849,10 @@ typedef enum _ND_INS_SET
|
||||
ND_SET_MOVBE,
|
||||
ND_SET_MOVDIR64B,
|
||||
ND_SET_MOVDIRI,
|
||||
ND_SET_MOVRS,
|
||||
ND_SET_MPX,
|
||||
ND_SET_MSRLIST,
|
||||
ND_SET_MSR_IMM,
|
||||
ND_SET_MWAITT,
|
||||
ND_SET_PAUSE,
|
||||
ND_SET_PCLMULQDQ,
|
||||
|
||||
@ -627,11 +627,21 @@ typedef enum _ND_EX_TYPE
|
||||
ND_EXT_AMX_E4,
|
||||
ND_EXT_AMX_E5,
|
||||
ND_EXT_AMX_E6,
|
||||
ND_EXT_AMX_E7,
|
||||
ND_EXT_AMX_E8,
|
||||
ND_EXT_AMX_E9,
|
||||
ND_EXT_AMX_E10,
|
||||
ND_EXT_AMX_E11,
|
||||
|
||||
// AMX-EVEX exceptions.
|
||||
ND_EXT_AMX_EVEX_E1,
|
||||
ND_EXT_AMX_EVEX_E2,
|
||||
ND_EXT_AMX_EVEX_E3,
|
||||
ND_EXT_AMX_EVEX_E4,
|
||||
ND_EXT_AMX_EVEX_E5,
|
||||
ND_EXT_AMX_EVEX_E6,
|
||||
ND_EXT_AMX_EVEX_E7,
|
||||
ND_EXT_AMX_EVEX_E8,
|
||||
|
||||
// APX-EVEX exceptions.
|
||||
ND_EXT_APX_EVEX_BMI,
|
||||
@ -1195,15 +1205,45 @@ typedef union _ND_RFLAGS
|
||||
//
|
||||
// FPU status flags. Each status flag can be one of ND_FPU_FLAG*.
|
||||
//
|
||||
typedef struct _ND_FPU_FLAGS
|
||||
typedef union _ND_FPU_FLAGS
|
||||
{
|
||||
ND_UINT8 C0 : 2; // C0 flag access mode. See ND_FPU_FLAG_*.
|
||||
ND_UINT8 C1 : 2; // C1 flag access mode. See ND_FPU_FLAG_*.
|
||||
ND_UINT8 C2 : 2; // C2 flag access mode. See ND_FPU_FLAG_*.
|
||||
ND_UINT8 C3 : 2; // C3 flag access mode. See ND_FPU_FLAG_*.
|
||||
ND_UINT8 Raw;
|
||||
struct
|
||||
{
|
||||
ND_UINT8 C0 : 2; // C0 flag access mode. See ND_FPU_FLAG_*.
|
||||
ND_UINT8 C1 : 2; // C1 flag access mode. See ND_FPU_FLAG_*.
|
||||
ND_UINT8 C2 : 2; // C2 flag access mode. See ND_FPU_FLAG_*.
|
||||
ND_UINT8 C3 : 2; // C3 flag access mode. See ND_FPU_FLAG_*.
|
||||
};
|
||||
} ND_FPU_FLAGS, *PND_FPU_FLAGS;
|
||||
|
||||
|
||||
#define ND_SIMD_EXC_IE 0x01 // Invalid Operation Exception.
|
||||
#define ND_SIMD_EXC_DE 0x02 // Denormal Exception.
|
||||
#define ND_SIMD_EXC_ZE 0x04 // Divide-by-Zero Exception.
|
||||
#define ND_SIMD_EXC_OE 0x08 // Overflow Exception.
|
||||
#define ND_SIMD_EXC_UE 0x10 // Underflow Exception.
|
||||
#define ND_SIMD_EXC_PE 0x20 // Precision Exception.
|
||||
|
||||
//
|
||||
// SIMD Floating-Point Exceptions. These values are the same as lower 6 bits in MXCSR. The Raw field
|
||||
// is a combination of ND_SIMD_EXC_* values, and is the same as the invidiual bitfields.
|
||||
//
|
||||
typedef union _ND_SIMD_EXCEPTIONS
|
||||
{
|
||||
ND_UINT8 Raw;
|
||||
struct
|
||||
{
|
||||
ND_UINT8 IE : 1; // Invalid Operation Exception.
|
||||
ND_UINT8 DE : 1; // Denormal Exception.
|
||||
ND_UINT8 ZE : 1; // Divide-by-Zero Exception.
|
||||
ND_UINT8 OE : 1; // Overflow Exception.
|
||||
ND_UINT8 UE : 1; // Underflow Exception.
|
||||
ND_UINT8 PE : 1; // Precision Exception.
|
||||
};
|
||||
} ND_SIMD_EXCEPTIONS;
|
||||
|
||||
|
||||
//
|
||||
// Branch information.
|
||||
//
|
||||
@ -1392,7 +1432,8 @@ typedef struct _INSTRUX
|
||||
// implicit operands such as stack, flags, etc.
|
||||
ND_OPERAND Operands[ND_MAX_OPERAND]; // Instruction operands.
|
||||
|
||||
// EVEX information.
|
||||
// SIMD/EVEX information.
|
||||
ND_SIMD_EXCEPTIONS SimdExceptions; // SIMD Floating-Point Exceptions. Valid only for SIMD instructions!
|
||||
ND_UINT8 ExceptionType; // Exception type. One of ND_EX_TYPE.
|
||||
ND_UINT8 TupleType; // EVEX tuple type, if EVEX. One of ND_TUPLE.
|
||||
|
||||
@ -1466,6 +1507,13 @@ typedef struct _ND_CONTEXT
|
||||
/// CsAccess, RipAccess, RflAccess, StackAcces, MemoryAccess, BranchInfo.
|
||||
#define ND_OPTION_ONLY_EXPLICIT_OPERANDS 0x00000001
|
||||
|
||||
// Do NOT zero the output INSTRUX structure before decoding this instruction. Use this option only if the
|
||||
// output INSTRUX structure is already zeroed (for example, as is the case when allocating it with calloc).
|
||||
// Make sure to NOT use this option when making succesive decode calls on the same buffer - this option
|
||||
// should only be used when decoding an instruction in an output buffer that has just been allocated and
|
||||
// has been 0-initialized, or if the caller explictly zeroed it before each decode call.
|
||||
#define ND_OPTION_SKIP_ZERO_INSTRUX 0x00000002
|
||||
|
||||
|
||||
//
|
||||
// Operands access map. Contains every register except for MSR & XCR, includes memory, flags, RIP, stack.
|
||||
|
||||
@ -107,7 +107,9 @@
|
||||
#define ND_CFF_HRESET ND_CFF(0x00000007, 0x00000001, NDR_EAX, 22)
|
||||
#define ND_CFF_AVXIFMA ND_CFF(0x00000007, 0x00000001, NDR_EAX, 23)
|
||||
#define ND_CFF_MSRLIST ND_CFF(0x00000007, 0x00000001, NDR_EAX, 27)
|
||||
#define ND_CFF_MOVRS ND_CFF(0x00000007, 0x00000001, NDR_EAX, 31)
|
||||
#define ND_CFF_TSE ND_CFF(0x00000007, 0x00000001, NDR_EBX, 1)
|
||||
#define ND_CFF_MSR_IMM ND_CFF(0x00000007, 0x00000001, NDR_ECX, 5)
|
||||
#define ND_CFF_AVXVNNIINT8 ND_CFF(0x00000007, 0x00000001, NDR_EDX, 4)
|
||||
#define ND_CFF_AVXNECONVERT ND_CFF(0x00000007, 0x00000001, NDR_EDX, 5)
|
||||
#define ND_CFF_AMXCOMPLEX ND_CFF(0x00000007, 0x00000001, NDR_EDX, 8)
|
||||
@ -119,6 +121,11 @@
|
||||
#define ND_CFF_XSAVEC ND_CFF(0x0000000D, 0x00000001, NDR_EAX, 1)
|
||||
#define ND_CFF_XSAVES ND_CFF(0x0000000D, 0x00000001, NDR_EAX, 3)
|
||||
#define ND_CFF_PTWRITE ND_CFF(0x00000014, 0x00000000, NDR_EBX, 4)
|
||||
#define ND_CFF_AMXFP8 ND_CFF(0x0000001E, 0x00000001, NDR_EAX, 4)
|
||||
#define ND_CFF_AMXTRANSPOSE ND_CFF(0x0000001E, 0x00000001, NDR_EAX, 5)
|
||||
#define ND_CFF_AMXTF32 ND_CFF(0x0000001E, 0x00000001, NDR_EAX, 6)
|
||||
#define ND_CFF_AMXAVX512 ND_CFF(0x0000001E, 0x00000001, NDR_EAX, 7)
|
||||
#define ND_CFF_AMXMOVRS ND_CFF(0x0000001E, 0x00000001, NDR_EAX, 8)
|
||||
#define ND_CFF_SVM ND_CFF(0x80000001, 0xFFFFFFFF, NDR_ECX, 2)
|
||||
#define ND_CFF_LZCNT ND_CFF(0x80000001, 0xFFFFFFFF, NDR_ECX, 5)
|
||||
#define ND_CFF_SSE4A ND_CFF(0x80000001, 0xFFFFFFFF, NDR_ECX, 6)
|
||||
|
||||
@ -543,6 +543,16 @@ valid_evex_mode = [
|
||||
'cond', # EVEX extension for conditional instructons
|
||||
]
|
||||
|
||||
# Valid SIMD Floating-Point Exceptions.
|
||||
valid_simd_exceptions = [
|
||||
'IE', # Invalid Operation Exception.
|
||||
'DE', # Denormal Exception.
|
||||
'ZE', # Divide-by-Zero Exception.
|
||||
'OE', # Overflow Exception.
|
||||
'UE', # Underflow Exception.
|
||||
'PE', # Precision Exception.
|
||||
]
|
||||
|
||||
|
||||
# Use one of these value to indicate absent operands.
|
||||
absent_op = ['n/a', '']
|
||||
@ -752,6 +762,9 @@ class Instruction():
|
||||
FpuFlags: list[str]
|
||||
FPU flags access mode (example: ['u', 'u', 'u', 'u']). A list of 4 str elements, each one
|
||||
indicating the access mode for flag Cx, where x is the position in the list.
|
||||
SimdExc: list[str]
|
||||
SIMD Floating-Point Exceptions (MXCSR flags affected) by the instruction (example: ['IE', 'OE', 'UE']).
|
||||
A list of strings, each string indicating if that particular SIMD exception is raised (or MXCSR flag).
|
||||
Modes: list[str]
|
||||
Valid operating modes for the indicated instruction.
|
||||
Encoding: dict
|
||||
@ -847,6 +860,7 @@ class Instruction():
|
||||
self.EvexMode = None
|
||||
self.Rflags = {'m': [], 't': [], '0': [], '1': [], 'u': []}
|
||||
self.FpuFlags = ['u', 'u', 'u', 'u']
|
||||
self.SimdExc = []
|
||||
self.Modes = valid_cpu_modes.copy()
|
||||
|
||||
for y in self.RawMeta:
|
||||
@ -988,6 +1002,12 @@ class Instruction():
|
||||
(m, ','.join(valid_cpu_modes)))
|
||||
|
||||
self.Modes = modes
|
||||
elif token == "x":
|
||||
for e in value.split('|'):
|
||||
if e not in valid_simd_exceptions:
|
||||
raise InvalidSpecificationException("Unknown SIMDexception '%s', expecting one of [%s]" %
|
||||
(e, ','.join(valid_simd_exceptions)))
|
||||
self.SimdExc.append(e)
|
||||
else:
|
||||
raise InvalidSpecificationException("Unknown token specified: %s" % token)
|
||||
|
||||
@ -1203,6 +1223,7 @@ def parse_entry(
|
||||
10. 'f': flags access ('m': modified, 't': tested, 'u': undefined, '0': cleared, '1': set to 1)
|
||||
11. 'u': FPU flags access
|
||||
12. 'm': valid operating modes
|
||||
13. 'x': SIMD exceptions/MXCSR flags
|
||||
|
||||
Raises
|
||||
------
|
||||
|
||||
@ -266,6 +266,12 @@ def instrux_to_idbe(
|
||||
else:
|
||||
d['EvexMode'] = '0'
|
||||
|
||||
# SIMD Floating-Point Exceptions.
|
||||
if ins.SimdExc:
|
||||
d['SimdExc'] = '|'.join(['ND_SIMD_EXC_' + x for x in ins.SimdExc])
|
||||
else:
|
||||
d['SimdExc'] = '0'
|
||||
|
||||
# Flags (tested, modified, set, cleared)
|
||||
for m in ['t', 'm', '1', '0']:
|
||||
flg = '0'
|
||||
@ -362,6 +368,7 @@ def cdef_instruction(
|
||||
.ExcType = 0,
|
||||
.FpuFlags = 0,
|
||||
.EvexMode = 0,
|
||||
.SimdExc = 0,
|
||||
.TestedFlags = 0,
|
||||
.ModifiedFlags = 0,
|
||||
.SetFlags = 0,
|
||||
@ -390,6 +397,7 @@ def cdef_instruction(
|
||||
/* ExcType */ 0,
|
||||
/* FpuFlags */ 0,
|
||||
/* EvexMode */ 0,
|
||||
/* SimdExc */ 0,
|
||||
/* TestedFlags */ 0,
|
||||
/* ModifiedFlags */ 0,
|
||||
/* SetFlags */ 0,
|
||||
|
||||
@ -94,7 +94,6 @@ AVX512FP16 : 0x00000007, 0x00000000, EDX, 23
|
||||
AMXTILE : 0x00000007, 0x00000000, EDX, 24
|
||||
AMXINT8 : 0x00000007, 0x00000000, EDX, 25
|
||||
|
||||
|
||||
SHA512 : 0x00000007, 0x00000001, EAX, 0
|
||||
SM3 : 0x00000007, 0x00000001, EAX, 1
|
||||
SM4 : 0x00000007, 0x00000001, EAX, 2
|
||||
@ -109,9 +108,9 @@ AMXFP16 : 0x00000007, 0x00000001, EAX, 21
|
||||
HRESET : 0x00000007, 0x00000001, EAX, 22
|
||||
AVXIFMA : 0x00000007, 0x00000001, EAX, 23
|
||||
MSRLIST : 0x00000007, 0x00000001, EAX, 27
|
||||
|
||||
MOVRS : 0x00000007, 0x00000001, EAX, 31
|
||||
TSE : 0x00000007, 0x00000001, EBX, 1
|
||||
|
||||
MSR_IMM : 0x00000007, 0x00000001, ECX, 5
|
||||
AVXVNNIINT8 : 0x00000007, 0x00000001, EDX, 4
|
||||
AVXNECONVERT : 0x00000007, 0x00000001, EDX, 5
|
||||
AMXCOMPLEX : 0x00000007, 0x00000001, EDX, 8
|
||||
@ -129,6 +128,13 @@ XSAVES : 0x0000000D, 0x00000001, EAX, 3
|
||||
PTWRITE : 0x00000014, 0x00000000, EBX, 4
|
||||
|
||||
|
||||
AMXFP8 : 0x0000001E, 0x00000001, EAX, 4
|
||||
AMXTRANSPOSE : 0x0000001E, 0x00000001, EAX, 5
|
||||
AMXTF32 : 0x0000001E, 0x00000001, EAX, 6
|
||||
AMXAVX512 : 0x0000001E, 0x00000001, EAX, 7
|
||||
AMXMOVRS : 0x0000001E, 0x00000001, EAX, 8
|
||||
|
||||
|
||||
SVM : 0x80000001, 0xFFFFFFFF, ECX, 2
|
||||
LZCNT : 0x80000001, 0xFFFFFFFF, ECX, 5
|
||||
SSE4A : 0x80000001, 0xFFFFFFFF, ECX, 6
|
||||
|
||||
@ -41,29 +41,29 @@ VMOVAPS ; Vfv{K}{z},Wfv ; ; evex m:1 p:0 l:x w:0
|
||||
VMOVAPD ; Vfv{K}{z},Wfv ; ; evex m:1 p:1 l:x w:1 0x28 /r ; s:AVX512F, t:DATAXFER, l:fvm, e:E1, w:W|R|R
|
||||
VMOVAPS ; Wfv{K}{z},Vfv ; ; evex m:1 p:0 l:x w:0 0x29 /r ; s:AVX512F, t:DATAXFER, l:fvm, e:E1, w:W|R|R
|
||||
VMOVAPD ; Wfv{K}{z},Vfv ; ; evex m:1 p:1 l:x w:1 0x29 /r ; s:AVX512F, t:DATAXFER, l:fvm, e:E1, w:W|R|R
|
||||
VCVTSI2SS ; Vdq,Hdq{er},Ey ; ; evex m:1 p:2 l:i w:x 0x2A /r ; s:AVX512F, t:CONVERT, l:t1s, e:E3, w:W|R|R, a:IWO64
|
||||
VCVTSI2SD ; Vdq,Hdq,Ey ; ; evex m:1 p:3 l:i w:0 0x2A /r ; s:AVX512F, t:CONVERT, l:t1s, e:E10NF, w:W|R|R, a:IER|IWO64
|
||||
VCVTSI2SD ; Vdq,Hdq{er},Ey ; ; evex m:1 p:3 l:i w:1 0x2A /r ; s:AVX512F, t:CONVERT, l:t1s, e:E3, w:W|R|R, a:IWO64
|
||||
VCVTSI2SS ; Vdq,Hdq{er},Ey ; ; evex m:1 p:2 l:i w:x 0x2A /r ; s:AVX512F, t:CONVERT, l:t1s, e:E3, w:W|R|R, a:IWO64, x:PE
|
||||
VCVTSI2SD ; Vdq,Hdq,Ey ; ; evex m:1 p:3 l:i w:0 0x2A /r ; s:AVX512F, t:CONVERT, l:t1s, e:E10NF, w:W|R|R, a:IER|IWO64, x:PE
|
||||
VCVTSI2SD ; Vdq,Hdq{er},Ey ; ; evex m:1 p:3 l:i w:1 0x2A /r ; s:AVX512F, t:CONVERT, l:t1s, e:E3, w:W|R|R, a:IWO64, x:PE
|
||||
VMOVNTPS ; Mfv,Vfv ; ; evex m:1 p:0 l:x w:0 0x2B /r:mem ; s:AVX512F, t:DATAXFER, l:fvm, e:E1NF, w:W|R
|
||||
VMOVNTPD ; Mfv,Vfv ; ; evex m:1 p:1 l:x w:1 0x2B /r:mem ; s:AVX512F, t:DATAXFER, l:fvm, e:E1NF, w:W|R
|
||||
VCVTTSS2SI ; Gy,Wss{sae} ; ; evex m:1 p:2 l:i w:x 0x2C /r ; s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R, a:IWO64
|
||||
VCVTTSD2SI ; Gy,Wsd{sae} ; ; evex m:1 p:3 l:i w:x 0x2C /r ; s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R, a:IWO64
|
||||
VCVTSS2SI ; Gy,Wss{er} ; ; evex m:1 p:2 l:i w:x 0x2D /r ; s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R, a:IWO64
|
||||
VCVTSD2SI ; Gy,Wsd{er} ; ; evex m:1 p:3 l:i w:x 0x2D /r ; s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R, a:IWO64
|
||||
VUCOMISS ; Vdq,Wss{sae} ; Fv ; evex m:1 p:0 l:i w:0 0x2E /r ; s:AVX512F, t:AVX512, l:t1s, w:R|R|W, e:E3, f:COMIS
|
||||
VUCOMISD ; Vdq,Wsd{sae} ; Fv ; evex m:1 p:1 l:i w:1 0x2E /r ; s:AVX512F, t:AVX512, l:t1s, w:R|R|W, e:E3, f:COMIS
|
||||
VUCOMXSD ; Vdq,Wsd{sae} ; Fv ; evex m:1 p:2 l:0 w:1 0x2E /r ; s:AVX102, t:AVX10CMPSFP, l:t1s, w:R|R|W, e:E3NF, f:CMPSFP
|
||||
VUCOMXSS ; Vdq,Wss{sae} ; Fv ; evex m:1 p:3 l:0 w:0 0x2E /r ; s:AVX102, t:AVX10CMPSFP, l:t1s, w:R|R|W, e:E3NF, f:CMPSFP
|
||||
VCOMISS ; Vdq,Wss{sae} ; Fv ; evex m:1 p:0 l:i w:0 0x2F /r ; s:AVX512F, t:AVX512, l:t1s, w:R|R|W, e:E3, f:COMIS
|
||||
VCOMISD ; Vdq,Wsd{sae} ; Fv ; evex m:1 p:1 l:i w:1 0x2F /r ; s:AVX512F, t:AVX512, l:t1s, w:R|R|W, e:E3, f:COMIS
|
||||
VCOMXSD ; Vdq,Wsd{sae} ; Fv ; evex m:1 p:2 l:0 w:1 0x2F /r ; s:AVX102, t:AVX10CMPSFP, l:t1s, w:R|R|W, e:E3NF, f:CMPSFP
|
||||
VCOMXSS ; Vdq,Wss{sae} ; Fv ; evex m:1 p:3 l:0 w:0 0x2F /r ; s:AVX102, t:AVX10CMPSFP, l:t1s, w:R|R|W, e:E3NF, f:CMPSFP
|
||||
VCVTTSS2SI ; Gy,Wss{sae} ; ; evex m:1 p:2 l:i w:x 0x2C /r ; s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R, a:IWO64, x:IE|PE
|
||||
VCVTTSD2SI ; Gy,Wsd{sae} ; ; evex m:1 p:3 l:i w:x 0x2C /r ; s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R, a:IWO64, x:IE|PE
|
||||
VCVTSS2SI ; Gy,Wss{er} ; ; evex m:1 p:2 l:i w:x 0x2D /r ; s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R, a:IWO64, x:IE|PE
|
||||
VCVTSD2SI ; Gy,Wsd{er} ; ; evex m:1 p:3 l:i w:x 0x2D /r ; s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R, a:IWO64, x:IE|PE
|
||||
VUCOMISS ; Vdq,Wss{sae} ; Fv ; evex m:1 p:0 l:i w:0 0x2E /r ; s:AVX512F, t:AVX512, l:t1s, w:R|R|W, e:E3, f:COMIS, x:IE|DE
|
||||
VUCOMISD ; Vdq,Wsd{sae} ; Fv ; evex m:1 p:1 l:i w:1 0x2E /r ; s:AVX512F, t:AVX512, l:t1s, w:R|R|W, e:E3, f:COMIS, x:IE|DE
|
||||
VUCOMXSS ; Vdq,Wss{sae} ; Fv ; evex m:1 p:2 l:i w:0 0x2E /r ; s:AVX102, t:AVX10CMPSFP, l:t1s, w:R|R|W, e:E3NF, f:CMPSFP, x:IE|DE
|
||||
VUCOMXSD ; Vdq,Wsd{sae} ; Fv ; evex m:1 p:3 l:i w:1 0x2E /r ; s:AVX102, t:AVX10CMPSFP, l:t1s, w:R|R|W, e:E3NF, f:CMPSFP, x:IE|DE
|
||||
VCOMISS ; Vdq,Wss{sae} ; Fv ; evex m:1 p:0 l:i w:0 0x2F /r ; s:AVX512F, t:AVX512, l:t1s, w:R|R|W, e:E3, f:COMIS, x:IE|DE
|
||||
VCOMISD ; Vdq,Wsd{sae} ; Fv ; evex m:1 p:1 l:i w:1 0x2F /r ; s:AVX512F, t:AVX512, l:t1s, w:R|R|W, e:E3, f:COMIS, x:IE|DE
|
||||
VCOMXSS ; Vdq,Wss{sae} ; Fv ; evex m:1 p:2 l:i w:0 0x2F /r ; s:AVX102, t:AVX10CMPSFP, l:t1s, w:R|R|W, e:E3NF, f:CMPSFP, x:IE|DE
|
||||
VCOMXSD ; Vdq,Wsd{sae} ; Fv ; evex m:1 p:3 l:i w:1 0x2F /r ; s:AVX102, t:AVX10CMPSFP, l:t1s, w:R|R|W, e:E3NF, f:CMPSFP, x:IE|DE
|
||||
|
||||
# 0x50 - 0x5F
|
||||
VSQRTPS ; Vfv{K}{z},Wfv|B32{er} ; ; evex m:1 p:0 l:x w:0 0x51 /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R
|
||||
VSQRTPD ; Vfv{K}{z},Wfv|B64{er} ; ; evex m:1 p:1 l:x w:1 0x51 /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R
|
||||
VSQRTSS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:1 p:2 l:i w:0 0x51 /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R
|
||||
VSQRTSD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:1 p:3 l:i w:1 0x51 /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R
|
||||
VSQRTPS ; Vfv{K}{z},Wfv|B32{er} ; ; evex m:1 p:0 l:x w:0 0x51 /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R, x:IE|PE|DE
|
||||
VSQRTPD ; Vfv{K}{z},Wfv|B64{er} ; ; evex m:1 p:1 l:x w:1 0x51 /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R, x:IE|PE|DE
|
||||
VSQRTSS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:1 p:2 l:i w:0 0x51 /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R, x:IE|PE|DE
|
||||
VSQRTSD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:1 p:3 l:i w:1 0x51 /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R, x:IE|PE|DE
|
||||
VANDPS ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:1 p:0 l:x w:0 0x54 /r ; s:AVX512DQ, t:LOGICAL_FP, l:fv, e:E4, w:W|R|R|R
|
||||
VANDPD ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:1 p:1 l:x w:1 0x54 /r ; s:AVX512DQ, t:LOGICAL_FP, l:fv, e:E4, w:W|R|R|R
|
||||
VANDNPS ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:1 p:0 l:x w:0 0x55 /r ; s:AVX512DQ, t:LOGICAL_FP, l:fv, e:E4, w:W|R|R|R
|
||||
@ -72,38 +72,38 @@ VORPS ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:1 p:0 l:x w:0
|
||||
VORPD ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:1 p:1 l:x w:1 0x56 /r ; s:AVX512DQ, t:LOGICAL_FP, l:fv, e:E4, w:W|R|R|R
|
||||
VXORPS ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:1 p:0 l:x w:0 0x57 /r ; s:AVX512DQ, t:LOGICAL_FP, l:fv, e:E4, w:W|R|R|R
|
||||
VXORPD ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:1 p:1 l:x w:1 0x57 /r ; s:AVX512DQ, t:LOGICAL_FP, l:fv, e:E4, w:W|R|R|R
|
||||
VADDPS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:1 p:0 l:x w:0 0x58 /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R
|
||||
VADDPD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:1 p:1 l:x w:1 0x58 /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R
|
||||
VADDSS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:1 p:2 l:i w:0 0x58 /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R
|
||||
VADDSD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:1 p:3 l:i w:1 0x58 /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R
|
||||
VMULPS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:1 p:0 l:x w:0 0x59 /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R
|
||||
VMULPD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:1 p:1 l:x w:1 0x59 /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R
|
||||
VMULSS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:1 p:2 l:i w:0 0x59 /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R
|
||||
VMULSD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:1 p:3 l:i w:1 0x59 /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R
|
||||
VCVTPS2PD ; Vfv{K}{z},Whv|B32{sae} ; ; evex m:1 p:0 l:x w:0 0x5A /r ; s:AVX512F, t:CONVERT, l:hv, e:E3, w:W|R|R
|
||||
VCVTPD2PS ; Vhv{K}{z},Wfv|B64{er} ; ; evex m:1 p:1 l:x w:1 0x5A /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R
|
||||
VCVTSS2SD ; Vdq{K}{z},Hdq,Wss{sae} ; ; evex m:1 p:2 l:i w:0 0x5A /r ; s:AVX512F, t:CONVERT, l:t1s, e:E3, w:W|R|R|R
|
||||
VCVTSD2SS ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:1 p:3 l:i w:1 0x5A /r ; s:AVX512F, t:CONVERT, l:t1s, e:E3, w:W|R|R|R
|
||||
VCVTDQ2PS ; Vfv{K}{z},Wfv|B32{er} ; ; evex m:1 p:0 l:x w:0 0x5B /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R
|
||||
VCVTQQ2PS ; Vhv{K}{z},Wfv|B64{er} ; ; evex m:1 p:0 l:x w:1 0x5B /r ; s:AVX512DQ, t:CONVERT, l:fv, e:E2, w:W|R|R
|
||||
VCVTPS2DQ ; Vfv{K}{z},Wfv|B32{er} ; ; evex m:1 p:1 l:x w:0 0x5B /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R
|
||||
VCVTTPS2DQ ; Vfv{K}{z},Wfv|B32{sae} ; ; evex m:1 p:2 l:x w:0 0x5B /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R
|
||||
VSUBPS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:1 p:0 l:x w:0 0x5C /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R
|
||||
VSUBPD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:1 p:1 l:x w:1 0x5C /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R
|
||||
VSUBSS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:1 p:2 l:i w:0 0x5C /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R
|
||||
VSUBSD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:1 p:3 l:i w:1 0x5C /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R
|
||||
VMINPS ; Vfv{K}{z},Hfv,Wfv|B32{sae} ; ; evex m:1 p:0 l:x w:0 0x5D /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R
|
||||
VMINPD ; Vfv{K}{z},Hfv,Wfv|B64{sae} ; ; evex m:1 p:1 l:x w:1 0x5D /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R
|
||||
VMINSS ; Vdq{K}{z},Hdq,Wss{sae} ; ; evex m:1 p:2 l:i w:0 0x5D /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R
|
||||
VMINSD ; Vdq{K}{z},Hdq,Wsd{sae} ; ; evex m:1 p:3 l:i w:1 0x5D /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R
|
||||
VDIVPS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:1 p:0 l:x w:0 0x5E /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R
|
||||
VDIVPD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:1 p:1 l:x w:1 0x5E /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R
|
||||
VDIVSS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:1 p:2 l:i w:0 0x5E /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R
|
||||
VDIVSD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:1 p:3 l:i w:1 0x5E /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R
|
||||
VMAXPS ; Vfv{K}{z},Hfv,Wfv|B32{sae} ; ; evex m:1 p:0 l:x w:0 0x5F /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R
|
||||
VMAXPD ; Vfv{K}{z},Hfv,Wfv|B64{sae} ; ; evex m:1 p:1 l:x w:1 0x5F /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R
|
||||
VMAXSS ; Vdq{K}{z},Hdq,Wss{sae} ; ; evex m:1 p:2 l:i w:0 0x5F /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R
|
||||
VMAXSD ; Vdq{K}{z},Hdq,Wsd{sae} ; ; evex m:1 p:3 l:i w:1 0x5F /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R
|
||||
VADDPS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:1 p:0 l:x w:0 0x58 /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VADDPD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:1 p:1 l:x w:1 0x58 /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VADDSS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:1 p:2 l:i w:0 0x58 /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VADDSD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:1 p:3 l:i w:1 0x58 /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VMULPS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:1 p:0 l:x w:0 0x59 /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VMULPD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:1 p:1 l:x w:1 0x59 /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VMULSS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:1 p:2 l:i w:0 0x59 /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VMULSD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:1 p:3 l:i w:1 0x59 /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VCVTPS2PD ; Vfv{K}{z},Whv|B32{sae} ; ; evex m:1 p:0 l:x w:0 0x5A /r ; s:AVX512F, t:CONVERT, l:hv, e:E3, w:W|R|R, x:IE|DE
|
||||
VCVTPD2PS ; Vhv{K}{z},Wfv|B64{er} ; ; evex m:1 p:1 l:x w:1 0x5A /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R, x:IE|OE|UE|PE|DE
|
||||
VCVTSS2SD ; Vdq{K}{z},Hdq,Wss{sae} ; ; evex m:1 p:2 l:i w:0 0x5A /r ; s:AVX512F, t:CONVERT, l:t1s, e:E3, w:W|R|R|R, x:IE|DE
|
||||
VCVTSD2SS ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:1 p:3 l:i w:1 0x5A /r ; s:AVX512F, t:CONVERT, l:t1s, e:E3, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VCVTDQ2PS ; Vfv{K}{z},Wfv|B32{er} ; ; evex m:1 p:0 l:x w:0 0x5B /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R, x:PE
|
||||
VCVTQQ2PS ; Vhv{K}{z},Wfv|B64{er} ; ; evex m:1 p:0 l:x w:1 0x5B /r ; s:AVX512DQ, t:CONVERT, l:fv, e:E2, w:W|R|R, x:PE
|
||||
VCVTPS2DQ ; Vfv{K}{z},Wfv|B32{er} ; ; evex m:1 p:1 l:x w:0 0x5B /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R, x:IE|PE
|
||||
VCVTTPS2DQ ; Vfv{K}{z},Wfv|B32{sae} ; ; evex m:1 p:2 l:x w:0 0x5B /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R, x:IE|PE
|
||||
VSUBPS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:1 p:0 l:x w:0 0x5C /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VSUBPD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:1 p:1 l:x w:1 0x5C /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VSUBSS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:1 p:2 l:i w:0 0x5C /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VSUBSD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:1 p:3 l:i w:1 0x5C /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VMINPS ; Vfv{K}{z},Hfv,Wfv|B32{sae} ; ; evex m:1 p:0 l:x w:0 0x5D /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R, x:IE|DE
|
||||
VMINPD ; Vfv{K}{z},Hfv,Wfv|B64{sae} ; ; evex m:1 p:1 l:x w:1 0x5D /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R, x:IE|DE
|
||||
VMINSS ; Vdq{K}{z},Hdq,Wss{sae} ; ; evex m:1 p:2 l:i w:0 0x5D /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R, x:IE|DE
|
||||
VMINSD ; Vdq{K}{z},Hdq,Wsd{sae} ; ; evex m:1 p:3 l:i w:1 0x5D /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R, x:IE|DE
|
||||
VDIVPS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:1 p:0 l:x w:0 0x5E /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R, x:IE|OE|UE|PE|DE|ZE
|
||||
VDIVPD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:1 p:1 l:x w:1 0x5E /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R, x:IE|OE|UE|PE|DE|ZE
|
||||
VDIVSS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:1 p:2 l:i w:0 0x5E /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R, x:IE|OE|UE|PE|DE|ZE
|
||||
VDIVSD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:1 p:3 l:i w:1 0x5E /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R, x:IE|OE|UE|PE|DE|ZE
|
||||
VMAXPS ; Vfv{K}{z},Hfv,Wfv|B32{sae} ; ; evex m:1 p:0 l:x w:0 0x5F /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R, x:IE|DE
|
||||
VMAXPD ; Vfv{K}{z},Hfv,Wfv|B64{sae} ; ; evex m:1 p:1 l:x w:1 0x5F /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R, x:IE|DE
|
||||
VMAXSS ; Vdq{K}{z},Hdq,Wss{sae} ; ; evex m:1 p:2 l:i w:0 0x5F /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R, x:IE|DE
|
||||
VMAXSD ; Vdq{K}{z},Hdq,Wsd{sae} ; ; evex m:1 p:3 l:i w:1 0x5F /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R, x:IE|DE
|
||||
|
||||
# 0x60 - 0x6F
|
||||
VPUNPCKLBW ; Vfv{K}{z},Hfv,Wfv ; ; evex m:1 p:1 l:x w:x 0x60 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:W|R|R|R
|
||||
@ -149,32 +149,30 @@ VPSRLDQ ; Hfv,Wfv,Ib ; ; evex m:1 p:1 l:x w:i
|
||||
VPSLLQ ; Hfv{K}{z},Wfv|B64,Ib ; ; evex m:1 p:1 l:x w:1 0x73 /6 ib ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R
|
||||
VPSLLDQ ; Hfv,Wfv,Ib ; ; evex m:1 p:1 l:x w:i 0x73 /7 ib ; s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:W|R|R
|
||||
VPCMPEQB ; rKq{K},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0x74 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R
|
||||
VCVTNEPH2BF8 ; Vhv{K}{z},Wfv|B16 ; ; evex m:1 p:2 l:x w:0 0x74 /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R
|
||||
VCVTNE2PH2BF8 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:1 p:3 l:x w:0 0x74 /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R|R
|
||||
VPCMPEQW ; rKq{K},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0x75 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R
|
||||
VPCMPEQD ; rKq{K},Hfv,Wfv|B32 ; ; evex m:1 p:1 l:x w:i 0x76 /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R
|
||||
VCVTTPS2UDQ ; Vfv{K}{z},Wfv|B32{sae} ; ; evex m:1 p:0 l:x w:0 0x78 /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R
|
||||
VCVTTPD2UDQ ; Vhv{K}{z},Wfv|B64{sae} ; ; evex m:1 p:0 l:x w:1 0x78 /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R
|
||||
VCVTTPS2UQQ ; Vfv{K}{z},Whv|B32{sae} ; ; evex m:1 p:1 l:x w:0 0x78 /r ; s:AVX512DQ, t:CONVERT, l:hv, e:E3, w:W|R|R
|
||||
VCVTTPD2UQQ ; Vfv{K}{z},Wfv|B64{sae} ; ; evex m:1 p:1 l:x w:1 0x78 /r ; s:AVX512DQ, t:CONVERT, l:fv, e:E2, w:W|R|R
|
||||
VCVTTSS2USI ; Gy,Wss{sae} ; ; evex m:1 p:2 l:i w:x 0x78 /r ; s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R, a:IWO64
|
||||
VCVTTSD2USI ; Gy,Wsd{sae} ; ; evex m:1 p:3 l:i w:x 0x78 /r ; s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R, a:IWO64
|
||||
VCVTPS2UDQ ; Vfv{K}{z},Wfv|B32{er} ; ; evex m:1 p:0 l:x w:0 0x79 /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R
|
||||
VCVTPD2UDQ ; Vhv{K}{z},Wfv|B64{er} ; ; evex m:1 p:0 l:x w:1 0x79 /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R
|
||||
VCVTPS2UQQ ; Vfv{K}{z},Whv|B32{er} ; ; evex m:1 p:1 l:x w:0 0x79 /r ; s:AVX512DQ, t:CONVERT, l:hv, e:E3, w:W|R|R
|
||||
VCVTPD2UQQ ; Vfv{K}{z},Wfv|B64{er} ; ; evex m:1 p:1 l:x w:1 0x79 /r ; s:AVX512DQ, t:CONVERT, l:fv, e:E2, w:W|R|R
|
||||
VCVTSS2USI ; Gy,Wss{er} ; ; evex m:1 p:2 l:i w:x 0x79 /r ; s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R, a:IWO64
|
||||
VCVTSD2USI ; Gy,Wsd{er} ; ; evex m:1 p:3 l:i w:x 0x79 /r ; s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R, a:IWO64
|
||||
VCVTTPS2QQ ; Vfv{K}{z},Whv|B32{sae} ; ; evex m:1 p:1 l:x w:0 0x7A /r ; s:AVX512DQ, t:CONVERT, l:hv, e:E3, w:W|R|R
|
||||
VCVTTPD2QQ ; Vfv{K}{z},Wfv|B64{sae} ; ; evex m:1 p:1 l:x w:1 0x7A /r ; s:AVX512DQ, t:CONVERT, l:fv, e:E2, w:W|R|R
|
||||
VCVTTPS2UDQ ; Vfv{K}{z},Wfv|B32{sae} ; ; evex m:1 p:0 l:x w:0 0x78 /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R, x:IE|PE
|
||||
VCVTTPD2UDQ ; Vhv{K}{z},Wfv|B64{sae} ; ; evex m:1 p:0 l:x w:1 0x78 /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R, x:IE|PE
|
||||
VCVTTPS2UQQ ; Vfv{K}{z},Whv|B32{sae} ; ; evex m:1 p:1 l:x w:0 0x78 /r ; s:AVX512DQ, t:CONVERT, l:hv, e:E3, w:W|R|R, x:IE|PE
|
||||
VCVTTPD2UQQ ; Vfv{K}{z},Wfv|B64{sae} ; ; evex m:1 p:1 l:x w:1 0x78 /r ; s:AVX512DQ, t:CONVERT, l:fv, e:E2, w:W|R|R, x:IE|PE
|
||||
VCVTTSS2USI ; Gy,Wss{sae} ; ; evex m:1 p:2 l:i w:x 0x78 /r ; s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R, a:IWO64, x:IE|PE
|
||||
VCVTTSD2USI ; Gy,Wsd{sae} ; ; evex m:1 p:3 l:i w:x 0x78 /r ; s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R, a:IWO64, x:IE|PE
|
||||
VCVTPS2UDQ ; Vfv{K}{z},Wfv|B32{er} ; ; evex m:1 p:0 l:x w:0 0x79 /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R, x:IE|PE
|
||||
VCVTPD2UDQ ; Vhv{K}{z},Wfv|B64{er} ; ; evex m:1 p:0 l:x w:1 0x79 /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R, x:IE|PE
|
||||
VCVTPS2UQQ ; Vfv{K}{z},Whv|B32{er} ; ; evex m:1 p:1 l:x w:0 0x79 /r ; s:AVX512DQ, t:CONVERT, l:hv, e:E3, w:W|R|R, x:IE|PE
|
||||
VCVTPD2UQQ ; Vfv{K}{z},Wfv|B64{er} ; ; evex m:1 p:1 l:x w:1 0x79 /r ; s:AVX512DQ, t:CONVERT, l:fv, e:E2, w:W|R|R, x:IE|PE
|
||||
VCVTSS2USI ; Gy,Wss{er} ; ; evex m:1 p:2 l:i w:x 0x79 /r ; s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R, a:IWO64, x:IE|PE
|
||||
VCVTSD2USI ; Gy,Wsd{er} ; ; evex m:1 p:3 l:i w:x 0x79 /r ; s:AVX512F, t:CONVERT, l:t1f, e:E3, w:W|R, a:IWO64, x:IE|PE
|
||||
VCVTTPS2QQ ; Vfv{K}{z},Whv|B32{sae} ; ; evex m:1 p:1 l:x w:0 0x7A /r ; s:AVX512DQ, t:CONVERT, l:hv, e:E3, w:W|R|R, x:IE|PE
|
||||
VCVTTPD2QQ ; Vfv{K}{z},Wfv|B64{sae} ; ; evex m:1 p:1 l:x w:1 0x7A /r ; s:AVX512DQ, t:CONVERT, l:fv, e:E2, w:W|R|R, x:IE|PE
|
||||
VCVTUDQ2PD ; Vfv{K}{z},Whv|B32 ; ; evex m:1 p:2 l:x w:0 0x7A /r ; s:AVX512F, t:CONVERT, l:hv, e:E5, w:W|R|R, a:IER
|
||||
VCVTUQQ2PD ; Vfv{K}{z},Wfv|B64{er} ; ; evex m:1 p:2 l:x w:1 0x7A /r ; s:AVX512DQ, t:CONVERT, l:fv, e:E2, w:W|R|R
|
||||
VCVTUDQ2PS ; Vfv{K}{z},Wfv|B32{er} ; ; evex m:1 p:3 l:x w:0 0x7A /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R
|
||||
VCVTUQQ2PS ; Vhv{K}{z},Wfv|B64{er} ; ; evex m:1 p:3 l:x w:1 0x7A /r ; s:AVX512DQ, t:CONVERT, l:fv, e:E2, w:W|R|R
|
||||
VCVTPS2QQ ; Vfv{K}{z},Whv|B32{er} ; ; evex m:1 p:1 l:x w:0 0x7B /r ; s:AVX512DQ, t:CONVERT, l:hv, e:E3, w:W|R|R
|
||||
VCVTPD2QQ ; Vfv{K}{z},Wfv|B64{er} ; ; evex m:1 p:1 l:x w:1 0x7B /r ; s:AVX512DQ, t:CONVERT, l:fv, e:E2, w:W|R|R
|
||||
VCVTUSI2SS ; Vss,Hss{er},Ey ; ; evex m:1 p:2 l:i w:x 0x7B /r ; s:AVX512F, t:CONVERT, l:t1s, e:E3, w:W|R|R, a:IWO64
|
||||
VCVTUSI2SD ; Vdq,Hdq,Ey ; ; evex m:1 p:3 l:i w:0 0x7B /r ; s:AVX512F, t:CONVERT, l:t1s, e:E10NF, w:W|R|R, a:IER|IWO64
|
||||
VCVTUQQ2PD ; Vfv{K}{z},Wfv|B64{er} ; ; evex m:1 p:2 l:x w:1 0x7A /r ; s:AVX512DQ, t:CONVERT, l:fv, e:E2, w:W|R|R, x:PE
|
||||
VCVTUDQ2PS ; Vfv{K}{z},Wfv|B32{er} ; ; evex m:1 p:3 l:x w:0 0x7A /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R, x:PE
|
||||
VCVTUQQ2PS ; Vhv{K}{z},Wfv|B64{er} ; ; evex m:1 p:3 l:x w:1 0x7A /r ; s:AVX512DQ, t:CONVERT, l:fv, e:E2, w:W|R|R, x:PE
|
||||
VCVTPS2QQ ; Vfv{K}{z},Whv|B32{er} ; ; evex m:1 p:1 l:x w:0 0x7B /r ; s:AVX512DQ, t:CONVERT, l:hv, e:E3, w:W|R|R, x:IE|PE
|
||||
VCVTPD2QQ ; Vfv{K}{z},Wfv|B64{er} ; ; evex m:1 p:1 l:x w:1 0x7B /r ; s:AVX512DQ, t:CONVERT, l:fv, e:E2, w:W|R|R, x:IE|PE
|
||||
VCVTUSI2SS ; Vss,Hss{er},Ey ; ; evex m:1 p:2 l:i w:x 0x7B /r ; s:AVX512F, t:CONVERT, l:t1s, e:E3, w:W|R|R, a:IWO64, x:PE
|
||||
VCVTUSI2SD ; Vdq,Hdq,Ey ; ; evex m:1 p:3 l:i w:0 0x7B /r ; s:AVX512F, t:CONVERT, l:t1s, e:E10NF, w:W|R|R, a:IER|IWO64, x:PE
|
||||
VCVTUSI2SD ; Vdq,Hdq{er},Ey ; ; evex m:1 p:3 l:i w:1 0x7B /r ; s:AVX512F, t:CONVERT, l:t1s, e:E3, w:W|R|R, a:IWO64
|
||||
VMOVD ; Ey,Vdq ; ; evex m:1 p:1 l:0 w:0 0x7E /r ; s:AVX512F, t:DATAXFER, l:t1s, e:E9NF, w:W|R, a:IWO64
|
||||
VMOVQ ; Ey,Vdq ; ; evex m:1 p:1 l:0 w:1 0x7E /r ; s:AVX512F, t:DATAXFER, l:t1s, e:E9NF, w:W|R, a:IWO64
|
||||
@ -196,10 +194,10 @@ VMOVDQU16 ; Wfv{K}{z},Vfv ; ; evex m:1 p:3 l:x w:1
|
||||
# 0xB0 - 0xBF
|
||||
|
||||
# 0xC0 - 0xCF
|
||||
VCMPPS ; rKq{K},Hfv,Wfv|B32{sae},Ib ; ; evex m:1 p:0 l:x w:0 0xC2 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R|R
|
||||
VCMPPD ; rKq{K},Hfv,Wfv|B64{sae},Ib ; ; evex m:1 p:1 l:x w:1 0xC2 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R|R
|
||||
VCMPSS ; rKq{K},Hdq,Wss{sae},Ib ; ; evex m:1 p:2 l:x w:0 0xC2 /r ib ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R
|
||||
VCMPSD ; rKq{K},Hdq,Wsd{sae},Ib ; ; evex m:1 p:3 l:x w:1 0xC2 /r ib ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R
|
||||
VCMPPS ; rKq{K},Hfv,Wfv|B32{sae},Ib ; ; evex m:1 p:0 l:x w:0 0xC2 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R|R, x:IE|DE
|
||||
VCMPPD ; rKq{K},Hfv,Wfv|B64{sae},Ib ; ; evex m:1 p:1 l:x w:1 0xC2 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R|R, x:IE|DE
|
||||
VCMPSS ; rKq{K},Hdq,Wss{sae},Ib ; ; evex m:1 p:2 l:x w:0 0xC2 /r ib ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R, x:IE|DE
|
||||
VCMPSD ; rKq{K},Hdq,Wsd{sae},Ib ; ; evex m:1 p:3 l:x w:1 0xC2 /r ib ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R, x:IE|DE
|
||||
VPINSRW ; Vdq,Hdq,Mw,Ib ; ; evex m:1 p:1 l:0 w:i 0xC4 /r:mem ib ; s:AVX512BW, t:AVX512, l:t1s16, e:E9NF, w:W|R|R|R
|
||||
VPINSRW ; Vdq,Hdq,Rv,Ib ; ; evex m:1 p:1 l:0 w:i 0xC4 /r:reg ib ; s:AVX512BW, t:AVX512, l:t1s16, e:E9NF, w:W|R|R|R
|
||||
VPEXTRW ; Gy,Udq,Ib ; ; evex m:1 p:1 l:0 w:i 0xC5 /r:reg ib ; s:AVX512BW, t:AVX512, l:t1s, e:E9NF, w:W|R|R
|
||||
@ -233,10 +231,10 @@ VPSRAQ ; Vfv{K}{z},Hfv,Wdq ; ; evex m:1 p:1 l:x w:1
|
||||
VPAVGW ; Vfv{K}{z},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0xE3 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R
|
||||
VPMULHUW ; Vfv{K}{z},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0xE4 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R
|
||||
VPMULHW ; Vfv{K}{z},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0xE5 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R
|
||||
VCVTTPD2DQ ; Vhv{K}{z},Wfv|B64{sae} ; ; evex m:1 p:1 l:x w:1 0xE6 /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R
|
||||
VCVTTPD2DQ ; Vhv{K}{z},Wfv|B64{sae} ; ; evex m:1 p:1 l:x w:1 0xE6 /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R, x:IE|PE
|
||||
VCVTDQ2PD ; Vfv{K}{z},Whv|B32 ; ; evex m:1 p:2 l:x w:0 0xE6 /r ; s:AVX512F, t:CONVERT, l:hv, e:E5, w:W|R|R, a:IER
|
||||
VCVTQQ2PD ; Vfv{K}{z},Wfv|B64{er} ; ; evex m:1 p:2 l:x w:1 0xE6 /r ; s:AVX512DQ, t:CONVERT, l:fv, e:E2, w:W|R|R
|
||||
VCVTPD2DQ ; Vhv{K}{z},Wfv|B64{er} ; ; evex m:1 p:3 l:x w:1 0xE6 /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R
|
||||
VCVTQQ2PD ; Vfv{K}{z},Wfv|B64{er} ; ; evex m:1 p:2 l:x w:1 0xE6 /r ; s:AVX512DQ, t:CONVERT, l:fv, e:E2, w:W|R|R, x:PE
|
||||
VCVTPD2DQ ; Vhv{K}{z},Wfv|B64{er} ; ; evex m:1 p:3 l:x w:1 0xE6 /r ; s:AVX512F, t:CONVERT, l:fv, e:E2, w:W|R|R, x:IE|PE
|
||||
VMOVNTDQ ; Mfv,Vfv ; ; evex m:1 p:1 l:x w:0 0xE7 /r:mem ; s:AVX512F, t:DATAXFER, l:fvm, e:E1NF, w:W|R
|
||||
VPSUBSB ; Vfv{K}{z},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0xE8 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R
|
||||
VPSUBSW ; Vfv{K}{z},Hfv,Wfv ; ; evex m:1 p:1 l:x w:i 0xE9 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R
|
||||
|
||||
@ -14,7 +14,7 @@ VPERMILPD ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:2 p:1 l:x w:1
|
||||
VPSRLVW ; Vfv{K}{z},Hfv,Wfv ; ; evex m:2 p:1 l:x w:1 0x10 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R
|
||||
VPSRAVW ; Vfv{K}{z},Hfv,Wfv ; ; evex m:2 p:1 l:x w:1 0x11 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4, w:W|R|R|R
|
||||
VPSLLVW ; Vfv{K}{z},Hfv,Wfv ; ; evex m:2 p:1 l:x w:1 0x12 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R
|
||||
VCVTPH2PS ; Vfv{K}{z},Whv{sae} ; ; evex m:2 p:1 l:x w:0 0x13 /r ; s:AVX512F, t:CONVERT, l:hvm, e:E11, w:W|R|R
|
||||
VCVTPH2PS ; Vfv{K}{z},Whv{sae} ; ; evex m:2 p:1 l:x w:0 0x13 /r ; s:AVX512F, t:CONVERT, l:hvm, e:E11, w:W|R|R, x:IE
|
||||
VPRORVD ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:1 l:x w:0 0x14 /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R
|
||||
VPRORVQ ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:2 p:1 l:x w:1 0x14 /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R
|
||||
VPROLVD ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:1 l:x w:0 0x15 /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R
|
||||
@ -66,10 +66,10 @@ VPMULDQ ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:2 p:1 l:x w:1
|
||||
VPCMPEQQ ; rKq{K},Hfv,Wfv|B64 ; ; evex m:2 p:1 l:x w:1 0x29 /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R
|
||||
VMOVNTDQA ; Vfv,Mfv ; ; evex m:2 p:1 l:x w:0 0x2A /r:mem ; s:AVX512F, t:DATAXFER, l:fvm, e:E1NF, w:W|R
|
||||
VPACKUSDW ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:1 l:x w:0 0x2B /r ; s:AVX512BW, t:AVX512, l:fv, e:E4NF, w:W|R|R|R
|
||||
VSCALEFPS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0x2C /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R
|
||||
VSCALEFPD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0x2C /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R
|
||||
VSCALEFSS ; Vss{K}{z},Hss,Wss{er} ; ; evex m:2 p:1 l:i w:0 0x2D /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R
|
||||
VSCALEFSD ; Vsd{K}{z},Hsd,Wsd{er} ; ; evex m:2 p:1 l:i w:1 0x2D /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R
|
||||
VSCALEFPS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0x2C /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VSCALEFPD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0x2C /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VSCALEFSS ; Vss{K}{z},Hss,Wss{er} ; ; evex m:2 p:1 l:i w:0 0x2D /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VSCALEFSD ; Vsd{K}{z},Hsd,Wsd{er} ; ; evex m:2 p:1 l:i w:1 0x2D /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VPMOVM2B ; Vfv,mKq ; ; evex m:2 p:2 l:x w:0 0x28 /r:reg ; s:AVX512BW, t:DATAXFER, e:E7NM, w:W|R
|
||||
VPMOVM2W ; Vfv,mKq ; ; evex m:2 p:2 l:x w:1 0x28 /r:reg ; s:AVX512BW, t:DATAXFER, e:E7NM, w:W|R
|
||||
VPMOVB2M ; rKq,Ufv ; ; evex m:2 p:2 l:x w:0 0x29 /r:reg ; s:AVX512BW, t:DATAXFER, e:E7NM, w:W|R
|
||||
@ -113,10 +113,10 @@ VPBROADCASTMW2D ; Vfv,mKq ; ; evex m:2 p:2 l:x w:0
|
||||
# 0x40 - 0x4F
|
||||
VPMULLD ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:1 l:x w:0 0x40 /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R
|
||||
VPMULLQ ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:2 p:1 l:x w:1 0x40 /r ; s:AVX512DQ, t:AVX512, l:fv, e:E4, w:W|R|R|R
|
||||
VGETEXPPS ; Vfv{K}{z},Wfv|B32{sae} ; ; evex m:2 p:1 l:x w:0 0x42 /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R
|
||||
VGETEXPPD ; Vfv{K}{z},Wfv|B64{sae} ; ; evex m:2 p:1 l:x w:1 0x42 /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R
|
||||
VGETEXPSS ; Vdq{K}{z},Hdq,Wss{sae} ; ; evex m:2 p:1 l:x w:0 0x43 /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R
|
||||
VGETEXPSD ; Vdq{K}{z},Hdq,Wsd{sae} ; ; evex m:2 p:1 l:x w:1 0x43 /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R
|
||||
VGETEXPPS ; Vfv{K}{z},Wfv|B32{sae} ; ; evex m:2 p:1 l:x w:0 0x42 /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R, x:IE|DE
|
||||
VGETEXPPD ; Vfv{K}{z},Wfv|B64{sae} ; ; evex m:2 p:1 l:x w:1 0x42 /r ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R, x:IE|DE
|
||||
VGETEXPSS ; Vdq{K}{z},Hdq,Wss{sae} ; ; evex m:2 p:1 l:x w:0 0x43 /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R, x:IE|DE
|
||||
VGETEXPSD ; Vdq{K}{z},Hdq,Wsd{sae} ; ; evex m:2 p:1 l:x w:1 0x43 /r ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R, x:IE|DE
|
||||
VPLZCNTD ; Vfv{K}{z},Wfv|B32 ; ; evex m:2 p:1 l:x w:0 0x44 /r ; s:AVX512CD, t:CONFLICT, l:fv, e:E4, w:W|R|R
|
||||
VPLZCNTQ ; Vfv{K}{z},Wfv|B64 ; ; evex m:2 p:1 l:x w:1 0x44 /r ; s:AVX512CD, t:CONFLICT, l:fv, e:E4, w:W|R|R
|
||||
VPSRLVD ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:1 l:x w:0 0x45 /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R
|
||||
@ -125,6 +125,8 @@ VPSRAVD ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:1 l:x w:0
|
||||
VPSRAVQ ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:2 p:1 l:x w:1 0x46 /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R
|
||||
VPSLLVD ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:1 l:x w:0 0x47 /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R
|
||||
VPSLLVQ ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:2 p:1 l:x w:1 0x47 /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R
|
||||
TILEMOVROW ; Voq,mTt,Bd ; ; evex m:2 p:1 l:2 w:0 0x4A /r:reg ; s:AMXAVX512, t:AMX, e:AMX_EVEX_E8, w:W|R|R, m:NOTSX
|
||||
TCVTROWD2PS ; Voq,mTt,Bd ; ; evex m:2 p:2 l:2 w:0 0x4A /r:reg ; s:AMXAVX512, t:AMX, e:AMX_EVEX_E8, w:W|R|R, m:NOTSX
|
||||
VRCP14PS ; Vfv{K}{z},Wfv|B32 ; ; evex m:2 p:1 l:x w:0 0x4C /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R
|
||||
VRCP14PD ; Vfv{K}{z},Wfv|B64 ; ; evex m:2 p:1 l:x w:1 0x4C /r ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R
|
||||
VRCP14SS ; Vdq{K}{z},Hdq,Wss ; ; evex m:2 p:1 l:x w:0 0x4D /r ; s:AVX512F, t:AVX512, l:t1s, e:E10, w:W|R|R|R
|
||||
@ -172,21 +174,28 @@ VBLENDMPS ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:1 l:x w:0
|
||||
VBLENDMPD ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:2 p:1 l:x w:1 0x65 /r ; s:AVX512F, t:BLEND, l:fv, e:E4, w:W|R|R|R
|
||||
VPBLENDMB ; Vfv{K}{z},Hfv,Wfv ; ; evex m:2 p:1 l:x w:0 0x66 /r ; s:AVX512BW, t:BLEND, l:fvm, e:E4, w:W|R|R|R
|
||||
VPBLENDMW ; Vfv{K}{z},Hfv,Wfv ; ; evex m:2 p:1 l:x w:1 0x66 /r ; s:AVX512BW, t:BLEND, l:fvm, e:E4, w:W|R|R|R
|
||||
VCVT2PS2PHX ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0x67 /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R|R
|
||||
VCVT2PS2PHX ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0x67 /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
|
||||
VP2INTERSECTD ; rKq+1,Hfv,Wfv|B32 ; ; evex m:2 p:3 l:x w:0 0x68 /r ; s:AVX512VP2INTERSECT, t:AVX512VP2INTERSECT, l:fv, e:E4NF, w:W|R|R
|
||||
VP2INTERSECTQ ; rKq+1,Hfv,Wfv|B64 ; ; evex m:2 p:3 l:x w:1 0x68 /r ; s:AVX512VP2INTERSECT, t:AVX512VP2INTERSECT, l:fv, e:E4NF, w:W|R|R
|
||||
|
||||
TCVTROWPS2PHH ; Voq,mTt,Bd ; ; evex m:2 p:0 l:2 w:0 0x6D /r:reg ; s:AMXAVX512, t:AMX, e:AMX_EVEX_E8, w:W|R|R, m:NOTSX
|
||||
TCVTROWPS2PHL ; Voq,mTt,Bd ; ; evex m:2 p:1 l:2 w:0 0x6D /r:reg ; s:AMXAVX512, t:AMX, e:AMX_EVEX_E8, w:W|R|R, m:NOTSX
|
||||
TCVTROWPS2PBF16L ; Voq,mTt,Bd ; ; evex m:2 p:2 l:2 w:0 0x6D /r:reg ; s:AMXAVX512, t:AMX, e:AMX_EVEX_E8, w:W|R|R, m:NOTSX
|
||||
TCVTROWPS2PBF16H ; Voq,mTt,Bd ; ; evex m:2 p:3 l:2 w:0 0x6D /r:reg ; s:AMXAVX512, t:AMX, e:AMX_EVEX_E8, w:W|R|R, m:NOTSX
|
||||
|
||||
# 0x70 - 0x7F
|
||||
VPSHLDVW ; Vfv{K}{z},Hfv,Wfv ; ; evex m:2 p:1 l:x w:1 0x70 /r ; s:AVX512VBMI2, t:AVX512VBMI, l:fvm, e:E4, w:RW|R|R|R
|
||||
VPSHLDVD ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:1 l:x w:0 0x71 /r ; s:AVX512VBMI2, t:AVX512VBMI, l:fv, e:E4, w:RW|R|R|R
|
||||
VPSHLDVQ ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:2 p:1 l:x w:1 0x71 /r ; s:AVX512VBMI2, t:AVX512VBMI, l:fv, e:E4, w:RW|R|R|R
|
||||
VPSHRDVW ; Vfv{K}{z},Hfv,Wfv ; ; evex m:2 p:1 l:x w:1 0x72 /r ; s:AVX512VBMI2, t:AVX512VBMI, l:fvm, e:E4, w:RW|R|R|R
|
||||
VCVTNEPS2BF16 ; Vhv{K}{z},Wfv|B32 ; ; evex m:2 p:2 l:x w:0 0x72 /r ; s:AVX512BF16, t:AVX512BF16, l:fv, e:E4, w:W|R|R
|
||||
VCVTNE2PS2BF16 ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:3 l:x w:0 0x72 /r ; s:AVX512BF16, t:AVX512BF16, l:fv, e:E4NF, w:W|R|R|R
|
||||
VCVTNEPS2BF16 ; Vhv{K}{z},Wfv|B32 ; ; evex m:2 p:2 l:x w:0 0x72 /r ; s:AVX512BF16, t:AVX512BF16, l:fv, e:E4, w:W|R|R, x:IE|OE|UE|PE|DE
|
||||
VCVTNE2PS2BF16 ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:3 l:x w:0 0x72 /r ; s:AVX512BF16, t:AVX512BF16, l:fv, e:E4NF, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VPSHRDVD ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:1 l:x w:0 0x73 /r ; s:AVX512VBMI2, t:AVX512VBMI, l:fv, e:E4, w:RW|R|R|R
|
||||
VPSHRDVQ ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:2 p:1 l:x w:1 0x73 /r ; s:AVX512VBMI2, t:AVX512VBMI, l:fv, e:E4, w:RW|R|R|R
|
||||
VCVTBIASPH2BF8 ; Vhv{K}{z},Hfv,Wfv|B16 ; ; evex m:2 p:0 l:x w:0 0x74 /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R|R
|
||||
VCVTNEPH2BF8 ; Vhv{K}{z},Wfv|B16 ; ; evex m:2 p:2 l:x w:0 0x74 /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R, x:IE|OE|UE|PE|DE
|
||||
VCVTNE2PH2BF8 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:2 p:3 l:x w:0 0x74 /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
|
||||
VPERMI2B ; Vfv{K}{z},Hfv,Wfv ; ; evex m:2 p:1 l:x w:0 0x75 /r ; s:AVX512VBMI, t:AVX512VBMI, l:fvm, e:E4NFnb, w:RW|R|R|R
|
||||
VPERMI2W ; Vfv{K}{z},Hfv,Wfv ; ; evex m:2 p:1 l:x w:1 0x75 /r ; s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:RW|R|R|R
|
||||
@ -231,85 +240,85 @@ VGATHERDPD ; Vfv{K},Mvm32h ; ; evex m:2 p:1 l:x w:1
|
||||
VGATHERQPS ; Vhv{K},Mvm64n ; ; evex m:2 p:1 l:x w:0 0x93 /r:mem vsib ; s:AVX512F, t:GATHER, a:MMASK, l:t1s, e:E12, w:W|R|RW
|
||||
VGATHERQPD ; Vfv{K},Mvm64n ; ; evex m:2 p:1 l:x w:1 0x93 /r:mem vsib ; s:AVX512F, t:GATHER, a:MMASK, l:t1s, e:E12, w:W|R|RW
|
||||
|
||||
VFMADDSUB132PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0x96 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R
|
||||
VFMADDSUB132PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0x96 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R
|
||||
VFMSUBADD132PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0x97 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R
|
||||
VFMSUBADD132PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0x97 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R
|
||||
VFMADD132PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0x98 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R
|
||||
VFMADD132PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0x98 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R
|
||||
VFMADD132SS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:2 p:1 l:i w:0 0x99 /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R
|
||||
VFMADD132SD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:2 p:1 l:i w:1 0x99 /r ; s:AVX512F, t:VFMA, l:t1s, e:E2, w:RW|R|R|R
|
||||
VFMSUB132PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0x9A /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R
|
||||
VFMSUB132PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0x9A /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R
|
||||
V4FMADDPS ; Voq{K}{z},Hoq+3,Mdq ; ; evex m:2 p:3 l:2 w:0 0x9A /r:mem ; s:AVX5124FMAPS, t:VFMAPS, l:t1_4x, e:E2, w:RW|R|R|R
|
||||
VFMSUB132SS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:2 p:1 l:i w:0 0x9B /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R
|
||||
VFMSUB132SD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:2 p:1 l:i w:1 0x9B /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R
|
||||
V4FMADDSS ; Vdq{K}{z},Hdq+3,Mdq ; ; evex m:2 p:3 l:i w:0 0x9B /r:mem ; s:AVX5124FMAPS, t:VFMAPS, e:E3, l:t1_4x, w:RW|R|R|R
|
||||
VFNMADD132PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0x9C /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R
|
||||
VFNMADD132PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0x9C /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R
|
||||
VFNMADD132SS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:2 p:1 l:i w:0 0x9D /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R
|
||||
VFNMADD132SD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:2 p:1 l:i w:1 0x9D /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R
|
||||
VFNMSUB132PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0x9E /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R
|
||||
VFNMSUB132PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0x9E /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R
|
||||
VFNMSUB132SS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:2 p:1 l:i w:0 0x9F /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R
|
||||
VFNMSUB132SD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:2 p:1 l:i w:1 0x9F /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R
|
||||
VFMADDSUB132PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0x96 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFMADDSUB132PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0x96 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFMSUBADD132PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0x97 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFMSUBADD132PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0x97 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFMADD132PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0x98 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFMADD132PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0x98 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFMADD132SS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:2 p:1 l:i w:0 0x99 /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFMADD132SD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:2 p:1 l:i w:1 0x99 /r ; s:AVX512F, t:VFMA, l:t1s, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFMSUB132PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0x9A /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFMSUB132PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0x9A /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
V4FMADDPS ; Voq{K}{z},Hoq+3,Mdq ; ; evex m:2 p:3 l:2 w:0 0x9A /r:mem ; s:AVX5124FMAPS, t:VFMAPS, l:t1_4x, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFMSUB132SS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:2 p:1 l:i w:0 0x9B /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFMSUB132SD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:2 p:1 l:i w:1 0x9B /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
V4FMADDSS ; Vdq{K}{z},Hdq+3,Mdq ; ; evex m:2 p:3 l:i w:0 0x9B /r:mem ; s:AVX5124FMAPS, t:VFMAPS, e:E3, l:t1_4x, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFNMADD132PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0x9C /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFNMADD132PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0x9C /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFNMADD132SS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:2 p:1 l:i w:0 0x9D /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFNMADD132SD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:2 p:1 l:i w:1 0x9D /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFNMSUB132PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0x9E /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFNMSUB132PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0x9E /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFNMSUB132SS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:2 p:1 l:i w:0 0x9F /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFNMSUB132SD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:2 p:1 l:i w:1 0x9F /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
|
||||
# 0xA0 - 0xAF
|
||||
VPSCATTERDD ; Mvm32n{K},Vfv ; ; evex m:2 p:1 l:x w:0 0xA0 /r:mem vsib ; s:AVX512F, t:SCATTER, a:MMASK, l:t1s, e:E12, w:W|R|RW
|
||||
VPSCATTERDQ ; Mvm32h{K},Vfv ; ; evex m:2 p:1 l:x w:1 0xA0 /r:mem vsib ; s:AVX512F, t:SCATTER, a:MMASK, l:t1s, e:E12, w:W|R|RW
|
||||
VPSCATTERQD ; Mvm64n{K},Vhv ; ; evex m:2 p:1 l:x w:0 0xA1 /r:mem vsib ; s:AVX512F, t:SCATTER, a:MMASK, l:t1s, e:E12, w:W|R|RW
|
||||
VPSCATTERQQ ; Mvm64n{K},Vfv ; ; evex m:2 p:1 l:x w:1 0xA1 /r:mem vsib ; s:AVX512F, t:SCATTER, a:MMASK, l:t1s, e:E12, w:W|R|RW
|
||||
VSCATTERDPS ; Mvm32n{K},Vfv ; ; evex m:2 p:1 l:x w:0 0xA2 /r:mem vsib ; s:AVX512F, t:SCATTER, a:MMASK, l:t1s, e:E12, w:W|R|RW
|
||||
VSCATTERDPD ; Mvm32h{K},Vfv ; ; evex m:2 p:1 l:x w:1 0xA2 /r:mem vsib ; s:AVX512F, t:SCATTER, a:MMASK, l:t1s, e:E12, w:W|R|RW
|
||||
VSCATTERQPS ; Mvm64n{K},Vhv ; ; evex m:2 p:1 l:x w:0 0xA3 /r:mem vsib ; s:AVX512F, t:SCATTER, a:MMASK, l:t1s, e:E12, w:W|R|RW
|
||||
VSCATTERQPD ; Mvm64n{K},Vfv ; ; evex m:2 p:1 l:x w:1 0xA3 /r:mem vsib ; s:AVX512F, t:SCATTER, a:MMASK, l:t1s, e:E12, w:W|R|RW
|
||||
VSCATTERDPS ; Mvm32n{K},Vfv ; ; evex m:2 p:1 l:x w:0 0xA2 /r:mem vsib ; s:AVX512F, t:SCATTER, a:MMASK, l:t1s, e:E12, w:W|R|RW, x:IE|OE|UE|PE|DE
|
||||
VSCATTERDPD ; Mvm32h{K},Vfv ; ; evex m:2 p:1 l:x w:1 0xA2 /r:mem vsib ; s:AVX512F, t:SCATTER, a:MMASK, l:t1s, e:E12, w:W|R|RW, x:IE|OE|UE|PE|DE
|
||||
VSCATTERQPS ; Mvm64n{K},Vhv ; ; evex m:2 p:1 l:x w:0 0xA3 /r:mem vsib ; s:AVX512F, t:SCATTER, a:MMASK, l:t1s, e:E12, w:W|R|RW, x:IE|OE|UE|PE|DE
|
||||
VSCATTERQPD ; Mvm64n{K},Vfv ; ; evex m:2 p:1 l:x w:1 0xA3 /r:mem vsib ; s:AVX512F, t:SCATTER, a:MMASK, l:t1s, e:E12, w:W|R|RW, x:IE|OE|UE|PE|DE
|
||||
|
||||
VFMADDSUB213PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0xA6 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R
|
||||
VFMADDSUB213PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0xA6 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R
|
||||
VFMSUBADD213PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0xA7 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R
|
||||
VFMSUBADD213PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0xA7 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R
|
||||
VFMADD213PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0xA8 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R
|
||||
VFMADD213PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0xA8 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R
|
||||
VFMADD213SS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:2 p:1 l:i w:0 0xA9 /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R
|
||||
VFMADD213SD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:2 p:1 l:i w:1 0xA9 /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R
|
||||
VFMSUB213PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0xAA /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R
|
||||
VFMSUB213PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0xAA /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R
|
||||
V4FNMADDPS ; Voq{K}{z},Hoq+3,Mdq ; ; evex m:2 p:3 l:2 w:0 0xAA /r:mem ; s:AVX5124FMAPS, t:VFMAPS, l:t1_4x, e:E2, w:RW|R|R|R
|
||||
VFMSUB213SS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:2 p:1 l:i w:0 0xAB /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R
|
||||
VFMSUB213SD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:2 p:1 l:i w:1 0xAB /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R
|
||||
V4FNMADDSS ; Vdq{K}{z},Hdq+3,Mdq ; ; evex m:2 p:3 l:i w:0 0xAB /r:mem ; s:AVX5124FMAPS, t:VFMAPS, l:t1_4x, e:E2, w:RW|R|R|R
|
||||
VFNMADD213PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0xAC /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R
|
||||
VFNMADD213PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0xAC /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R
|
||||
VFNMADD213SS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:2 p:1 l:i w:0 0xAD /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R
|
||||
VFNMADD213SD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:2 p:1 l:i w:1 0xAD /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R
|
||||
VFNMSUB213PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0xAE /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R
|
||||
VFNMSUB213PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0xAE /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R
|
||||
VFNMSUB213SS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:2 p:1 l:i w:0 0xAF /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R
|
||||
VFNMSUB213SD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:2 p:1 l:i w:1 0xAF /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R
|
||||
VFMADDSUB213PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0xA6 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFMADDSUB213PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0xA6 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFMSUBADD213PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0xA7 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFMSUBADD213PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0xA7 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFMADD213PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0xA8 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFMADD213PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0xA8 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFMADD213SS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:2 p:1 l:i w:0 0xA9 /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFMADD213SD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:2 p:1 l:i w:1 0xA9 /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFMSUB213PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0xAA /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFMSUB213PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0xAA /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
V4FNMADDPS ; Voq{K}{z},Hoq+3,Mdq ; ; evex m:2 p:3 l:2 w:0 0xAA /r:mem ; s:AVX5124FMAPS, t:VFMAPS, l:t1_4x, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFMSUB213SS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:2 p:1 l:i w:0 0xAB /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFMSUB213SD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:2 p:1 l:i w:1 0xAB /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
V4FNMADDSS ; Vdq{K}{z},Hdq+3,Mdq ; ; evex m:2 p:3 l:i w:0 0xAB /r:mem ; s:AVX5124FMAPS, t:VFMAPS, l:t1_4x, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFNMADD213PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0xAC /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFNMADD213PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0xAC /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFNMADD213SS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:2 p:1 l:i w:0 0xAD /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFNMADD213SD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:2 p:1 l:i w:1 0xAD /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFNMSUB213PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0xAE /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFNMSUB213PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0xAE /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFNMSUB213SS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:2 p:1 l:i w:0 0xAF /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFNMSUB213SD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:2 p:1 l:i w:1 0xAF /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
|
||||
# 0xB0 - 0xBF
|
||||
VPMADD52LUQ ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:2 p:1 l:x w:1 0xB4 /r ; s:AVX512IFMA, t:IFMA, l:fv, e:E4, w:RW|R|R|R
|
||||
VPMADD52HUQ ; Vfv{K}{z},Hfv,Wfv|B64 ; ; evex m:2 p:1 l:x w:1 0xB5 /r ; s:AVX512IFMA, t:IFMA, l:fv, e:E4, w:RW|R|R|R
|
||||
VFMADDSUB231PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0xB6 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R
|
||||
VFMADDSUB231PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0xB6 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R
|
||||
VFMSUBADD231PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0xB7 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R
|
||||
VFMSUBADD231PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0xB7 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R
|
||||
VFMADD231PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0xB8 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R
|
||||
VFMADD231PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0xB8 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R
|
||||
VFMADD231SS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:2 p:1 l:i w:0 0xB9 /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R
|
||||
VFMADD231SD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:2 p:1 l:i w:1 0xB9 /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R
|
||||
VFMSUB231PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0xBA /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R
|
||||
VFMSUB231PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0xBA /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R
|
||||
VFMSUB231SS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:2 p:1 l:i w:0 0xBB /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R
|
||||
VFMSUB231SD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:2 p:1 l:i w:1 0xBB /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R
|
||||
VFNMADD231PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0xBC /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R
|
||||
VFNMADD231PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0xBC /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R
|
||||
VFNMADD231SS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:2 p:1 l:i w:0 0xBD /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R
|
||||
VFNMADD231SD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:2 p:1 l:i w:1 0xBD /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R
|
||||
VFNMSUB231PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0xBE /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R
|
||||
VFNMSUB231PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0xBE /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R
|
||||
VFNMSUB231SS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:2 p:1 l:i w:0 0xBF /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R
|
||||
VFNMSUB231SD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:2 p:1 l:i w:1 0xBF /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R
|
||||
VFMADDSUB231PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0xB6 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFMADDSUB231PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0xB6 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFMSUBADD231PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0xB7 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFMSUBADD231PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0xB7 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFMADD231PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0xB8 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFMADD231PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0xB8 /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFMADD231SS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:2 p:1 l:i w:0 0xB9 /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFMADD231SD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:2 p:1 l:i w:1 0xB9 /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFMSUB231PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0xBA /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFMSUB231PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0xBA /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFMSUB231SS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:2 p:1 l:i w:0 0xBB /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFMSUB231SD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:2 p:1 l:i w:1 0xBB /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFNMADD231PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0xBC /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFNMADD231PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0xBC /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFNMADD231SS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:2 p:1 l:i w:0 0xBD /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFNMADD231SD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:2 p:1 l:i w:1 0xBD /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFNMSUB231PS ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:2 p:1 l:x w:0 0xBE /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFNMSUB231PD ; Vfv{K}{z},Hfv,Wfv|B64{er} ; ; evex m:2 p:1 l:x w:1 0xBE /r ; s:AVX512F, t:VFMA, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFNMSUB231SS ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:2 p:1 l:i w:0 0xBF /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFNMSUB231SD ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:2 p:1 l:i w:1 0xBF /r ; s:AVX512F, t:VFMA, l:t1s, e:E3, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
|
||||
# 0xC0 - 0xCF
|
||||
VPCONFLICTD ; Vfv{K}{z},Wfv|B32 ; ; evex m:2 p:1 l:x w:0 0xC4 /r ; s:AVX512CD, t:CONFLICT, l:fv, e:E4NF, w:W|R|R
|
||||
@ -331,16 +340,16 @@ VSCATTERPF0QPD ; Mvm64n{K} ; ; evex m:2 p:1 l:2 w:1
|
||||
VSCATTERPF1QPS ; Mvm64n{K} ; ; evex m:2 p:1 l:2 w:0 0xC7 /6:mem vsib ; s:AVX512PF, t:SCATTER, a:MMASK, l:t1s, e:E12NP, w:P|R
|
||||
VSCATTERPF1QPD ; Mvm64n{K} ; ; evex m:2 p:1 l:2 w:1 0xC7 /6:mem vsib ; s:AVX512PF, t:SCATTER, a:MMASK, l:t1s, e:E12NP, w:P|R
|
||||
|
||||
VEXP2PS ; Voq{K}{z},Woq|B32{sae} ; ; evex m:2 p:1 l:2 w:0 0xC8 /r ; s:AVX512ER, t:KNL, l:fv, e:E2, w:W|R|R
|
||||
VEXP2PD ; Voq{K}{z},Woq|B64{sae} ; ; evex m:2 p:1 l:2 w:1 0xC8 /r ; s:AVX512ER, t:KNL, l:fv, e:E2, w:W|R|R
|
||||
VRCP28PS ; Voq{K}{z},Woq|B32{sae} ; ; evex m:2 p:1 l:2 w:0 0xCA /r ; s:AVX512ER, t:KNL, l:fv, e:E2, w:W|R|R
|
||||
VRCP28PD ; Voq{K}{z},Woq|B64{sae} ; ; evex m:2 p:1 l:2 w:1 0xCA /r ; s:AVX512ER, t:KNL, l:fv, e:E2, w:W|R|R
|
||||
VRCP28SS ; Vdq{K}{z},Hdq,Wss{sae} ; ; evex m:2 p:1 l:i w:0 0xCB /r ; s:AVX512ER, t:KNL, l:t1s, e:E3, w:W|R|R|R
|
||||
VRCP28SD ; Vdq{K}{z},Hdq,Wsd{sae} ; ; evex m:2 p:1 l:i w:1 0xCB /r ; s:AVX512ER, t:KNL, l:t1s, e:E3, w:W|R|R|R
|
||||
VRSQRT28PS ; Voq{K}{z},Woq|B32{sae} ; ; evex m:2 p:1 l:2 w:0 0xCC /r ; s:AVX512ER, t:KNL, l:fv, e:E2, w:W|R|R
|
||||
VRSQRT28PD ; Voq{K}{z},Woq|B64{sae} ; ; evex m:2 p:1 l:2 w:1 0xCC /r ; s:AVX512ER, t:KNL, l:fv, e:E2, w:W|R|R
|
||||
VRSQRT28SS ; Vdq{K}{z},Hdq,Wss{sae} ; ; evex m:2 p:1 l:i w:0 0xCD /r ; s:AVX512ER, t:KNL, l:t1s, e:E3, w:W|R|R|R
|
||||
VRSQRT28SD ; Vdq{K}{z},Hdq,Wsd{sae} ; ; evex m:2 p:1 l:i w:1 0xCD /r ; s:AVX512ER, t:KNL, l:t1s, e:E3, w:W|R|R|R
|
||||
VEXP2PS ; Voq{K}{z},Woq|B32{sae} ; ; evex m:2 p:1 l:2 w:0 0xC8 /r ; s:AVX512ER, t:KNL, l:fv, e:E2, w:W|R|R, x:IE|OE
|
||||
VEXP2PD ; Voq{K}{z},Woq|B64{sae} ; ; evex m:2 p:1 l:2 w:1 0xC8 /r ; s:AVX512ER, t:KNL, l:fv, e:E2, w:W|R|R, x:IE|OE
|
||||
VRCP28PS ; Voq{K}{z},Woq|B32{sae} ; ; evex m:2 p:1 l:2 w:0 0xCA /r ; s:AVX512ER, t:KNL, l:fv, e:E2, w:W|R|R, x:IE|ZE
|
||||
VRCP28PD ; Voq{K}{z},Woq|B64{sae} ; ; evex m:2 p:1 l:2 w:1 0xCA /r ; s:AVX512ER, t:KNL, l:fv, e:E2, w:W|R|R, x:IE|ZE
|
||||
VRCP28SS ; Vdq{K}{z},Hdq,Wss{sae} ; ; evex m:2 p:1 l:i w:0 0xCB /r ; s:AVX512ER, t:KNL, l:t1s, e:E3, w:W|R|R|R, x:IE|ZE
|
||||
VRCP28SD ; Vdq{K}{z},Hdq,Wsd{sae} ; ; evex m:2 p:1 l:i w:1 0xCB /r ; s:AVX512ER, t:KNL, l:t1s, e:E3, w:W|R|R|R, x:IE|ZE
|
||||
VRSQRT28PS ; Voq{K}{z},Woq|B32{sae} ; ; evex m:2 p:1 l:2 w:0 0xCC /r ; s:AVX512ER, t:KNL, l:fv, e:E2, w:W|R|R, x:IE|ZE
|
||||
VRSQRT28PD ; Voq{K}{z},Woq|B64{sae} ; ; evex m:2 p:1 l:2 w:1 0xCC /r ; s:AVX512ER, t:KNL, l:fv, e:E2, w:W|R|R, x:IE|ZE
|
||||
VRSQRT28SS ; Vdq{K}{z},Hdq,Wss{sae} ; ; evex m:2 p:1 l:i w:0 0xCD /r ; s:AVX512ER, t:KNL, l:t1s, e:E3, w:W|R|R|R, x:IE|ZE
|
||||
VRSQRT28SD ; Vdq{K}{z},Hdq,Wsd{sae} ; ; evex m:2 p:1 l:i w:1 0xCD /r ; s:AVX512ER, t:KNL, l:t1s, e:E3, w:W|R|R|R, x:IE|ZE
|
||||
VGF2P8MULB ; Vfv{K}{z},Hfv,Wfv ; ; evex m:2 p:1 l:x w:0 0xCF /r ; s:GFNI, t:GFNI, l:fvm, e:E4, w:W|R|R|R
|
||||
|
||||
# 0xD0 - 0xDF
|
||||
@ -350,6 +359,8 @@ VPDPWSUD ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:2 l:x w:0
|
||||
VPDPWUUDS ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:0 l:x w:0 0xD3 /r ; s:AVX102, t:AVX10INT, l:fv, e:E4, w:RW|R|R|R
|
||||
VPDPWUSDS ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:1 l:x w:0 0xD3 /r ; s:AVX102, t:AVX10INT, l:fv, e:E4, w:RW|R|R|R
|
||||
VPDPWSUDS ; Vfv{K}{z},Hfv,Wfv|B32 ; ; evex m:2 p:2 l:x w:0 0xD3 /r ; s:AVX102, t:AVX10INT, l:fv, e:E4, w:RW|R|R|R
|
||||
VSM4KEY4 ; Vfv,Hfv,Wfv ; ; evex m:2 p:2 l:x w:0 0xDA /r ; s:SM4, t:SM4, l:fvm, e:E6, w:W|R|R
|
||||
VSM4RNDS4 ; Vfv,Hfv,Wfv ; ; evex m:2 p:3 l:x w:0 0xDA /r ; s:SM4, t:SM4, l:fvm, e:E6, w:W|R|R
|
||||
VAESENC ; Vfv,Hfv,Wfv ; ; evex m:2 p:1 l:x w:i 0xDC /r ; s:VAES, t:VAES, l:fvm, e:E4NF, w:W|R|R
|
||||
VAESENCLAST ; Vfv,Hfv,Wfv ; ; evex m:2 p:1 l:x w:i 0xDD /r ; s:VAES, t:VAES, l:fvm, e:E4NF, w:W|R|R
|
||||
VAESDEC ; Vfv,Hfv,Wfv ; ; evex m:2 p:1 l:x w:i 0xDE /r ; s:VAES, t:VAES, l:fvm, e:E4NF, w:W|R|R
|
||||
|
||||
@ -10,13 +10,19 @@ VALIGND ; Vfv{K}{z},Hfv,Wfv|B32,Ib ; ; evex m:3 p:1 l:x w:0
|
||||
VALIGNQ ; Vfv{K}{z},Hfv,Wfv|B64,Ib ; ; evex m:3 p:1 l:x w:1 0x03 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R|R
|
||||
VPERMILPS ; Vfv{K}{z},Wfv|B32,Ib ; ; evex m:3 p:1 l:x w:0 0x04 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R
|
||||
VPERMILPD ; Vfv{K}{z},Wfv|B64,Ib ; ; evex m:3 p:1 l:x w:1 0x05 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R
|
||||
VRNDSCALEPH ; Vfv{K}{z},Wfv|B16{sae},Ib ; ; evex m:3 p:0 l:x w:0 0x08 /r ib ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R
|
||||
VRNDSCALEPS ; Vfv{K}{z},Wfv|B32{sae},Ib ; ; evex m:3 p:1 l:x w:0 0x08 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R
|
||||
|
||||
TCVTROWPS2PHH ; Voq,mTt,Ib ; ; evex m:3 p:0 l:2 w:0 0x07 /r:reg ib ; s:AMXAVX512, t:AMX, e:AMX_EVEX_E7, w:W|R|R, m:NOTSX
|
||||
TILEMOVROW ; Voq,mTt,Ib ; ; evex m:3 p:1 l:2 w:0 0x07 /r:reg ib ; s:AMXAVX512, t:AMX, e:AMX_EVEX_E7, w:W|R|R, m:NOTSX
|
||||
TCVTROWD2PS ; Voq,mTt,Ib ; ; evex m:3 p:2 l:2 w:0 0x07 /r:reg ib ; s:AMXAVX512, t:AMX, e:AMX_EVEX_E7, w:W|R|R, m:NOTSX
|
||||
TCVTROWPS2PBF16H ; Voq,mTt,Ib ; ; evex m:3 p:3 l:2 w:0 0x07 /r:reg ib ; s:AMXAVX512, t:AMX, e:AMX_EVEX_E7, w:W|R|R, m:NOTSX
|
||||
|
||||
VRNDSCALEPH ; Vfv{K}{z},Wfv|B16{sae},Ib ; ; evex m:3 p:0 l:x w:0 0x08 /r ib ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R, x:IE|PE|UE
|
||||
VRNDSCALEPS ; Vfv{K}{z},Wfv|B32{sae},Ib ; ; evex m:3 p:1 l:x w:0 0x08 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R, x:IE|PE
|
||||
VRNDSCALENEPBF16 ; Vfv{K}{z},Wfv|B16,Ib ; ; evex m:3 p:3 l:x w:0 0x08 /r ib ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:W|R|R|R
|
||||
VRNDSCALEPD ; Vfv{K}{z},Wfv|B64{sae},Ib ; ; evex m:3 p:1 l:x w:1 0x09 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R
|
||||
VRNDSCALESH ; Vdq{K}{z},Hdq,Wsh{sae},Ib ; ; evex m:3 p:0 l:i w:0 0x0A /r ib ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R|R
|
||||
VRNDSCALESS ; Vdq{K}{z},Hdq,Wss{sae},Ib ; ; evex m:3 p:1 l:i w:0 0x0A /r ib ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R
|
||||
VRNDSCALESD ; Vdq{K}{z},Hdq,Wsd{sae},Ib ; ; evex m:3 p:1 l:i w:1 0x0B /r ib ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R
|
||||
VRNDSCALEPD ; Vfv{K}{z},Wfv|B64{sae},Ib ; ; evex m:3 p:1 l:x w:1 0x09 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R, x:IE|PE
|
||||
VRNDSCALESH ; Vdq{K}{z},Hdq,Wsh{sae},Ib ; ; evex m:3 p:0 l:i w:0 0x0A /r ib ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R|R, x:IE|UE|PE
|
||||
VRNDSCALESS ; Vdq{K}{z},Hdq,Wss{sae},Ib ; ; evex m:3 p:1 l:i w:0 0x0A /r ib ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R, x:IE|PE
|
||||
VRNDSCALESD ; Vdq{K}{z},Hdq,Wsd{sae},Ib ; ; evex m:3 p:1 l:i w:1 0x0B /r ib ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R, x:IE|PE
|
||||
VPALIGNR ; Vfv{K}{z},Hfv,Wfv,Ib ; ; evex m:3 p:1 l:x w:i 0x0F /r ib ; s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:W|R|R|R|R
|
||||
|
||||
# 0x10 - 0x1F
|
||||
@ -38,7 +44,7 @@ VINSERTF32X8 ; Voq{K}{z},Hoq,Wqq,Ib ; ; evex m:3 p:1 l:2 w:0
|
||||
VINSERTF64X4 ; Voq{K}{z},Hoq,Wqq,Ib ; ; evex m:3 p:1 l:2 w:1 0x1A /r ib ; s:AVX512F, t:AVX512, l:t4, e:E6NF, w:W|R|R|R|R
|
||||
VEXTRACTF32X8 ; Wqq{K}{z},Voq,Ib ; ; evex m:3 p:1 l:2 w:0 0x1B /r ib ; s:AVX512DQ, t:AVX512, l:t8, e:E6NF, w:W|R|R|R
|
||||
VEXTRACTF64X4 ; Wqq{K}{z},Voq,Ib ; ; evex m:3 p:1 l:2 w:1 0x1B /r ib ; s:AVX512F, t:AVX512, l:t4, e:E6NF, w:W|R|R|R
|
||||
VCVTPS2PH ; Whv{K}{z},Vfv{sae},Ib ; ; evex m:3 p:1 l:x w:0 0x1D /r ib ; s:AVX512F, t:CONVERT, l:hvm, e:E11, w:W|R|R|R
|
||||
VCVTPS2PH ; Whv{K}{z},Vfv{sae},Ib ; ; evex m:3 p:1 l:x w:0 0x1D /r ib ; s:AVX512F, t:CONVERT, l:hvm, e:E11, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VPCMPUD ; rKq{K},Hfv,Wfv|B32,Ib ; ; evex m:3 p:1 l:x w:0 0x1E /r ib ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R|R
|
||||
VPCMPUQ ; rKq{K},Hfv,Wfv|B64,Ib ; ; evex m:3 p:1 l:x w:1 0x1E /r ib ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R|R
|
||||
VPCMPD ; rKq{K},Hfv,Wfv|B32,Ib ; ; evex m:3 p:1 l:x w:0 0x1F /r ib ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R|R
|
||||
@ -55,13 +61,13 @@ VSHUFF32X4 ; Vuv{K}{z},Huv,Wuv|B32,Ib ; ; evex m:3 p:1 l:x w:0
|
||||
VSHUFF64X2 ; Vuv{K}{z},Huv,Wuv|B64,Ib ; ; evex m:3 p:1 l:x w:1 0x23 /r ib ; s:AVX512F, t:AVX512, a:NOL0, l:fv, e:E4NF, w:W|R|R|R|R
|
||||
VPTERNLOGD ; Vfv{K}{z},Hfv,Wfv|B32,Ib ; ; evex m:3 p:1 l:x w:0 0x25 /r ib ; s:AVX512F, t:LOGICAL, l:fv, e:E4, w:RW|R|R|R|R
|
||||
VPTERNLOGQ ; Vfv{K}{z},Hfv,Wfv|B64,Ib ; ; evex m:3 p:1 l:x w:1 0x25 /r ib ; s:AVX512F, t:LOGICAL, l:fv, e:E4, w:RW|R|R|R|R
|
||||
VGETMANTPH ; Vfv{K}{z},Wfv|B16{sae},Ib ; ; evex m:3 p:0 l:x w:0 0x26 /r ib ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R
|
||||
VGETMANTPS ; Vfv{K}{z},Wfv|B32{sae},Ib ; ; evex m:3 p:1 l:x w:0 0x26 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R
|
||||
VGETMANTPD ; Vfv{K}{z},Wfv|B64{sae},Ib ; ; evex m:3 p:1 l:x w:1 0x26 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R
|
||||
VGETMANTPH ; Vfv{K}{z},Wfv|B16{sae},Ib ; ; evex m:3 p:0 l:x w:0 0x26 /r ib ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R, x:IE|DE
|
||||
VGETMANTPS ; Vfv{K}{z},Wfv|B32{sae},Ib ; ; evex m:3 p:1 l:x w:0 0x26 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R, x:IE|DE
|
||||
VGETMANTPD ; Vfv{K}{z},Wfv|B64{sae},Ib ; ; evex m:3 p:1 l:x w:1 0x26 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R, x:IE|DE
|
||||
VGETMANTPBF16 ; Vfv{K}{z},Wfv|B16,Ib ; ; evex m:3 p:3 l:x w:0 0x26 /r ib ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:W|R|R|R
|
||||
VGETMANTSH ; Vdq{K}{z},Hdq,Wsh{sae},Ib ; ; evex m:3 p:0 l:i w:0 0x27 /r ib ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R|R
|
||||
VGETMANTSS ; Vdq{K}{z},Hdq,Wss{sae},Ib ; ; evex m:3 p:1 l:i w:0 0x27 /r ib ; s:AVX512F, t:AVX512, l:t1s, e:E2, w:W|R|R|R|R
|
||||
VGETMANTSD ; Vdq{K}{z},Hdq,Wsd{sae},Ib ; ; evex m:3 p:1 l:i w:1 0x27 /r ib ; s:AVX512F, t:AVX512, l:t1s, e:E2, w:W|R|R|R|R
|
||||
VGETMANTSH ; Vdq{K}{z},Hdq,Wsh{sae},Ib ; ; evex m:3 p:0 l:i w:0 0x27 /r ib ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R|R, x:IE|DE
|
||||
VGETMANTSS ; Vdq{K}{z},Hdq,Wss{sae},Ib ; ; evex m:3 p:1 l:i w:0 0x27 /r ib ; s:AVX512F, t:AVX512, l:t1s, e:E2, w:W|R|R|R|R, x:IE|DE
|
||||
VGETMANTSD ; Vdq{K}{z},Hdq,Wsd{sae},Ib ; ; evex m:3 p:1 l:i w:1 0x27 /r ib ; s:AVX512F, t:AVX512, l:t1s, e:E2, w:W|R|R|R|R, x:IE|DE
|
||||
|
||||
# 0x30 - 0x3F
|
||||
VINSERTI32X4 ; Vuv{K}{z},Huv,Wdq,Ib ; ; evex m:3 p:1 l:x w:0 0x38 /r ib ; s:AVX512F, t:AVX512, a:NOL0, l:t4, e:E6NF, w:W|R|R|R|R
|
||||
@ -85,28 +91,28 @@ VSHUFI64X2 ; Vuv{K}{z},Huv,Wuv|B64,Ib ; ; evex m:3 p:1 l:x w:1
|
||||
VPCLMULQDQ ; Vfv,Hfv,Wfv,Ib ; ; evex m:3 p:1 l:x w:i 0x44 /r ib ; s:VPCLMULQDQ, t:VPCLMULQDQ, l:fvm, e:E4NF, w:W|R|R|R
|
||||
|
||||
# 0x50 - 0x5F
|
||||
VRANGEPS ; Vfv{K}{z},Hfv,Wfv|B32{sae},Ib ; ; evex m:3 p:1 l:x w:0 0x50 /r ib ; s:AVX512DQ, t:AVX512, l:fv, e:E2, w:W|R|R|R|R
|
||||
VRANGEPD ; Vfv{K}{z},Hfv,Wfv|B64{sae},Ib ; ; evex m:3 p:1 l:x w:1 0x50 /r ib ; s:AVX512DQ, t:AVX512, l:fv, e:E2, w:W|R|R|R|R
|
||||
VRANGESS ; Vdq{K}{z},Hdq,Wss{sae},Ib ; ; evex m:3 p:1 l:i w:0 0x51 /r ib ; s:AVX512DQ, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R
|
||||
VRANGESD ; Vdq{K}{z},Hdq,Wsd{sae},Ib ; ; evex m:3 p:1 l:i w:1 0x51 /r ib ; s:AVX512DQ, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R
|
||||
VMINMAXPH ; Vfv{K}{z},Hfv,Wfv|B16{sae},Ib ; ; evex m:3 p:0 l:x w:0 0x52 /r ib ; s:AVX102, t:AVX10MINMAX, l:fv, e:E2, w:W|R|R|R|R
|
||||
VMINMAXPS ; Vfv{K}{z},Hfv,Wfv|B32{sae},Ib ; ; evex m:3 p:1 l:x w:0 0x52 /r ib ; s:AVX102, t:AVX10MINMAX, l:fv, e:E2, w:W|R|R|R|R
|
||||
VMINMAXPD ; Vfv{K}{z},Hfv,Wfv|B64{sae},Ib ; ; evex m:3 p:1 l:x w:1 0x52 /r ib ; s:AVX102, t:AVX10MINMAX, l:fv, e:E2, w:W|R|R|R|R
|
||||
VRANGEPS ; Vfv{K}{z},Hfv,Wfv|B32{sae},Ib ; ; evex m:3 p:1 l:x w:0 0x50 /r ib ; s:AVX512DQ, t:AVX512, l:fv, e:E2, w:W|R|R|R|R, x:IE|DE
|
||||
VRANGEPD ; Vfv{K}{z},Hfv,Wfv|B64{sae},Ib ; ; evex m:3 p:1 l:x w:1 0x50 /r ib ; s:AVX512DQ, t:AVX512, l:fv, e:E2, w:W|R|R|R|R, x:IE|DE
|
||||
VRANGESS ; Vdq{K}{z},Hdq,Wss{sae},Ib ; ; evex m:3 p:1 l:i w:0 0x51 /r ib ; s:AVX512DQ, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R, x:IE|DE
|
||||
VRANGESD ; Vdq{K}{z},Hdq,Wsd{sae},Ib ; ; evex m:3 p:1 l:i w:1 0x51 /r ib ; s:AVX512DQ, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R, x:IE|DE
|
||||
VMINMAXPH ; Vfv{K}{z},Hfv,Wfv|B16{sae},Ib ; ; evex m:3 p:0 l:x w:0 0x52 /r ib ; s:AVX102, t:AVX10MINMAX, l:fv, e:E2, w:W|R|R|R|R, x:IE|DE
|
||||
VMINMAXPS ; Vfv{K}{z},Hfv,Wfv|B32{sae},Ib ; ; evex m:3 p:1 l:x w:0 0x52 /r ib ; s:AVX102, t:AVX10MINMAX, l:fv, e:E2, w:W|R|R|R|R, x:IE|DE
|
||||
VMINMAXPD ; Vfv{K}{z},Hfv,Wfv|B64{sae},Ib ; ; evex m:3 p:1 l:x w:1 0x52 /r ib ; s:AVX102, t:AVX10MINMAX, l:fv, e:E2, w:W|R|R|R|R, x:IE|DE
|
||||
VMINMAXNEPBF16 ; Vfv{K}{z},Hfv,Wfv|B16,Ib ; ; evex m:3 p:3 l:x w:0 0x52 /r ib ; s:AVX102, t:AVX10MINMAX, l:fv, e:E4, w:W|R|R|R|R
|
||||
VMINMAXSH ; Vdq{K}{z},Hdq,Wsh{sae},Ib ; ; evex m:3 p:0 l:i w:0 0x53 /r ib ; s:AVX102, t:AVX10MINMAX, l:t1s, e:E3, w:W|R|R|R|R
|
||||
VMINMAXSS ; Vdq{K}{z},Hdq,Wss{sae},Ib ; ; evex m:3 p:1 l:i w:0 0x53 /r ib ; s:AVX102, t:AVX10MINMAX, l:t1s, e:E3, w:W|R|R|R|R
|
||||
VMINMAXSD ; Vdq{K}{z},Hdq,Wsd{sae},Ib ; ; evex m:3 p:1 l:i w:1 0x53 /r ib ; s:AVX102, t:AVX10MINMAX, l:t1s, e:E3, w:W|R|R|R|R
|
||||
VFIXUPIMMPS ; Vfv{K}{z},Hfv,Wfv|B32{sae},Ib ; ; evex m:3 p:1 l:x w:0 0x54 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E2, w:RW|R|R|R|R
|
||||
VFIXUPIMMPD ; Vfv{K}{z},Hfv,Wfv|B64{sae},Ib ; ; evex m:3 p:1 l:x w:1 0x54 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E2, w:RW|R|R|R|R
|
||||
VFIXUPIMMSS ; Vdq{K}{z},Hdq,Wss{sae},Ib ; ; evex m:3 p:1 l:i w:0 0x55 /r ib ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:RW|R|R|R|R
|
||||
VFIXUPIMMSD ; Vdq{K}{z},Hdq,Wsd{sae},Ib ; ; evex m:3 p:1 l:i w:1 0x55 /r ib ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:RW|R|R|R|R
|
||||
VREDUCEPH ; Vfv{K}{z},Wfv|B16{sae},Ib ; ; evex m:3 p:0 l:x w:0 0x56 /r ib ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R
|
||||
VREDUCEPS ; Vfv{K}{z},Wfv|B32{sae},Ib ; ; evex m:3 p:1 l:x w:0 0x56 /r ib ; s:AVX512DQ, t:AVX512, l:fv, e:E2, w:W|R|R|R
|
||||
VREDUCEPD ; Vfv{K}{z},Wfv|B64{sae},Ib ; ; evex m:3 p:1 l:x w:1 0x56 /r ib ; s:AVX512DQ, t:AVX512, l:fv, e:E2, w:W|R|R|R
|
||||
VMINMAXSH ; Vdq{K}{z},Hdq,Wsh{sae},Ib ; ; evex m:3 p:0 l:i w:0 0x53 /r ib ; s:AVX102, t:AVX10MINMAX, l:t1s, e:E3, w:W|R|R|R|R, x:IE|DE
|
||||
VMINMAXSS ; Vdq{K}{z},Hdq,Wss{sae},Ib ; ; evex m:3 p:1 l:i w:0 0x53 /r ib ; s:AVX102, t:AVX10MINMAX, l:t1s, e:E3, w:W|R|R|R|R, x:IE|DE
|
||||
VMINMAXSD ; Vdq{K}{z},Hdq,Wsd{sae},Ib ; ; evex m:3 p:1 l:i w:1 0x53 /r ib ; s:AVX102, t:AVX10MINMAX, l:t1s, e:E3, w:W|R|R|R|R, x:IE|DE
|
||||
VFIXUPIMMPS ; Vfv{K}{z},Hfv,Wfv|B32{sae},Ib ; ; evex m:3 p:1 l:x w:0 0x54 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E2, w:RW|R|R|R|R, x:IE|ZE
|
||||
VFIXUPIMMPD ; Vfv{K}{z},Hfv,Wfv|B64{sae},Ib ; ; evex m:3 p:1 l:x w:1 0x54 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E2, w:RW|R|R|R|R, x:IE|ZE
|
||||
VFIXUPIMMSS ; Vdq{K}{z},Hdq,Wss{sae},Ib ; ; evex m:3 p:1 l:i w:0 0x55 /r ib ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:RW|R|R|R|R, x:IE|ZE
|
||||
VFIXUPIMMSD ; Vdq{K}{z},Hdq,Wsd{sae},Ib ; ; evex m:3 p:1 l:i w:1 0x55 /r ib ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:RW|R|R|R|R, x:IE|ZE
|
||||
VREDUCEPH ; Vfv{K}{z},Wfv|B16{sae},Ib ; ; evex m:3 p:0 l:x w:0 0x56 /r ib ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R, x:IE|PE
|
||||
VREDUCEPS ; Vfv{K}{z},Wfv|B32{sae},Ib ; ; evex m:3 p:1 l:x w:0 0x56 /r ib ; s:AVX512DQ, t:AVX512, l:fv, e:E2, w:W|R|R|R, x:IE|PE
|
||||
VREDUCEPD ; Vfv{K}{z},Wfv|B64{sae},Ib ; ; evex m:3 p:1 l:x w:1 0x56 /r ib ; s:AVX512DQ, t:AVX512, l:fv, e:E2, w:W|R|R|R, x:IE|PE
|
||||
VREDUCENEPBF16 ; Vfv{K}{z},Wfv|B16,Ib ; ; evex m:3 p:3 l:x w:0 0x56 /r ib ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:W|R|R|R
|
||||
VREDUCESH ; Vdq{K}{z},Hdq,Wsh{sae},Ib ; ; evex m:3 p:0 l:i w:0 0x57 /r ib ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R|R
|
||||
VREDUCESS ; Vdq{K}{z},Hdq,Wss{sae},Ib ; ; evex m:3 p:1 l:i w:0 0x57 /r ib ; s:AVX512DQ, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R
|
||||
VREDUCESD ; Vdq{K}{z},Hdq,Wsd{sae},Ib ; ; evex m:3 p:1 l:i w:1 0x57 /r ib ; s:AVX512DQ, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R
|
||||
VREDUCESH ; Vdq{K}{z},Hdq,Wsh{sae},Ib ; ; evex m:3 p:0 l:i w:0 0x57 /r ib ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R|R, x:IE|PE
|
||||
VREDUCESS ; Vdq{K}{z},Hdq,Wss{sae},Ib ; ; evex m:3 p:1 l:i w:0 0x57 /r ib ; s:AVX512DQ, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R, x:IE|PE
|
||||
VREDUCESD ; Vdq{K}{z},Hdq,Wsd{sae},Ib ; ; evex m:3 p:1 l:i w:1 0x57 /r ib ; s:AVX512DQ, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R, x:IE|PE
|
||||
|
||||
# 0x60 - 0x6F
|
||||
VFPCLASSPH ; rKq{K},Wfv|B16,Ib ; ; evex m:3 p:0 l:x w:0 0x66 /r ib ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E4, w:W|R|R|R
|
||||
@ -125,6 +131,9 @@ VPSHRDW ; Vfv{K}{z},Hfv,Wfv,Ib ; ; evex m:3 p:1 l:x w:1
|
||||
VPSHRDD ; Vfv{K}{z},Hfv,Wfv|B32,Ib ; ; evex m:3 p:1 l:x w:0 0x73 /r ib ; s:AVX512VBMI2, t:AVX512VBMI, l:fv, e:E4, w:RW|R|R|R|R
|
||||
VPSHRDQ ; Vfv{K}{z},Hfv,Wfv|B64,Ib ; ; evex m:3 p:1 l:x w:1 0x73 /r ib ; s:AVX512VBMI2, t:AVX512VBMI, l:fv, e:E4, w:RW|R|R|R|R
|
||||
|
||||
TCVTROWPS2PBF16L ; Voq,mTt,Ib ; ; evex m:3 p:2 l:2 w:0 0x77 /r:reg ib ; s:AMXAVX512, t:AMX, e:AMX_EVEX_E7, w:W|R|R, m:NOTSX
|
||||
TCVTROWPS2PHL ; Voq,mTt,Ib ; ; evex m:3 p:3 l:2 w:0 0x77 /r:reg ib ; s:AMXAVX512, t:AMX, e:AMX_EVEX_E7, w:W|R|R, m:NOTSX
|
||||
|
||||
# 0x80 - 0x8F
|
||||
|
||||
# 0x90 - 0x9F
|
||||
@ -134,12 +143,12 @@ VPSHRDQ ; Vfv{K}{z},Hfv,Wfv|B64,Ib ; ; evex m:3 p:1 l:x w:1
|
||||
# 0xB0 - 0xBF
|
||||
|
||||
# 0xC0 - 0xCF
|
||||
VCMPPH ; rK{K},Hfv,Wfv|B16{sae},Ib ; ; evex m:3 p:0 l:x w:0 0xC2 /r ib ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R|R
|
||||
VCMPSH ; rK{K},Hfv,Wsh{sae},Ib ; ; evex m:3 p:2 l:i w:0 0xC2 /r ib ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R|R
|
||||
VCMPPH ; rK{K},Hfv,Wfv|B16{sae},Ib ; ; evex m:3 p:0 l:x w:0 0xC2 /r ib ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R|R, x:IE|DE
|
||||
VCMPSH ; rK{K},Hfv,Wsh{sae},Ib ; ; evex m:3 p:2 l:i w:0 0xC2 /r ib ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R|R, x:IE|DE
|
||||
VCMPPBF16 ; rK{K},Hfv,Wfv|B16,Ib ; ; evex m:3 p:3 l:x w:0 0xC2 /r ib ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:W|R|R|R|R
|
||||
|
||||
VGF2P8AFFINEQB ; Vfv{K}{z},Hfv,Wfv|B64,Ib ; ; evex m:3 p:1 l:x w:1 0xCE /r ib ; s:GFNI, t:GFNI, l:fv, e:E4NF, w:W|R|R|R|R
|
||||
VGF2P8AFFINEINVQB ; Vfv{K}{z},Hfv,Wfv|B64,Ib ; ; evex m:3 p:1 l:x w:1 0xCF /r ib ; s:GFNI, t:GFNI, l:fv, e:E4NF, w:W|R|R|R|R
|
||||
VGF2P8AFFINEQB ; Vfv{K}{z},Hfv,Wfv|B64,Ib ; ; evex m:3 p:1 l:x w:1 0xCE /r ib ; s:GFNI, t:GFNI, l:fv, e:E4NF, w:W|R|R|R|R
|
||||
VGF2P8AFFINEINVQB ; Vfv{K}{z},Hfv,Wfv|B64,Ib ; ; evex m:3 p:1 l:x w:1 0xCF /r ib ; s:GFNI, t:GFNI, l:fv, e:E4NF, w:W|R|R|R|R
|
||||
|
||||
# 0xD0 - 0xDF
|
||||
|
||||
|
||||
@ -8,111 +8,113 @@ VMOVSH ; Vdq{K}{z},Wsh ; ; evex m:5 p:2 l:i w:0
|
||||
VMOVSH ; Vdq{K}{z},Hdq,Wsh ; ; evex m:5 p:2 l:i w:0 0x10 /r:reg ; s:AVX512FP16, t:AVX512FP16, e:E5, w:W|R|R|R
|
||||
VMOVSH ; Wsh{K},Vdq ; ; evex m:5 p:2 l:i w:0 0x11 /r:mem ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E5, w:W|R|R
|
||||
VMOVSH ; Wsh{K}{z},Hdq,Vdq ; ; evex m:5 p:2 l:i w:0 0x11 /r:reg ; s:AVX512FP16, t:AVX512FP16, e:E5, w:W|R|R|R
|
||||
VCVTBIASPH2HF8 ; Vhv{K}{z},Hfv,Wfv|B16 ; ; evex m:5 p:0 l:x w:0 0x18 /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R|R
|
||||
VCVTNEPH2HF8 ; Vhv{K}{z},Wfv|B16 ; ; evex m:5 p:2 l:x w:0 0x18 /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R
|
||||
VCVTNE2PH2HF8 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:5 p:3 l:x w:0 0x18 /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R|R
|
||||
VCVTBIASPH2HF8S ; Vhv{K}{z},Hfv,Wfv|B16 ; ; evex m:5 p:0 l:x w:0 0x1B /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R|R
|
||||
VCVTNEPH2HF8S ; Vhv{K}{z},Wfv|B16 ; ; evex m:5 p:2 l:x w:0 0x1B /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R
|
||||
VCVTNE2PH2HF8S ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:5 p:3 l:x w:0 0x1B /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R|R
|
||||
VCVTPS2PHX ; Vhv{K}{z},Wfv|B32{er} ; ; evex m:5 p:1 l:x w:0 0x1D /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R
|
||||
VCVTSS2SH ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:5 p:0 l:i w:0 0x1D /r ; s:AVX512FP16, t:AVX512FP16, l:t1s, e:E3, w:W|R|R|R
|
||||
VCVTHF82PH ; Vfv{K}{z},Whv ; ; evex m:5 p:3 l:x w:0 0x1E /r ; s:AVX102, t:AVX10CONVERT, l:hv, e:E2, w:W|R|R
|
||||
VCVTBIASPH2HF8 ; Vhv{K}{z},Hfv,Wfv|B16 ; ; evex m:5 p:0 l:x w:0 0x18 /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VCVTNEPH2HF8 ; Vhv{K}{z},Wfv|B16 ; ; evex m:5 p:2 l:x w:0 0x18 /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R, x:IE|OE|UE|PE|DE
|
||||
VCVTNE2PH2HF8 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:5 p:3 l:x w:0 0x18 /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VCVTBIASPH2HF8S ; Vhv{K}{z},Hfv,Wfv|B16 ; ; evex m:5 p:0 l:x w:0 0x1B /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VCVTNEPH2HF8S ; Vhv{K}{z},Wfv|B16 ; ; evex m:5 p:2 l:x w:0 0x1B /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R, x:IE|OE|UE|PE|DE
|
||||
VCVTNE2PH2HF8S ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:5 p:3 l:x w:0 0x1B /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VCVTPS2PHX ; Vhv{K}{z},Wfv|B32{er} ; ; evex m:5 p:1 l:x w:0 0x1D /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R, x:IE|OE|UE|PE|DE
|
||||
VCVTSS2SH ; Vdq{K}{z},Hdq,Wss{er} ; ; evex m:5 p:0 l:i w:0 0x1D /r ; s:AVX512FP16, t:AVX512FP16, l:t1s, e:E3, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VCVTHF82PH ; Vfv{K}{z},Whv ; ; evex m:5 p:3 l:x w:0 0x1E /r ; s:AVX102, t:AVX10CONVERT, l:hv, e:E2, w:W|R|R, x:DE
|
||||
|
||||
# 0x20 - 0x2F
|
||||
VCVTSI2SH ; Vdq,Hdq,Ey ; ; evex m:5 p:2 l:i w:x 0x2A /r ; s:AVX512FP16, t:AVX512FP16, l:t1s, e:E3NF, w:W|R|R, a:IWO64
|
||||
VCVTTSH2SI ; Gy,Wsh{sae} ; ; evex m:5 p:2 l:i w:x 0x2C /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3NF, w:W|R, a:IWO64
|
||||
VCVTSH2SI ; Gy,Wsh{er} ; ; evex m:5 p:2 l:i w:x 0x2D /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3NF, w:W|R, a:IWO64
|
||||
VUCOMISH ; Vdq,Wsh{sae} ; Fv ; evex m:5 p:0 l:i w:0 0x2E /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3NF, w:R|R|W, f:ZF=m|PF=m|CF=m|OF=0|SF=0|AF=0
|
||||
VUCOMXSH ; Vdq,Wsh{sae} ; Fv ; evex m:5 p:3 l:0 w:0 0x2E /r ; s:AVX102, t:AVX10CMPSFP,l:t1s16, e:E3NF, w:R|R|W, f:CMPSFP
|
||||
VCOMISH ; Vdq,Wsh{sae} ; Fv ; evex m:5 p:0 l:i w:0 0x2F /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3NF, w:R|R|W, f:ZF=m|PF=m|CF=m|OF=0|SF=0|AF=0
|
||||
VCVTSI2SH ; Vdq,Hdq,Ey ; ; evex m:5 p:2 l:i w:x 0x2A /r ; s:AVX512FP16, t:AVX512FP16, l:t1s, e:E3NF, w:W|R|R, a:IWO64, x:OE|PE
|
||||
VCVTTSH2SI ; Gy,Wsh{sae} ; ; evex m:5 p:2 l:i w:x 0x2C /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3NF, w:W|R, a:IWO64, x:IE|PE
|
||||
VCVTSH2SI ; Gy,Wsh{er} ; ; evex m:5 p:2 l:i w:x 0x2D /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3NF, w:W|R, a:IWO64, x:IE|PE
|
||||
VUCOMISH ; Vdq,Wsh{sae} ; Fv ; evex m:5 p:0 l:i w:0 0x2E /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3NF, w:R|R|W, f:ZF=m|PF=m|CF=m|OF=0|SF=0|AF=0, x:IE|DE
|
||||
VUCOMXSH ; Vdq,Wsh{sae} ; Fv ; evex m:5 p:2 l:i w:0 0x2E /r ; s:AVX102, t:AVX10CMPSFP,l:t1s16, e:E3NF, w:R|R|W, f:CMPSFP, x:IE|DE
|
||||
VCOMISH ; Vdq,Wsh{sae} ; Fv ; evex m:5 p:0 l:i w:0 0x2F /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3NF, w:R|R|W, f:ZF=m|PF=m|CF=m|OF=0|SF=0|AF=0, x:IE|DE
|
||||
VCOMSBF16 ; Vdq,Wsh ; Fv ; evex m:5 p:1 l:i w:0 0x2F /r ; s:AVX102, t:AVX10BF16, l:t1s16, e:E10NF, w:R|R|W, f:ZF=m|PF=m|CF=m|OF=0|SF=0|AF=0
|
||||
VCOMXSH ; Vdq,Wsh{sae} ; Fv ; evex m:5 p:3 l:0 w:0 0x2F /r ; s:AVX102, t:AVX10CMPSFP,l:t1s16, e:E3NF, w:R|R|W, f:CMPSFP
|
||||
|
||||
# 0x40 - 0x4F
|
||||
VGETEXPPBF16 ; Vfv{K}{z},Wfv|B16 ; ; evex m:5 p:1 l:x w:0 0x42 /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:W|R|R
|
||||
VCOMXSH ; Vdq,Wsh{sae} ; Fv ; evex m:5 p:2 l:i w:0 0x2F /r ; s:AVX102, t:AVX10CMPSFP,l:t1s16, e:E3NF, w:R|R|W, f:CMPSFP, x:IE|DE
|
||||
|
||||
# 0x50 - 0x5F
|
||||
VSQRTPH ; Vfv{K}{z},Wfv|B16{er} ; ; evex m:5 p:0 l:x w:0 0x51 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R
|
||||
VSQRTPH ; Vfv{K}{z},Wfv|B16{er} ; ; evex m:5 p:0 l:x w:0 0x51 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R, x:IE|PE|DE
|
||||
VSQRTNEPBF16 ; Vfv{K}{z},Wfv|B16 ; ; evex m:5 p:1 l:x w:0 0x51 /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:W|R|R
|
||||
VSQRTSH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:5 p:2 l:i w:0 0x51 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R
|
||||
VADDPH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:5 p:0 l:x w:0 0x58 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R
|
||||
VSQRTSH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:5 p:2 l:i w:0 0x51 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R, x:IE|PE|DE
|
||||
VADDPH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:5 p:0 l:x w:0 0x58 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VADDNEPBF16 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:5 p:1 l:x w:0 0x58 /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:W|R|R|R
|
||||
VADDSH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:5 p:2 l:i w:0 0x58 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R
|
||||
VMULPH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:5 p:0 l:x w:0 0x59 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R
|
||||
VADDSH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:5 p:2 l:i w:0 0x58 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VMULPH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:5 p:0 l:x w:0 0x59 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VMULNEPBF16 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:5 p:1 l:x w:0 0x59 /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:W|R|R|R
|
||||
VMULSH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:5 p:2 l:i w:0 0x59 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R
|
||||
VCVTPH2PD ; Vfv{K}{z},Wqv|B16{sae} ; ; evex m:5 p:0 l:x w:0 0x5A /r ; s:AVX512FP16, t:AVX512FP16, l:qv, e:E2, w:W|R|R
|
||||
VCVTPD2PH ; Vdq{K}{z},Wfv|B64{er} ; ; evex m:5 p:1 l:x w:1 0x5A /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R
|
||||
VCVTSH2SD ; Vdq{K}{z},Hdq,Wsh{sae} ; ; evex m:5 p:2 l:i w:0 0x5A /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R
|
||||
VCVTSD2SH ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:5 p:3 l:i w:1 0x5A /r ; s:AVX512FP16, t:AVX512FP16, l:t1s, e:E3, w:W|R|R|R
|
||||
VCVTDQ2PH ; Vhv{K}{z},Wfv|B32{er} ; ; evex m:5 p:0 l:x w:0 0x5B /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R
|
||||
VCVTQQ2PH ; Vdq{K}{z},Wfv|B64{er} ; ; evex m:5 p:0 l:x w:1 0x5B /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R
|
||||
VCVTPH2DQ ; Vfv{K}{z},Whv|B16{er} ; ; evex m:5 p:1 l:x w:0 0x5B /r ; s:AVX512FP16, t:AVX512FP16, l:hv, e:E2, w:W|R|R
|
||||
VCVTTPH2DQ ; Vfv{K}{z},Whv|B16{sae} ; ; evex m:5 p:2 l:x w:0 0x5B /r ; s:AVX512FP16, t:AVX512FP16, l:hv, e:E2, w:W|R|R
|
||||
VSUBPH ; Vfv{K}{z},Hfv,Wfv|B16{sae} ; ; evex m:5 p:0 l:x w:0 0x5C /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R
|
||||
VMULSH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:5 p:2 l:i w:0 0x59 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VCVTPH2PD ; Vfv{K}{z},Wqv|B16{sae} ; ; evex m:5 p:0 l:x w:0 0x5A /r ; s:AVX512FP16, t:AVX512FP16, l:qv, e:E2, w:W|R|R, x:IE|PE
|
||||
VCVTPD2PH ; Vdq{K}{z},Wfv|B64{er} ; ; evex m:5 p:1 l:x w:1 0x5A /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R, x:IE|OE|UE|PE|DE
|
||||
VCVTSH2SD ; Vdq{K}{z},Hdq,Wsh{sae} ; ; evex m:5 p:2 l:i w:0 0x5A /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R, x:IE|DE
|
||||
VCVTSD2SH ; Vdq{K}{z},Hdq,Wsd{er} ; ; evex m:5 p:3 l:i w:1 0x5A /r ; s:AVX512FP16, t:AVX512FP16, l:t1s, e:E3, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VCVTDQ2PH ; Vhv{K}{z},Wfv|B32{er} ; ; evex m:5 p:0 l:x w:0 0x5B /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R, x:PE|OE
|
||||
VCVTQQ2PH ; Vdq{K}{z},Wfv|B64{er} ; ; evex m:5 p:0 l:x w:1 0x5B /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R, x:PE|OE
|
||||
VCVTPH2DQ ; Vfv{K}{z},Whv|B16{er} ; ; evex m:5 p:1 l:x w:0 0x5B /r ; s:AVX512FP16, t:AVX512FP16, l:hv, e:E2, w:W|R|R, x:IE|PE
|
||||
VCVTTPH2DQ ; Vfv{K}{z},Whv|B16{sae} ; ; evex m:5 p:2 l:x w:0 0x5B /r ; s:AVX512FP16, t:AVX512FP16, l:hv, e:E2, w:W|R|R, x:IE|PE
|
||||
VSUBPH ; Vfv{K}{z},Hfv,Wfv|B16{sae} ; ; evex m:5 p:0 l:x w:0 0x5C /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VSUBNEPBF16 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:5 p:1 l:x w:0 0x5C /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:W|R|R|R
|
||||
VSUBSH ; Vdq{K}{z},Hdq,Wsh{sae} ; ; evex m:5 p:2 l:i w:0 0x5C /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R
|
||||
VMINPH ; Vfv{K}{z},Hfv,Wfv|B16{sae} ; ; evex m:5 p:0 l:x w:0 0x5D /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R
|
||||
VSUBSH ; Vdq{K}{z},Hdq,Wsh{sae} ; ; evex m:5 p:2 l:i w:0 0x5C /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VMINPH ; Vfv{K}{z},Hfv,Wfv|B16{sae} ; ; evex m:5 p:0 l:x w:0 0x5D /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R, x:IE|DE
|
||||
VMINPBF16 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:5 p:1 l:x w:0 0x5D /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:W|R|R|R
|
||||
VMINSH ; Vdq{K}{z},Hdq,Wsh{sae} ; ; evex m:5 p:2 l:i w:0 0x5D /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R
|
||||
VDIVPH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:5 p:0 l:x w:0 0x5E /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R
|
||||
VMINSH ; Vdq{K}{z},Hdq,Wsh{sae} ; ; evex m:5 p:2 l:i w:0 0x5D /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R, x:IE|DE
|
||||
VDIVPH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:5 p:0 l:x w:0 0x5E /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R, x:IE|OE|UE|PE|DE|ZE
|
||||
VDIVNEPBF16 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:5 p:1 l:x w:0 0x5E /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:W|R|R|R
|
||||
VDIVSH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:5 p:2 l:i w:0 0x5E /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R
|
||||
VMAXPH ; Vfv{K}{z},Hfv,Wfv|B16{sae} ; ; evex m:5 p:0 l:x w:0 0x5F /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R
|
||||
VDIVSH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:5 p:2 l:i w:0 0x5E /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R, x:IE|OE|UE|PE|DE|ZE
|
||||
VMAXPH ; Vfv{K}{z},Hfv,Wfv|B16{sae} ; ; evex m:5 p:0 l:x w:0 0x5F /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R, x:IE|DE
|
||||
VMAXPBF16 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:5 p:1 l:x w:0 0x5F /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:W|R|R|R
|
||||
VMAXSH ; Vdq{K}{z},Hdq,Wsh{sae} ; ; evex m:5 p:2 l:i w:0 0x5F /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R
|
||||
VMAXSH ; Vdq{K}{z},Hdq,Wsh{sae} ; ; evex m:5 p:2 l:i w:0 0x5F /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R, x:IE|DE
|
||||
|
||||
# 0x60 - 0x6F
|
||||
VCVTTPH2IBS ; Vfv{K}{z},Wfv|B16{sae} ; ; evex m:5 p:0 l:x w:0 0x68 /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R
|
||||
VCVTTPS2IBS ; Vfv{K}{z},Wfv|B32{sae} ; ; evex m:5 p:1 l:x w:0 0x68 /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R
|
||||
VCVTTPH2IBS ; Vfv{K}{z},Wfv|B16{sae} ; ; evex m:5 p:0 l:x w:0 0x68 /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R, x:IE|PE
|
||||
VCVTTPS2IBS ; Vfv{K}{z},Wfv|B32{sae} ; ; evex m:5 p:1 l:x w:0 0x68 /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R, x:IE|PE
|
||||
VCVTTNEBF162IBS ; Vfv{K}{z},Wfv|B16 ; ; evex m:5 p:3 l:x w:0 0x68 /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E4, w:W|R|R
|
||||
VCVTPH2IBS ; Vfv{K}{z},Wfv|B16{er} ; ; evex m:5 p:0 l:x w:0 0x69 /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R
|
||||
VCVTPS2IBS ; Vfv{K}{z},Wfv|B32{er} ; ; evex m:5 p:1 l:x w:0 0x69 /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R
|
||||
VCVTPH2IBS ; Vfv{K}{z},Wfv|B16{er} ; ; evex m:5 p:0 l:x w:0 0x69 /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R, x:IE|PE
|
||||
VCVTPS2IBS ; Vfv{K}{z},Wfv|B32{er} ; ; evex m:5 p:1 l:x w:0 0x69 /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R, x:IE|PE
|
||||
VCVTNEBF162IBS ; Vfv{K}{z},Wfv|B16 ; ; evex m:5 p:3 l:x w:0 0x69 /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E4, w:W|R|R
|
||||
VCVTTPH2IUBS ; Vfv{K}{z},Wfv|B16{sae} ; ; evex m:5 p:0 l:x w:0 0x6A /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R
|
||||
VCVTTPS2IUBS ; Vfv{K}{z},Wfv|B32{sae} ; ; evex m:5 p:1 l:x w:0 0x6A /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R
|
||||
VCVTTPH2IUBS ; Vfv{K}{z},Wfv|B16{sae} ; ; evex m:5 p:0 l:x w:0 0x6A /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R, x:IE|PE
|
||||
VCVTTPS2IUBS ; Vfv{K}{z},Wfv|B32{sae} ; ; evex m:5 p:1 l:x w:0 0x6A /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R, x:IE|PE
|
||||
VCVTTNEBF162IUBS ; Vfv{K}{z},Wfv|B16 ; ; evex m:5 p:3 l:x w:0 0x6A /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E4, w:W|R|R
|
||||
VCVTPH2IUBS ; Vfv{K}{z},Wfv|B16{er} ; ; evex m:5 p:0 l:x w:0 0x6B /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R
|
||||
VCVTPS2IUBS ; Vfv{K}{z},Wfv|B32{er} ; ; evex m:5 p:1 l:x w:0 0x6B /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R
|
||||
VCVTPH2IUBS ; Vfv{K}{z},Wfv|B16{er} ; ; evex m:5 p:0 l:x w:0 0x6B /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R, x:IE|PE
|
||||
VCVTPS2IUBS ; Vfv{K}{z},Wfv|B32{er} ; ; evex m:5 p:1 l:x w:0 0x6B /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R, x:IE|PE
|
||||
VCVTNEBF162IUBS ; Vfv{K}{z},Wfv|B16 ; ; evex m:5 p:3 l:x w:0 0x6B /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E4, w:W|R|R
|
||||
VCVTTPS2UDQS ; Vfv{K}{z},Wfv|B32{sae} ; ; evex m:5 p:0 l:x w:0 0x6C /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R
|
||||
VCVTTPD2UDQS ; Vhv{K}{z},Wfv|B64{sae} ; ; evex m:5 p:0 l:x w:1 0x6C /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R
|
||||
VCVTTPS2UQQS ; Vfv{K}{z},Whv|B32{sae} ; ; evex m:5 p:1 l:x w:0 0x6C /r ; s:AVX102, t:AVX10SCONVERT, l:hv, e:E2, w:W|R|R
|
||||
VCVTTPD2UQQS ; Vfv{K}{z},Wfv|B64{sae} ; ; evex m:5 p:1 l:x w:1 0x6C /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R
|
||||
VCVTTSS2USIS ; Gy,Wss{sae} ; ; evex m:5 p:2 l:i w:x 0x6C /r ; s:AVX102, t:AVX10SCONVERT, l:t1s, e:E3NF, w:W|R, a:IWO64
|
||||
VCVTTSD2USIS ; Gy,Wsd{sae} ; ; evex m:5 p:3 l:i w:x 0x6C /r ; s:AVX102, t:AVX10SCONVERT, l:t1s, e:E3NF, w:W|R, a:IWO64
|
||||
VCVTTPS2DQS ; Vfv{K}{z},Wfv|B32{sae} ; ; evex m:5 p:0 l:x w:0 0x6D /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R
|
||||
VCVTTPD2DQS ; Vhv{K}{z},Wfv|B64{sae} ; ; evex m:5 p:0 l:x w:1 0x6D /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R
|
||||
VCVTTPS2QQS ; Vfv{K}{z},Whv|B32{sae} ; ; evex m:5 p:1 l:x w:0 0x6D /r ; s:AVX102, t:AVX10SCONVERT, l:hv, e:E2, w:W|R|R
|
||||
VCVTTPD2QQS ; Vfv{K}{z},Wfv|B64{sae} ; ; evex m:5 p:1 l:x w:1 0x6D /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R
|
||||
VCVTTSS2SIS ; Gy,Wss{sae} ; ; evex m:5 p:2 l:i w:x 0x6D /r ; s:AVX102, t:AVX10SCONVERT, l:t1s, e:E3NF, w:W|R, a:IWO64
|
||||
VCVTTSD2SIS ; Gy,Wsd{sae} ; ; evex m:5 p:3 l:i w:x 0x6D /r ; s:AVX102, t:AVX10SCONVERT, l:t1s, e:E3NF, w:W|R, a:IWO64
|
||||
VCVTTPS2UDQS ; Vfv{K}{z},Wfv|B32{sae} ; ; evex m:5 p:0 l:x w:0 0x6C /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R, x:IE|PE
|
||||
VCVTTPD2UDQS ; Vhv{K}{z},Wfv|B64{sae} ; ; evex m:5 p:0 l:x w:1 0x6C /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R, x:IE|PE
|
||||
VCVTTPS2UQQS ; Vfv{K}{z},Whv|B32{sae} ; ; evex m:5 p:1 l:x w:0 0x6C /r ; s:AVX102, t:AVX10SCONVERT, l:hv, e:E2, w:W|R|R, x:IE|PE
|
||||
VCVTTPD2UQQS ; Vfv{K}{z},Wfv|B64{sae} ; ; evex m:5 p:1 l:x w:1 0x6C /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R, x:IE|PE
|
||||
VCVTTSS2USIS ; Gy,Wss{sae} ; ; evex m:5 p:2 l:i w:x 0x6C /r ; s:AVX102, t:AVX10SCONVERT, l:t1s, e:E3NF, w:W|R, a:IWO64, x:IE|PE
|
||||
VCVTTSD2USIS ; Gy,Wsd{sae} ; ; evex m:5 p:3 l:i w:x 0x6C /r ; s:AVX102, t:AVX10SCONVERT, l:t1s, e:E3NF, w:W|R, a:IWO64, x:IE|PE
|
||||
VCVTTPS2DQS ; Vfv{K}{z},Wfv|B32{sae} ; ; evex m:5 p:0 l:x w:0 0x6D /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R, x:IE|PE
|
||||
VCVTTPD2DQS ; Vhv{K}{z},Wfv|B64{sae} ; ; evex m:5 p:0 l:x w:1 0x6D /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R, x:IE|PE
|
||||
VCVTTPS2QQS ; Vfv{K}{z},Whv|B32{sae} ; ; evex m:5 p:1 l:x w:0 0x6D /r ; s:AVX102, t:AVX10SCONVERT, l:hv, e:E2, w:W|R|R, x:IE|PE
|
||||
VCVTTPD2QQS ; Vfv{K}{z},Wfv|B64{sae} ; ; evex m:5 p:1 l:x w:1 0x6D /r ; s:AVX102, t:AVX10SCONVERT, l:fv, e:E2, w:W|R|R, x:IE|PE
|
||||
VCVTTSS2SIS ; Gy,Wss{sae} ; ; evex m:5 p:2 l:i w:x 0x6D /r ; s:AVX102, t:AVX10SCONVERT, l:t1s, e:E3NF, w:W|R, a:IWO64, x:IE|PE
|
||||
VCVTTSD2SIS ; Gy,Wsd{sae} ; ; evex m:5 p:3 l:i w:x 0x6D /r ; s:AVX102, t:AVX10SCONVERT, l:t1s, e:E3NF, w:W|R, a:IWO64, x:IE|PE
|
||||
|
||||
VMOVW ; Vdq,Mw ; ; evex m:5 p:1 l:0 w:i 0x6E /r:mem ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E9NF, w:W|R
|
||||
VMOVW ; Vdq,Rd ; ; evex m:5 p:1 l:0 w:i 0x6E /r:reg ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E9NF, w:W|R
|
||||
VMOVW ; Vdq,Ww ; ; evex m:5 p:2 l:0 w:0 0x6E /r ; s:AVX102, t:AVX10PARTCOPY, l:t1s16, e:E9NF, w:W|R
|
||||
|
||||
VMOVRSD ; Vfv{K}{z},Wfv ; ; evex m:5 p:2 l:x w:0 0x6F /r:mem ; s:MOVRS, t:DATAXFER, l:fvm, e:E4, w:W|R|R
|
||||
VMOVRSB ; Vfv{K}{z},Wfv ; ; evex m:5 p:3 l:x w:0 0x6F /r:mem ; s:MOVRS, t:DATAXFER, l:fvm, e:E4, w:W|R|R
|
||||
VMOVRSQ ; Vfv{K}{z},Wfv ; ; evex m:5 p:2 l:x w:1 0x6F /r:mem ; s:MOVRS, t:DATAXFER, l:fvm, e:E4, w:W|R|R
|
||||
VMOVRSW ; Vfv{K}{z},Wfv ; ; evex m:5 p:3 l:x w:1 0x6F /r:mem ; s:MOVRS, t:DATAXFER, l:fvm, e:E4, w:W|R|R
|
||||
|
||||
# 0x70 - 0x7F
|
||||
VCVTBIASPH2BF8S ; Vhv{K}{z},Hfv,Wfv|B16 ; ; evex m:5 p:0 l:x w:0 0x74 /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R|R
|
||||
VCVTNEPH2BF8S ; Vhv{K}{z},Wfv|B16 ; ; evex m:5 p:2 l:x w:0 0x74 /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R
|
||||
VCVTNE2PH2BF8S ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:5 p:3 l:x w:0 0x74 /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R|R
|
||||
VCVTTPH2UDQ ; Vfv{K}{z},Whv|B16{sae} ; ; evex m:5 p:0 l:x w:0 0x78 /r ; s:AVX512FP16, t:AVX512FP16, l:hv, e:E2, w:W|R|R
|
||||
VCVTTPH2UQQ ; Vfv{K}{z},Wqv|B16{sae} ; ; evex m:5 p:1 l:x w:0 0x78 /r ; s:AVX512FP16, t:AVX512FP16, l:qv, e:E2, w:W|R|R
|
||||
VCVTTSH2USI ; Gy,Wsh{sae} ; ; evex m:5 p:2 l:i w:0 0x78 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3NF, w:W|R, a:IWO64
|
||||
VCVTPH2UDQ ; Vfv{K}{z},Whv|B16{er} ; ; evex m:5 p:0 l:x w:0 0x79 /r ; s:AVX512FP16, t:AVX512FP16, l:hv, e:E2, w:W|R|R
|
||||
VCVTPH2UQQ ; Vfv{K}{z},Wqv|B16{er} ; ; evex m:5 p:1 l:x w:0 0x79 /r ; s:AVX512FP16, t:AVX512FP16, l:qv, e:E2, w:W|R|R
|
||||
VCVTSH2USI ; Gy,Wsh{er} ; ; evex m:5 p:2 l:i w:x 0x79 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3NF, w:W|R, a:IWO64
|
||||
VCVTUDQ2PH ; Vhv{K}{z},Wfv|B32{er} ; ; evex m:5 p:3 l:x w:0 0x7A /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R
|
||||
VCVTUQQ2PH ; Vqv{K}{z},Wfv|B64{er} ; ; evex m:5 p:3 l:x w:1 0x7A /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R
|
||||
VCVTTPH2QQ ; Vfv{K}{z},Wqv|B16{sae} ; ; evex m:5 p:1 l:x w:0 0x7A /r ; s:AVX512FP16, t:AVX512FP16, l:qv, e:E2, w:W|R|R
|
||||
VCVTPH2QQ ; Vfv{K}{z},Wqv|B16{er} ; ; evex m:5 p:1 l:x w:0 0x7B /r ; s:AVX512FP16, t:AVX512FP16, l:qv, e:E2, w:W|R|R
|
||||
VCVTUSI2SH ; Vdq,Hdq,Ey{er} ; ; evex m:5 p:2 l:i w:x 0x7B /r ; s:AVX512FP16, t:AVX512FP16, l:t1s, e:E3NF, w:W|R|R, a:IWO64
|
||||
VCVTTPH2UW ; Vfv{K}{z},Wfv|B16{sae} ; ; evex m:5 p:0 l:x w:0 0x7C /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R
|
||||
VCVTTPH2W ; Vfv{K}{z},Wfv|B16{sae} ; ; evex m:5 p:1 l:x w:0 0x7C /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R
|
||||
VCVTPH2UW ; Vfv{K}{z},Wfv|B16{er} ; ; evex m:5 p:0 l:x w:0 0x7D /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R
|
||||
VCVTPH2W ; Vfv{K}{z},Wfv|B16{er} ; ; evex m:5 p:1 l:x w:0 0x7D /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R
|
||||
VCVTW2PH ; Vfv{K}{z},Wfv|B16{er} ; ; evex m:5 p:2 l:x w:0 0x7D /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R
|
||||
VCVTUW2PH ; Vfv{K}{z},Wfv|B16{er} ; ; evex m:5 p:3 l:x w:0 0x7D /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R
|
||||
VCVTBIASPH2BF8S ; Vhv{K}{z},Hfv,Wfv|B16 ; ; evex m:5 p:0 l:x w:0 0x74 /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VCVTNEPH2BF8S ; Vhv{K}{z},Wfv|B16 ; ; evex m:5 p:2 l:x w:0 0x74 /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R, x:IE|OE|UE|PE|DE
|
||||
VCVTNE2PH2BF8S ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:5 p:3 l:x w:0 0x74 /r ; s:AVX102, t:AVX10CONVERT, l:fv, e:E4NF, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VCVTTPH2UDQ ; Vfv{K}{z},Whv|B16{sae} ; ; evex m:5 p:0 l:x w:0 0x78 /r ; s:AVX512FP16, t:AVX512FP16, l:hv, e:E2, w:W|R|R, x:IE|PE
|
||||
VCVTTPH2UQQ ; Vfv{K}{z},Wqv|B16{sae} ; ; evex m:5 p:1 l:x w:0 0x78 /r ; s:AVX512FP16, t:AVX512FP16, l:qv, e:E2, w:W|R|R, x:IE|PE
|
||||
VCVTTSH2USI ; Gy,Wsh{sae} ; ; evex m:5 p:2 l:i w:0 0x78 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3NF, w:W|R, a:IWO64, x:IE|PE
|
||||
VCVTPH2UDQ ; Vfv{K}{z},Whv|B16{er} ; ; evex m:5 p:0 l:x w:0 0x79 /r ; s:AVX512FP16, t:AVX512FP16, l:hv, e:E2, w:W|R|R, x:IE|PE
|
||||
VCVTPH2UQQ ; Vfv{K}{z},Wqv|B16{er} ; ; evex m:5 p:1 l:x w:0 0x79 /r ; s:AVX512FP16, t:AVX512FP16, l:qv, e:E2, w:W|R|R, x:IE|PE
|
||||
VCVTSH2USI ; Gy,Wsh{er} ; ; evex m:5 p:2 l:i w:x 0x79 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3NF, w:W|R, a:IWO64, x:IE|PE
|
||||
VCVTUDQ2PH ; Vhv{K}{z},Wfv|B32{er} ; ; evex m:5 p:3 l:x w:0 0x7A /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R, x:PE|OE
|
||||
VCVTUQQ2PH ; Vqv{K}{z},Wfv|B64{er} ; ; evex m:5 p:3 l:x w:1 0x7A /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R, x:PE|OE
|
||||
VCVTTPH2QQ ; Vfv{K}{z},Wqv|B16{sae} ; ; evex m:5 p:1 l:x w:0 0x7A /r ; s:AVX512FP16, t:AVX512FP16, l:qv, e:E2, w:W|R|R, x:IE|PE
|
||||
VCVTPH2QQ ; Vfv{K}{z},Wqv|B16{er} ; ; evex m:5 p:1 l:x w:0 0x7B /r ; s:AVX512FP16, t:AVX512FP16, l:qv, e:E2, w:W|R|R, x:IE|PE
|
||||
VCVTUSI2SH ; Vdq,Hdq,Ey{er} ; ; evex m:5 p:2 l:i w:x 0x7B /r ; s:AVX512FP16, t:AVX512FP16, l:t1s, e:E3NF, w:W|R|R, a:IWO64, x:IE|PE
|
||||
VCVTTPH2UW ; Vfv{K}{z},Wfv|B16{sae} ; ; evex m:5 p:0 l:x w:0 0x7C /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R, x:IE|PE
|
||||
VCVTTPH2W ; Vfv{K}{z},Wfv|B16{sae} ; ; evex m:5 p:1 l:x w:0 0x7C /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R, x:IE|PE
|
||||
VCVTPH2UW ; Vfv{K}{z},Wfv|B16{er} ; ; evex m:5 p:0 l:x w:0 0x7D /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R, x:IE|PE
|
||||
VCVTPH2W ; Vfv{K}{z},Wfv|B16{er} ; ; evex m:5 p:1 l:x w:0 0x7D /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R, x:IE|PE
|
||||
VCVTW2PH ; Vfv{K}{z},Wfv|B16{er} ; ; evex m:5 p:2 l:x w:0 0x7D /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R, x:PE
|
||||
VCVTUW2PH ; Vfv{K}{z},Wfv|B16{er} ; ; evex m:5 p:3 l:x w:0 0x7D /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R, x:PE|OE
|
||||
VMOVW ; Mw,Vdq ; ; evex m:5 p:1 l:0 w:i 0x7E /r:mem ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E9NF, w:W|R
|
||||
VMOVW ; Rd,Vdq ; ; evex m:5 p:1 l:0 w:i 0x7E /r:reg ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E9NF, w:W|R
|
||||
VMOVW ; Ww,Vdq ; ; evex m:5 p:2 l:0 w:0 0x7E /r ; s:AVX102, t:AVX10PARTCOPY, l:t1s16, e:E9NF, w:W|R
|
||||
|
||||
@ -4,17 +4,18 @@
|
||||
#
|
||||
|
||||
# 0x10 - 0x1F
|
||||
VCVTSH2SS ; Vdq{K}{z},Hdq,Wsh{sae} ; ; evex m:6 p:0 l:i w:0 0x13 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R
|
||||
VCVTPH2PSX ; Vfv{K}{z},Whv|B16{sae} ; ; evex m:6 p:1 l:x w:0 0x13 /r ; s:AVX512FP16, t:AVX512FP16, l:hv, e:E2, w:W|R|R
|
||||
VCVTSH2SS ; Vdq{K}{z},Hdq,Wsh{sae} ; ; evex m:6 p:0 l:i w:0 0x13 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R, x:IE|DE
|
||||
VCVTPH2PSX ; Vfv{K}{z},Whv|B16{sae} ; ; evex m:6 p:1 l:x w:0 0x13 /r ; s:AVX512FP16, t:AVX512FP16, l:hv, e:E2, w:W|R|R, x:IE|DE
|
||||
|
||||
# 0x20 - 0x2F
|
||||
VSCALEFPBF16 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:6 p:0 l:x w:0 0x2C /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:W|R|R|R
|
||||
VSCALEFPH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0x2C /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R
|
||||
VSCALEFSH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0x2D /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R
|
||||
VSCALEFPH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0x2C /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VSCALEFSH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0x2D /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
|
||||
# 0x40 - 0x4F
|
||||
VGETEXPPH ; Vfv{K}{z},Wfv|B16{sae} ; ; evex m:6 p:1 l:x w:0 0x42 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R
|
||||
VGETEXPSH ; Vdq{K}{z},Hdq,Wsh{sae} ; ; evex m:6 p:1 l:i w:0 0x43 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R
|
||||
VGETEXPPBF16 ; Vfv{K}{z},Wfv|B16 ; ; evex m:6 p:0 l:x w:0 0x42 /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:W|R|R
|
||||
VGETEXPPH ; Vfv{K}{z},Wfv|B16{sae} ; ; evex m:6 p:1 l:x w:0 0x42 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R, x:IE|DE
|
||||
VGETEXPSH ; Vdq{K}{z},Hdq,Wsh{sae} ; ; evex m:6 p:1 l:i w:0 0x43 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R, x:IE|DE
|
||||
VRCPPBF16 ; Vfv{K}{z},Wfv|B16 ; ; evex m:6 p:0 l:x w:0 0x4C /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:W|R|R
|
||||
VRCPPH ; Vfv{K}{z},Wfv|B16 ; ; evex m:6 p:1 l:x w:0 0x4C /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E4, w:W|R|R
|
||||
VRCPSH ; Vdq{K}{z},Hdq,Wsh ; ; evex m:6 p:1 l:i w:0 0x4D /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E10, w:W|R|R|R
|
||||
@ -23,61 +24,61 @@ VRSQRTPH ; Vfv{K}{z},Wfv|B16 ; ; evex m:6 p:1 l:x w:0
|
||||
VRSQRTSH ; Vdq{K}{z},Hdq,Wsh ; ; evex m:6 p:1 l:i w:0 0x4F /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E10, w:W|R|R|R
|
||||
|
||||
# 0x50 - 0x5F
|
||||
VFMADDCPH ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:6 p:2 l:x w:0 0x56 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E4S, w:RW|R|R|R
|
||||
VFCMADDCPH ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:6 p:3 l:x w:0 0x56 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E4S, w:RW|R|R|R
|
||||
VFMADDCSH ; Vdq{K}{z},Hdq,Wd{er} ; ; evex m:6 p:2 l:i w:0 0x57 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s, e:E10S, w:RW|R|R|R
|
||||
VFCMADDCSH ; Vdq{K}{z},Hdq,Wd{er} ; ; evex m:6 p:3 l:i w:0 0x57 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s, e:E10S, w:RW|R|R|R
|
||||
VFMADDCPH ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:6 p:2 l:x w:0 0x56 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E4S, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFCMADDCPH ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:6 p:3 l:x w:0 0x56 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E4S, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFMADDCSH ; Vdq{K}{z},Hdq,Wd{er} ; ; evex m:6 p:2 l:i w:0 0x57 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s, e:E10S, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFCMADDCSH ; Vdq{K}{z},Hdq,Wd{er} ; ; evex m:6 p:3 l:i w:0 0x57 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s, e:E10S, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
|
||||
# 0x90 - 0x9F
|
||||
VFMADDSUB132PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0x96 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
|
||||
VFMSUBADD132PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0x97 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
|
||||
VFMADDSUB132PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0x96 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFMSUBADD132PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0x97 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFMADD132NEPBF16 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:6 p:0 l:x w:0 0x98 /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:RW|R|R|R
|
||||
VFMADD132PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0x98 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
|
||||
VFMADD132SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0x99 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R
|
||||
VFMADD132PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0x98 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFMADD132SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0x99 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFMSUB132NEPBF16 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:6 p:0 l:x w:0 0x9A /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:RW|R|R|R
|
||||
VFMSUB132PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0x9A /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
|
||||
VFMSUB132SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0x9B /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R
|
||||
VFMSUB132PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0x9A /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFMSUB132SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0x9B /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFNMADD132NEPBF16 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:6 p:0 l:x w:0 0x9C /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:RW|R|R|R
|
||||
VFNMADD132PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0x9C /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
|
||||
VFNMADD132SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0x9D /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R
|
||||
VFNMADD132PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0x9C /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFNMADD132SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0x9D /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFNMSUB132NEPBF16 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:6 p:0 l:x w:0 0x9E /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:RW|R|R|R
|
||||
VFNMSUB132PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0x9E /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
|
||||
VFNMSUB132SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0x9F /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R
|
||||
VFNMSUB132PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0x9E /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFNMSUB132SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0x9F /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
|
||||
# 0xA0 - 0xAF
|
||||
VFMADDSUB213PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xA6 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
|
||||
VFMSUBADD213PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xA7 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
|
||||
VFMADDSUB213PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xA6 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFMSUBADD213PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xA7 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFMADD213NEPBF16 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:6 p:0 l:x w:0 0xA8 /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:RW|R|R|R
|
||||
VFMADD213PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xA8 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
|
||||
VFMADD213SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0xA9 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R
|
||||
VFMADD213PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xA8 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFMADD213SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0xA9 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFMSUB213NEPBF16 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:6 p:0 l:x w:0 0xAA /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:RW|R|R|R
|
||||
VFMSUB213PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xAA /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
|
||||
VFMSUB213SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0xAB /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R
|
||||
VFMSUB213PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xAA /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFMSUB213SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0xAB /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFNMADD213NEPBF16 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:6 p:0 l:x w:0 0xAC /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:RW|R|R|R
|
||||
VFNMADD213PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xAC /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
|
||||
VFNMADD213SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0xAD /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R
|
||||
VFNMADD213PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xAC /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFNMADD213SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0xAD /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFNMSUB213NEPBF16 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:6 p:0 l:x w:0 0xAE /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:RW|R|R|R
|
||||
VFNMSUB213PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xAE /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
|
||||
VFNMSUB213SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0xAF /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R
|
||||
VFNMSUB213PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xAE /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFNMSUB213SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0xAF /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
|
||||
# 0xB0 - 0xBF
|
||||
VFMADDSUB231PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xB6 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
|
||||
VFMSUBADD231PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xB7 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
|
||||
VFMADDSUB231PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xB6 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFMSUBADD231PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xB7 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFMADD231NEPBF16 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:6 p:0 l:x w:0 0xB8 /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:RW|R|R|R
|
||||
VFMADD231PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xB8 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
|
||||
VFMADD231SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0xB9 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R
|
||||
VFMADD231PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xB8 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFMADD231SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0xB9 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFMSUB231NEPBF16 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:6 p:0 l:x w:0 0xBA /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:RW|R|R|R
|
||||
VFMSUB231PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xBA /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
|
||||
VFMSUB231SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0xBB /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R
|
||||
VFMSUB231PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xBA /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFMSUB231SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0xBB /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFNMADD231NEPBF16 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:6 p:0 l:x w:0 0xBC /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:RW|R|R|R
|
||||
VFNMADD231PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xBC /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
|
||||
VFNMADD231SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0xBD /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R
|
||||
VFNMADD231PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xBC /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFNMADD231SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0xBD /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFNMSUB231NEPBF16 ; Vfv{K}{z},Hfv,Wfv|B16 ; ; evex m:6 p:0 l:x w:0 0xBE /r ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:RW|R|R|R
|
||||
VFNMSUB231PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xBE /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R
|
||||
VFNMSUB231SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0xBF /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R
|
||||
VFNMSUB231PH ; Vfv{K}{z},Hfv,Wfv|B16{er} ; ; evex m:6 p:1 l:x w:0 0xBE /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFNMSUB231SH ; Vdq{K}{z},Hdq,Wsh{er} ; ; evex m:6 p:1 l:i w:0 0xBF /r ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:RW|R|R|R, x:IE|OE|UE|PE|DE
|
||||
|
||||
# 0xD0 - 0xD7
|
||||
VFMULCPH ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:6 p:2 l:x w:0 0xD6 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E4S, w:W|R|R|R
|
||||
VFCMULCPH ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:6 p:3 l:x w:0 0xD6 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E4S, w:W|R|R|R
|
||||
VFMULCSH ; Vdq{K}{z},Hdq,Wd{er} ; ; evex m:6 p:2 l:i w:0 0xD7 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s, e:E10S, w:W|R|R|R
|
||||
VFCMULCSH ; Vdq{K}{z},Hdq,Wd{er} ; ; evex m:6 p:3 l:i w:0 0xD7 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s, e:E10S, w:W|R|R|R
|
||||
VFMULCPH ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:6 p:2 l:x w:0 0xD6 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E4S, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFCMULCPH ; Vfv{K}{z},Hfv,Wfv|B32{er} ; ; evex m:6 p:3 l:x w:0 0xD6 /r ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E4S, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFMULCSH ; Vdq{K}{z},Hdq,Wd{er} ; ; evex m:6 p:2 l:i w:0 0xD7 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s, e:E10S, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFCMULCSH ; Vdq{K}{z},Hdq,Wd{er} ; ; evex m:6 p:3 l:i w:0 0xD7 /r ; s:AVX512FP16, t:AVX512FP16, l:t1s, e:E10S, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
|
||||
@ -3,5 +3,7 @@
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
#
|
||||
|
||||
UWRMSR ; Id,Rq ; MSR ; evex m:7 nf:0 p:2 l:0 w:0 0xF8 /0:reg id ; s:APX_F, t:USER_MSR, w:R|R|W, m:O64, v:vex
|
||||
URDMSR ; Rq,Id ; MSR ; evex m:7 nf:0 p:3 l:0 w:0 0xF8 /0:reg id ; s:APX_F, t:USER_MSR, w:W|R|R, m:O64, v:vex
|
||||
WRMSRNS ; Id,Rq ; MSR ; evex m:7 nf:0 p:2 l:0 w:0 0xF6 /0:reg id ; s:MSR_IMM, t:SYSTEM, w:R|R|W, m:KERNEL|O64, v:vex
|
||||
RDMSR ; Rq,Id ; MSR ; evex m:7 nf:0 p:3 l:0 w:0 0xF6 /0:reg id ; s:MSR_IMM, t:SYSTEM, w:W|R|R, m:KERNEL|O64, v:vex
|
||||
UWRMSR ; Id,Rq ; MSR ; evex m:7 nf:0 p:2 l:0 w:0 0xF8 /0:reg id ; s:APX_F, t:USER_MSR, w:R|R|W, m:O64, v:vex
|
||||
URDMSR ; Rq,Id ; MSR ; evex m:7 nf:0 p:3 l:0 w:0 0xF8 /0:reg id ; s:APX_F, t:USER_MSR, w:W|R|R, m:O64, v:vex
|
||||
|
||||
@ -157,7 +157,8 @@ PREFETCHT1 ; Mb ; ; 0x0F 0x18 /2:m
|
||||
NOP ; Ev ; ; 0x0F 0x18 /2:reg ; s:PPRO, t:WIDENOP, w:N
|
||||
PREFETCHT2 ; Mb ; ; 0x0F 0x18 /3:mem ; s:SSE, t:PREFETCH, w:P
|
||||
NOP ; Ev ; ; 0x0F 0x18 /3:reg ; s:PPRO, t:WIDENOP, w:N
|
||||
NOP ; Ev ; ; 0x0F 0x18 /4 ; s:PPRO, t:WIDENOP, w:N
|
||||
PREFETCHRST2 ; Mb ; ; 0x0F 0x18 /4:mem ; s:MOVRS, t:PREFETCH, w:P
|
||||
NOP ; Ev ; ; 0x0F 0x18 /4:reg ; s:PPRO, t:WIDENOP, w:N
|
||||
NOP ; Ev ; ; 0x0F 0x18 /5 ; s:PPRO, t:WIDENOP, w:N
|
||||
NOP ; Ev ; ; 0x0F 0x18 /6 ; s:PPRO, t:WIDENOP, w:N
|
||||
NOP ; Ev ; ; 0x0F 0x18 /7 ; s:PPRO, t:WIDENOP, w:N
|
||||
@ -173,7 +174,8 @@ PREFETCHT1 ; Mb ; ; piti 0x0F 0x18 /2:m
|
||||
NOP ; Ev ; ; piti 0x0F 0x18 /2:reg ; s:PPRO, t:WIDENOP, w:N
|
||||
PREFETCHT2 ; Mb ; ; piti 0x0F 0x18 /3:mem ; s:SSE, t:PREFETCH, w:P
|
||||
NOP ; Ev ; ; piti 0x0F 0x18 /3:reg ; s:PPRO, t:WIDENOP, w:N
|
||||
NOP ; Ev ; ; piti 0x0F 0x18 /4 ; s:PPRO, t:WIDENOP, w:N
|
||||
PREFETCHRST2 ; Mb ; ; piti 0x0F 0x18 /4:mem ; s:MOVRS, t:PREFETCH, w:P
|
||||
NOP ; Ev ; ; piti 0x0F 0x18 /4:reg ; s:PPRO, t:WIDENOP, w:N
|
||||
NOP ; Ev ; ; piti 0x0F 0x18 /5 ; s:PPRO, t:WIDENOP, w:N
|
||||
PREFETCHIT1 ; Mb ; ;piti riprel 0x0F 0x18 /6:mem ; s:PREFETCHITI, t:PREFETCH, w:N, m:O64
|
||||
NOP ; Ev ; ; piti 0x0F 0x18 /6:mem ; s:PPRO, t:WIDENOP, w:N
|
||||
@ -264,26 +266,26 @@ MOVAPS ; Vps,Wps ; ; NP 0x0F 0x28 /r
|
||||
MOVAPD ; Vpd,Wpd ; ; 0x66 0x0F 0x28 /r ; s:SSE2, t:DATAXFER, w:W|R, e:1
|
||||
MOVAPS ; Wps,Vps ; ; NP 0x0F 0x29 /r ; s:SSE, t:DATAXFER, w:W|R, e:1
|
||||
MOVAPD ; Wpd,Vpd ; ; 0x66 0x0F 0x29 /r ; s:SSE2, t:DATAXFER, w:W|R, e:1
|
||||
CVTPI2PS ; Vq,Qq ; ; NP 0x0F 0x2A /r ; s:SSE, t:CONVERT, w:W|R
|
||||
CVTPI2PD ; Vpd,Qq ; ; 0x66 0x0F 0x2A /r ; s:SSE2, t:CONVERT, w:W|R
|
||||
CVTSI2SS ; Vss,Ey ; ; 0xF3 0x0F 0x2A /r ; s:SSE, t:CONVERT, w:W|R, e:3
|
||||
CVTSI2SD ; Vsd,Ey ; ; 0xF2 0x0F 0x2A /r ; s:SSE2, t:CONVERT, w:W|R, e:3
|
||||
CVTPI2PS ; Vq,Qq ; ; NP 0x0F 0x2A /r ; s:SSE, t:CONVERT, w:W|R, x:PE
|
||||
CVTPI2PD ; Vpd,Qq ; ; 0x66 0x0F 0x2A /r ; s:SSE2, t:CONVERT, w:W|R, x:PE
|
||||
CVTSI2SS ; Vss,Ey ; ; 0xF3 0x0F 0x2A /r ; s:SSE, t:CONVERT, w:W|R, e:3, x:PE
|
||||
CVTSI2SD ; Vsd,Ey ; ; 0xF2 0x0F 0x2A /r ; s:SSE2, t:CONVERT, w:W|R, e:3, x:PE
|
||||
MOVNTPS ; Mps,Vps ; ; NP 0x0F 0x2B /r:mem ; s:SSE, t:DATAXFER, w:W|R, e:1
|
||||
MOVNTPD ; Mpd,Vpd ; ; 0x66 0x0F 0x2B /r:mem ; s:SSE2, t:DATAXFER, w:W|R, e:1
|
||||
MOVNTSS ; Mss,Vss ; ; 0xF3 0x0F 0x2B /r:mem ; s:SSE4A, t:DATAXFER, w:W|R
|
||||
MOVNTSD ; Msd,Vsd ; ; 0xF2 0x0F 0x2B /r:mem ; s:SSE4A, t:DATAXFER, w:W|R
|
||||
CVTTPS2PI ; Pq,Wq ; ; NP 0x0F 0x2C /r ; s:SSE, t:CONVERT, w:W|R
|
||||
CVTTPD2PI ; Pq,Wpd ; ; 0x66 0x0F 0x2C /r ; s:SSE2, t:CONVERT, w:W|R
|
||||
CVTTSS2SI ; Gy,Wss ; ; 0xF3 0x0F 0x2C /r ; s:SSE, t:CONVERT, w:W|R, e:3
|
||||
CVTTSD2SI ; Gy,Wsd ; ; 0xF2 0x0F 0x2C /r ; s:SSE2, t:CONVERT, w:W|R, e:3
|
||||
CVTPS2PI ; Pq,Wq ; ; NP 0x0F 0x2D /r ; s:SSE, t:CONVERT, w:W|R
|
||||
CVTPD2PI ; Pq,Wpd ; ; 0x66 0x0F 0x2D /r ; s:SSE2, t:CONVERT, w:W|R
|
||||
CVTSS2SI ; Gy,Wss ; ; 0xF3 0x0F 0x2D /r ; s:SSE, t:CONVERT, w:W|R, e:3
|
||||
CVTSD2SI ; Gy,Wsd ; ; 0xF2 0x0F 0x2D /r ; s:SSE2, t:CONVERT, w:W|R, e:3
|
||||
UCOMISS ; Vss,Wss ; Fv ; NP 0x0F 0x2E /r ; s:SSE, t:SSE, w:R|R|W, f:COMIS
|
||||
UCOMISD ; Vsd,Wsd ; Fv ; 0x66 0x0F 0x2E /r ; s:SSE2, t:SSE2, w:R|R|W, f:COMIS, e:3
|
||||
COMISS ; Vss,Wss ; Fv ; NP 0x0F 0x2F /r ; s:SSE, t:SSE, w:R|R|W, f:COMIS, e:3
|
||||
COMISD ; Vsd,Wsd ; Fv ; 0x66 0x0F 0x2F /r ; s:SSE2, t:SSE2, w:R|R|W, f:COMIS, e:3
|
||||
CVTTPS2PI ; Pq,Wq ; ; NP 0x0F 0x2C /r ; s:SSE, t:CONVERT, w:W|R, x:IE|PE
|
||||
CVTTPD2PI ; Pq,Wpd ; ; 0x66 0x0F 0x2C /r ; s:SSE2, t:CONVERT, w:W|R, x:IE|PE
|
||||
CVTTSS2SI ; Gy,Wss ; ; 0xF3 0x0F 0x2C /r ; s:SSE, t:CONVERT, w:W|R, e:3, x:IE|PE
|
||||
CVTTSD2SI ; Gy,Wsd ; ; 0xF2 0x0F 0x2C /r ; s:SSE2, t:CONVERT, w:W|R, e:3, x:IE|PE
|
||||
CVTPS2PI ; Pq,Wq ; ; NP 0x0F 0x2D /r ; s:SSE, t:CONVERT, w:W|R, x:IE|PE
|
||||
CVTPD2PI ; Pq,Wpd ; ; 0x66 0x0F 0x2D /r ; s:SSE2, t:CONVERT, w:W|R, x:IE|PE
|
||||
CVTSS2SI ; Gy,Wss ; ; 0xF3 0x0F 0x2D /r ; s:SSE, t:CONVERT, w:W|R, e:3, x:IE|PE
|
||||
CVTSD2SI ; Gy,Wsd ; ; 0xF2 0x0F 0x2D /r ; s:SSE2, t:CONVERT, w:W|R, e:3, x:IE|PE
|
||||
UCOMISS ; Vss,Wss ; Fv ; NP 0x0F 0x2E /r ; s:SSE, t:SSE, w:R|R|W, f:COMIS, e:3, x:IE|DE
|
||||
UCOMISD ; Vsd,Wsd ; Fv ; 0x66 0x0F 0x2E /r ; s:SSE2, t:SSE2, w:R|R|W, f:COMIS, e:3, x:IE|DE
|
||||
COMISS ; Vss,Wss ; Fv ; NP 0x0F 0x2F /r ; s:SSE, t:SSE, w:R|R|W, f:COMIS, e:3, x:IE|DE
|
||||
COMISD ; Vsd,Wsd ; Fv ; 0x66 0x0F 0x2F /r ; s:SSE2, t:SSE2, w:R|R|W, f:COMIS, e:3, x:IE|DE
|
||||
|
||||
# 0x30 - 0x3F
|
||||
WRMSR ; ; EAX,EDX,ECX,MSR ; 0x0F 0x30 ; s:PENTIUMREAL, t:SYSTEM, w:R|R|R|W, a:SERIAL|NOREX2, m:KERNEL|NOV86, i:MSR
|
||||
@ -316,10 +318,10 @@ CMOVNLE ; Gv,Ev ; Fv ; 0x0F 0x4F /r
|
||||
# Note: for MOVMSKPS & MOVMSKPD, the Intel doc says the destination reg is y (32 or 64 bit).
|
||||
MOVMSKPS ; Gy,Ups ; ; NP 0x0F 0x50 /r:reg ; s:SSE, t:DATAXFER, w:W|R, e:7, a:D64
|
||||
MOVMSKPD ; Gy,Upd ; ; 0x66 0x0F 0x50 /r:reg ; s:SSE2, t:DATAXFER, w:W|R, e:7, a:D64
|
||||
SQRTPS ; Vps,Wps ; ; NP 0x0F 0x51 /r ; s:SSE, t:SSE, w:W|R, e:2
|
||||
SQRTPD ; Vpd,Wpd ; ; 0x66 0x0F 0x51 /r ; s:SSE2, t:SSE, w:W|R, e:2
|
||||
SQRTSS ; Vss,Wss ; ; 0xF3 0x0F 0x51 /r ; s:SSE, t:SSE, w:W|R, e:3
|
||||
SQRTSD ; Vsd,Wsd ; ; 0xF2 0x0F 0x51 /r ; s:SSE2, t:SSE, w:W|R, e:3
|
||||
SQRTPS ; Vps,Wps ; ; NP 0x0F 0x51 /r ; s:SSE, t:SSE, w:W|R, e:2, x:IE|PE|DE
|
||||
SQRTPD ; Vpd,Wpd ; ; 0x66 0x0F 0x51 /r ; s:SSE2, t:SSE, w:W|R, e:2, x:IE|PE|DE
|
||||
SQRTSS ; Vss,Wss ; ; 0xF3 0x0F 0x51 /r ; s:SSE, t:SSE, w:W|R, e:3, x:IE|PE|DE
|
||||
SQRTSD ; Vsd,Wsd ; ; 0xF2 0x0F 0x51 /r ; s:SSE2, t:SSE, w:W|R, e:3, x:IE|PE|DE
|
||||
RSQRTPS ; Vps,Wps ; ; NP 0x0F 0x52 /r ; s:SSE, t:SSE, w:W|R, e:4
|
||||
RSQRTSS ; Vss,Wss ; ; 0xF3 0x0F 0x52 /r ; s:SSE, t:SSE, w:W|R, e:5
|
||||
RCPPS ; Vps,Wps ; ; NP 0x0F 0x53 /r ; s:SSE, t:SSE, w:W|R, e:4
|
||||
@ -332,37 +334,37 @@ ORPS ; Vps,Wps ; ; NP 0x0F 0x56 /r
|
||||
ORPD ; Vpd,Wpd ; ; 0x66 0x0F 0x56 /r ; s:SSE2, t:LOGICAL_FP, w:RW|R, e:4
|
||||
XORPS ; Vps,Wps ; ; NP 0x0F 0x57 /r ; s:SSE, t:LOGICAL_FP, w:RW|R, e:4
|
||||
XORPD ; Vpd,Wpd ; ; 0x66 0x0F 0x57 /r ; s:SSE2, t:LOGICAL_FP, w:RW|R, e:4
|
||||
ADDPS ; Vps,Wps ; ; NP 0x0F 0x58 /r ; s:SSE, t:SSE, w:RW|R, e:2
|
||||
ADDPD ; Vpd,Wpd ; ; 0x66 0x0F 0x58 /r ; s:SSE2, t:SSE, w:RW|R, e:2
|
||||
ADDSS ; Vss,Wss ; ; 0xF3 0x0F 0x58 /r ; s:SSE, t:SSE, w:RW|R, e:3
|
||||
ADDSD ; Vsd,Wsd ; ; 0xF2 0x0F 0x58 /r ; s:SSE2, t:SSE, w:RW|R, e:3
|
||||
MULPS ; Vps,Wps ; ; NP 0x0F 0x59 /r ; s:SSE, t:SSE, w:RW|R, e:2
|
||||
MULPD ; Vpd,Wpd ; ; 0x66 0x0F 0x59 /r ; s:SSE2, t:SSE, w:RW|R, e:2
|
||||
MULSS ; Vss,Wss ; ; 0xF3 0x0F 0x59 /r ; s:SSE, t:SSE, w:RW|R, e:3
|
||||
MULSD ; Vsd,Wsd ; ; 0xF2 0x0F 0x59 /r ; s:SSE2, t:SSE, w:RW|R, e:3
|
||||
CVTPS2PD ; Vpd,Wq ; ; NP 0x0F 0x5A /r ; s:SSE2, t:CONVERT, w:W|R, e:3
|
||||
CVTPD2PS ; Vps,Wpd ; ; 0x66 0x0F 0x5A /r ; s:SSE2, t:CONVERT, w:W|R, e:2
|
||||
CVTSS2SD ; Vsd,Wss ; ; 0xF3 0x0F 0x5A /r ; s:SSE2, t:CONVERT, w:W|R, e:3
|
||||
CVTSD2SS ; Vss,Wsd ; ; 0xF2 0x0F 0x5A /r ; s:SSE2, t:CONVERT, w:W|R, e:3
|
||||
CVTDQ2PS ; Vps,Wdq ; ; NP 0x0F 0x5B /r ; s:SSE2, t:CONVERT, w:W|R, e:2
|
||||
CVTPS2DQ ; Vdq,Wps ; ; 0x66 0x0F 0x5B /r ; s:SSE2, t:CONVERT, w:W|R, e:2
|
||||
CVTTPS2DQ ; Vdq,Wps ; ; 0xF3 0x0F 0x5B /r ; s:SSE2, t:CONVERT, w:W|R, e:2
|
||||
SUBPS ; Vps,Wps ; ; NP 0x0F 0x5C /r ; s:SSE, t:SSE, w:RW|R, e:2
|
||||
SUBPD ; Vpd,Wpd ; ; 0x66 0x0F 0x5C /r ; s:SSE2, t:SSE, w:RW|R, e:2
|
||||
SUBSS ; Vss,Wss ; ; 0xF3 0x0F 0x5C /r ; s:SSE, t:SSE, w:RW|R, e:3
|
||||
SUBSD ; Vsd,Wsd ; ; 0xF2 0x0F 0x5C /r ; s:SSE2, t:SSE, w:RW|R, e:3
|
||||
MINPS ; Vps,Wps ; ; NP 0x0F 0x5D /r ; s:SSE, t:SSE, w:RW|R, e:2
|
||||
MINPD ; Vpd,Wpd ; ; 0x66 0x0F 0x5D /r ; s:SSE2, t:SSE, w:RW|R, e:2
|
||||
MINSS ; Vss,Wss ; ; 0xF3 0x0F 0x5D /r ; s:SSE, t:SSE, w:RW|R, e:3
|
||||
MINSD ; Vsd,Wsd ; ; 0xF2 0x0F 0x5D /r ; s:SSE2, t:SSE, w:RW|R, e:3
|
||||
DIVPS ; Vps,Wps ; ; NP 0x0F 0x5E /r ; s:SSE, t:SSE, w:RW|R, e:2
|
||||
DIVPD ; Vpd,Wpd ; ; 0x66 0x0F 0x5E /r ; s:SSE2, t:SSE, w:RW|R, e:2
|
||||
DIVSS ; Vss,Wss ; ; 0xF3 0x0F 0x5E /r ; s:SSE, t:SSE, w:RW|R, e:3
|
||||
DIVSD ; Vsd,Wsd ; ; 0xF2 0x0F 0x5E /r ; s:SSE2, t:SSE, w:RW|R, e:3
|
||||
MAXPS ; Vps,Wps ; ; NP 0x0F 0x5F /r ; s:SSE, t:SSE, w:RW|R, e:2
|
||||
MAXPD ; Vpd,Wpd ; ; 0x66 0x0F 0x5F /r ; s:SSE2, t:SSE, w:RW|R, e:2
|
||||
MAXSS ; Vss,Wss ; ; 0xF3 0x0F 0x5F /r ; s:SSE, t:SSE, w:RW|R, e:3
|
||||
MAXSD ; Vsd,Wsd ; ; 0xF2 0x0F 0x5F /r ; s:SSE2, t:SSE, w:RW|R, e:3
|
||||
ADDPS ; Vps,Wps ; ; NP 0x0F 0x58 /r ; s:SSE, t:SSE, w:RW|R, e:2, x:IE|OE|UE|PE|DE
|
||||
ADDPD ; Vpd,Wpd ; ; 0x66 0x0F 0x58 /r ; s:SSE2, t:SSE, w:RW|R, e:2, x:IE|OE|UE|PE|DE
|
||||
ADDSS ; Vss,Wss ; ; 0xF3 0x0F 0x58 /r ; s:SSE, t:SSE, w:RW|R, e:3, x:IE|OE|UE|PE|DE
|
||||
ADDSD ; Vsd,Wsd ; ; 0xF2 0x0F 0x58 /r ; s:SSE2, t:SSE, w:RW|R, e:3, x:IE|OE|UE|PE|DE
|
||||
MULPS ; Vps,Wps ; ; NP 0x0F 0x59 /r ; s:SSE, t:SSE, w:RW|R, e:2, x:IE|OE|UE|PE|DE
|
||||
MULPD ; Vpd,Wpd ; ; 0x66 0x0F 0x59 /r ; s:SSE2, t:SSE, w:RW|R, e:2, x:IE|OE|UE|PE|DE
|
||||
MULSS ; Vss,Wss ; ; 0xF3 0x0F 0x59 /r ; s:SSE, t:SSE, w:RW|R, e:3, x:IE|OE|UE|PE|DE
|
||||
MULSD ; Vsd,Wsd ; ; 0xF2 0x0F 0x59 /r ; s:SSE2, t:SSE, w:RW|R, e:3, x:IE|OE|UE|PE|DE
|
||||
CVTPS2PD ; Vpd,Wq ; ; NP 0x0F 0x5A /r ; s:SSE2, t:CONVERT, w:W|R, e:3, x:IE|DE
|
||||
CVTPD2PS ; Vps,Wpd ; ; 0x66 0x0F 0x5A /r ; s:SSE2, t:CONVERT, w:W|R, e:2, x:IE|OE|UE|PE|DE
|
||||
CVTSS2SD ; Vsd,Wss ; ; 0xF3 0x0F 0x5A /r ; s:SSE2, t:CONVERT, w:W|R, e:3, x:IE|DE
|
||||
CVTSD2SS ; Vss,Wsd ; ; 0xF2 0x0F 0x5A /r ; s:SSE2, t:CONVERT, w:W|R, e:3, x:IE|OE|UE|PE|DE
|
||||
CVTDQ2PS ; Vps,Wdq ; ; NP 0x0F 0x5B /r ; s:SSE2, t:CONVERT, w:W|R, e:2, x:PE
|
||||
CVTPS2DQ ; Vdq,Wps ; ; 0x66 0x0F 0x5B /r ; s:SSE2, t:CONVERT, w:W|R, e:2, x:IE|PE
|
||||
CVTTPS2DQ ; Vdq,Wps ; ; 0xF3 0x0F 0x5B /r ; s:SSE2, t:CONVERT, w:W|R, e:2, x:IE|PE
|
||||
SUBPS ; Vps,Wps ; ; NP 0x0F 0x5C /r ; s:SSE, t:SSE, w:RW|R, e:2, x:IE|OE|UE|PE|DE
|
||||
SUBPD ; Vpd,Wpd ; ; 0x66 0x0F 0x5C /r ; s:SSE2, t:SSE, w:RW|R, e:2, x:IE|OE|UE|PE|DE
|
||||
SUBSS ; Vss,Wss ; ; 0xF3 0x0F 0x5C /r ; s:SSE, t:SSE, w:RW|R, e:3, x:IE|OE|UE|PE|DE
|
||||
SUBSD ; Vsd,Wsd ; ; 0xF2 0x0F 0x5C /r ; s:SSE2, t:SSE, w:RW|R, e:3, x:IE|OE|UE|PE|DE
|
||||
MINPS ; Vps,Wps ; ; NP 0x0F 0x5D /r ; s:SSE, t:SSE, w:RW|R, e:2, x:IE|DE
|
||||
MINPD ; Vpd,Wpd ; ; 0x66 0x0F 0x5D /r ; s:SSE2, t:SSE, w:RW|R, e:2, x:IE|DE
|
||||
MINSS ; Vss,Wss ; ; 0xF3 0x0F 0x5D /r ; s:SSE, t:SSE, w:RW|R, e:3, x:IE|DE
|
||||
MINSD ; Vsd,Wsd ; ; 0xF2 0x0F 0x5D /r ; s:SSE2, t:SSE, w:RW|R, e:3, x:IE|DE
|
||||
DIVPS ; Vps,Wps ; ; NP 0x0F 0x5E /r ; s:SSE, t:SSE, w:RW|R, e:2, x:IE|OE|UE|PE|DE|ZE
|
||||
DIVPD ; Vpd,Wpd ; ; 0x66 0x0F 0x5E /r ; s:SSE2, t:SSE, w:RW|R, e:2, x:IE|OE|UE|PE|DE|ZE
|
||||
DIVSS ; Vss,Wss ; ; 0xF3 0x0F 0x5E /r ; s:SSE, t:SSE, w:RW|R, e:3, x:IE|OE|UE|PE|DE|ZE
|
||||
DIVSD ; Vsd,Wsd ; ; 0xF2 0x0F 0x5E /r ; s:SSE2, t:SSE, w:RW|R, e:3, x:IE|OE|UE|PE|DE|ZE
|
||||
MAXPS ; Vps,Wps ; ; NP 0x0F 0x5F /r ; s:SSE, t:SSE, w:RW|R, e:2, x:IE|DE
|
||||
MAXPD ; Vpd,Wpd ; ; 0x66 0x0F 0x5F /r ; s:SSE2, t:SSE, w:RW|R, e:2, x:IE|DE
|
||||
MAXSS ; Vss,Wss ; ; 0xF3 0x0F 0x5F /r ; s:SSE, t:SSE, w:RW|R, e:3, x:IE|DE
|
||||
MAXSD ; Vsd,Wsd ; ; 0xF2 0x0F 0x5F /r ; s:SSE2, t:SSE, w:RW|R, e:3, x:IE|DE
|
||||
|
||||
# 0x60 - 0x6F
|
||||
PUNPCKLBW ; Pq,Qd ; ; NP 0x0F 0x60 /r ; s:MMX, t:MMX, w:RW|R
|
||||
@ -435,10 +437,10 @@ EXTRQ ; Uq,Ib,Ib ; ; 0x66 0x0F 0x78 /0 i
|
||||
VMWRITE ; Gy,Ey ; Fv ; NP 0x0F 0x79 /r ; s:VTX, t:VTX, w:R|R|W, f:VMX, a:F64, m:VMXROOT
|
||||
EXTRQ ; Vdq,Uq ; ; 0x66 0x0F 0x79 /r:reg ; s:SSE4A, t:BITBYTE, w:W|R
|
||||
INSERTQ ; Vdq,Udq ; ; 0xF2 0x0F 0x79 /r:reg ; s:SSE4A, t:BITBYTE, w:W|R
|
||||
HADDPD ; Vpd,Wpd ; ; 0x66 0x0F 0x7C /r ; s:SSE3, t:SSE, w:RW|R, e:2
|
||||
HADDPS ; Vps,Wps ; ; 0xF2 0x0F 0x7C /r ; s:SSE3, t:SSE, w:RW|R, e:2
|
||||
HSUBPD ; Vpd,Wpd ; ; 0x66 0x0F 0x7D /r ; s:SSE3, t:SSE, w:RW|R, e:2
|
||||
HSUBPS ; Vps,Wps ; ; 0xF2 0x0F 0x7D /r ; s:SSE3, t:SSE, w:RW|R, e:2
|
||||
HADDPD ; Vpd,Wpd ; ; 0x66 0x0F 0x7C /r ; s:SSE3, t:SSE, w:RW|R, e:2, x:IE|OE|UE|PE|DE
|
||||
HADDPS ; Vps,Wps ; ; 0xF2 0x0F 0x7C /r ; s:SSE3, t:SSE, w:RW|R, e:2, x:IE|OE|UE|PE|DE
|
||||
HSUBPD ; Vpd,Wpd ; ; 0x66 0x0F 0x7D /r ; s:SSE3, t:SSE, w:RW|R, e:2, x:IE|OE|UE|PE|DE
|
||||
HSUBPS ; Vps,Wps ; ; 0xF2 0x0F 0x7D /r ; s:SSE3, t:SSE, w:RW|R, e:2, x:IE|OE|UE|PE|DE
|
||||
MOVD ; Ey,Pd ; ; NP 0x0F 0x7E /r ; s:MMX, t:DATAXFER, w:W|R
|
||||
MOVQ ; Ey,Pq ; ; rexw NP 0x0F 0x7E /r ; s:MMX, t:DATAXFER, w:W|R
|
||||
MOVD ; Ey,Vdq ; ; 0x66 0x0F 0x7E /r ; s:SSE2, t:DATAXFER, w:W|R, e:5
|
||||
@ -562,10 +564,10 @@ MOVSX ; Gv,Ew ; ; 0x0F 0xBF /r
|
||||
# 0xC0 - 0xCF
|
||||
XADD ; Eb,Gb ; Fv ; 0x0F 0xC0 /r ; s:I486REAL, t:SEMAPHORE, w:RW|RW|W, f:ARITH, p:LOCK|HLE
|
||||
XADD ; Ev,Gv ; Fv ; 0x0F 0xC1 /r ; s:I486REAL, t:SEMAPHORE, w:RW|RW|W, f:ARITH, p:LOCK|HLE
|
||||
CMPPS ; Vps,Wps,Ib ; ; NP 0x0F 0xC2 /r ib ; s:SSE, t:SSE, w:RW|R|R, e:2
|
||||
CMPPD ; Vpd,Wpd,Ib ; ; 0x66 0x0F 0xC2 /r ib ; s:SSE2, t:SSE, w:RW|R|R, e:2
|
||||
CMPSS ; Vss,Wss,Ib ; ; 0xF3 0x0F 0xC2 /r ib ; s:SSE, t:SSE, w:RW|R|R, e:3
|
||||
CMPSD ; Vsd,Wsd,Ib ; ; 0xF2 0x0F 0xC2 /r ib ; s:SSE2, t:SSE, w:RW|R|R, e:3
|
||||
CMPPS ; Vps,Wps,Ib ; ; NP 0x0F 0xC2 /r ib ; s:SSE, t:SSE, w:RW|R|R, e:2, x:IE|DE
|
||||
CMPPD ; Vpd,Wpd,Ib ; ; 0x66 0x0F 0xC2 /r ib ; s:SSE2, t:SSE, w:RW|R|R, e:2, x:IE|DE
|
||||
CMPSS ; Vss,Wss,Ib ; ; 0xF3 0x0F 0xC2 /r ib ; s:SSE, t:SSE, w:RW|R|R, e:3, x:IE|DE
|
||||
CMPSD ; Vsd,Wsd,Ib ; ; 0xF2 0x0F 0xC2 /r ib ; s:SSE2, t:SSE, w:RW|R|R, e:3, x:IE|DE
|
||||
MOVNTI ; My,Gy ; ; NP 0x0F 0xC3 /r:mem ; s:SSE2, t:DATAXFER, w:W|R
|
||||
PINSRW ; Pq,Rd,Ib ; ; NP 0x0F 0xC4 /r:reg ib ; s:MMX, t:MMX, w:RW|R|R
|
||||
PINSRW ; Pq,Mw,Ib ; ; NP 0x0F 0xC4 /r:mem ib ; s:MMX, t:MMX, w:RW|R|R
|
||||
@ -604,8 +606,8 @@ BSWAP ; Zv ; ; 0x0F 0xCE
|
||||
BSWAP ; Zv ; ; 0x0F 0xCF ; s:I486REAL, t:DATAXFER, w:RW
|
||||
|
||||
# 0xD0 - 0xDF
|
||||
ADDSUBPD ; Vpd,Wpd ; ; 0x66 0x0F 0xD0 /r ; s:SSE3, t:SSE, w:RW|R, e:2
|
||||
ADDSUBPS ; Vps,Wps ; ; 0xF2 0x0F 0xD0 /r ; s:SSE3, t:SSE, w:RW|R, e:2
|
||||
ADDSUBPD ; Vpd,Wpd ; ; 0x66 0x0F 0xD0 /r ; s:SSE3, t:SSE, w:RW|R, e:2, x:IE|OE|UE|PE|DE
|
||||
ADDSUBPS ; Vps,Wps ; ; 0xF2 0x0F 0xD0 /r ; s:SSE3, t:SSE, w:RW|R, e:2, x:IE|OE|UE|PE|DE
|
||||
PSRLW ; Pq,Qq ; ; NP 0x0F 0xD1 /r ; s:MMX, t:MMX, w:RW|R
|
||||
PSRLW ; Vx,Wx ; ; 0x66 0x0F 0xD1 /r ; s:SSE2, t:SSE, w:RW|R, e:4
|
||||
PSRLD ; Pq,Qq ; ; NP 0x0F 0xD2 /r ; s:MMX, t:MMX, w:RW|R
|
||||
@ -651,9 +653,9 @@ PMULHUW ; Pq,Qq ; ; NP 0x0F 0xE4 /r
|
||||
PMULHUW ; Vx,Wx ; ; 0x66 0x0F 0xE4 /r ; s:SSE2, t:SSE, w:RW|R, e:4
|
||||
PMULHW ; Pq,Qq ; ; NP 0x0F 0xE5 /r ; s:MMX, t:MMX, w:RW|R
|
||||
PMULHW ; Vx,Wx ; ; 0x66 0x0F 0xE5 /r ; s:SSE2, t:SSE, w:RW|R, e:4
|
||||
CVTTPD2DQ ; Vx,Wpd ; ; 0x66 0x0F 0xE6 /r ; s:SSE2, t:CONVERT, w:W|R, e:2
|
||||
CVTTPD2DQ ; Vx,Wpd ; ; 0x66 0x0F 0xE6 /r ; s:SSE2, t:CONVERT, w:W|R, e:2, x:IE|PE
|
||||
CVTDQ2PD ; Vx,Wq ; ; 0xF3 0x0F 0xE6 /r ; s:SSE2, t:CONVERT, w:W|R, e:5
|
||||
CVTPD2DQ ; Vx,Wpd ; ; 0xF2 0x0F 0xE6 /r ; s:SSE2, t:CONVERT, w:W|R, e:2
|
||||
CVTPD2DQ ; Vx,Wpd ; ; 0xF2 0x0F 0xE6 /r ; s:SSE2, t:CONVERT, w:W|R, e:2, x:IE|PE
|
||||
MOVNTQ ; Mq,Pq ; ; NP 0x0F 0xE7 /r:mem ; s:MMX, t:DATAXFER, w:W|R
|
||||
MOVNTDQ ; Mx,Vx ; ; 0x66 0x0F 0xE7 /r:mem ; s:SSE2, t:DATAXFER, w:W|R, e:1
|
||||
PSUBSB ; Pq,Qq ; ; NP 0x0F 0xE8 /r ; s:MMX, t:MMX, w:RW|R
|
||||
|
||||
@ -86,6 +86,9 @@ INVEPT ; Gy,Mdq ; Fv ; 0x66 0x0F 0x
|
||||
INVVPID ; Gy,Mdq ; Fv ; 0x66 0x0F 0x38 0x81 /r:mem ; s:VTX, t:VTX, w:R|R|W, f:VMX, a:F64|SERIAL|NOREX2, m:VMXROOT
|
||||
INVPCID ; Gy,Mdq ; ; 0x66 0x0F 0x38 0x82 /r:mem ; s:INVPCID, t:MISC, w:R|R, a:F64|NOREX2, m:KERNEL|NOV86
|
||||
|
||||
MOVRS ; Gb,Mb ; ; 0x0F 0x38 0x8A /r:mem ; s:MOVRS, t:DATAXFER, w:W|R, a:NOREP, m:O64
|
||||
MOVRS ; Gv,Mv ; ; 0x0F 0x38 0x8B /r:mem ; s:MOVRS, t:DATAXFER, w:W|R, a:NOREP, m:O64
|
||||
|
||||
# 0x90 - 0x9F
|
||||
|
||||
# 0xA0 - 0xAF
|
||||
|
||||
@ -4,10 +4,10 @@
|
||||
#
|
||||
|
||||
# 0x00 - 0x0F
|
||||
ROUNDPS ; Vx,Wx,Ib ; ; 0x66 0x0F 0x3A 0x08 /r ib ; s:SSE4, t:SSE, w:W|R|R, e:2, a:NOREX2
|
||||
ROUNDPD ; Vx,Wx,Ib ; ; 0x66 0x0F 0x3A 0x09 /r ib ; s:SSE4, t:SSE, w:W|R|R, e:2, a:NOREX2
|
||||
ROUNDSS ; Vss,Wss,Ib ; ; 0x66 0x0F 0x3A 0x0A /r ib ; s:SSE4, t:SSE, w:W|R|R, e:3, a:NOREX2
|
||||
ROUNDSD ; Vsd,Wsd,Ib ; ; 0x66 0x0F 0x3A 0x0B /r ib ; s:SSE4, t:SSE, w:W|R|R, e:3, a:NOREX2
|
||||
ROUNDPS ; Vx,Wx,Ib ; ; 0x66 0x0F 0x3A 0x08 /r ib ; s:SSE4, t:SSE, w:W|R|R, e:2, a:NOREX2, x:IE|PE
|
||||
ROUNDPD ; Vx,Wx,Ib ; ; 0x66 0x0F 0x3A 0x09 /r ib ; s:SSE4, t:SSE, w:W|R|R, e:2, a:NOREX2, x:IE|PE
|
||||
ROUNDSS ; Vss,Wss,Ib ; ; 0x66 0x0F 0x3A 0x0A /r ib ; s:SSE4, t:SSE, w:W|R|R, e:3, a:NOREX2, x:IE|PE
|
||||
ROUNDSD ; Vsd,Wsd,Ib ; ; 0x66 0x0F 0x3A 0x0B /r ib ; s:SSE4, t:SSE, w:W|R|R, e:3, a:NOREX2, x:IE|PE
|
||||
BLENDPS ; Vx,Wx,Ib ; ; 0x66 0x0F 0x3A 0x0C /r ib ; s:SSE4, t:SSE, w:RW|R|R, e:4, a:NOREX2
|
||||
BLENDPD ; Vx,Wx,Ib ; ; 0x66 0x0F 0x3A 0x0D /r ib ; s:SSE4, t:SSE, w:RW|R|R, e:4, a:NOREX2
|
||||
PBLENDW ; Vx,Wx,Ib ; ; 0x66 0x0F 0x3A 0x0E /r ib ; s:SSE4, t:SSE, w:RW|R|R, e:4, a:NOREX2
|
||||
@ -37,8 +37,8 @@ PINSRQ ; Vdq,Eq,Ib ; ; rexw 0x66 0x0F 0x
|
||||
# 0x30 - 0x3F
|
||||
|
||||
# 0x40 - 0x4F
|
||||
DPPS ; Vx,Wx,Ib ; ; 0x66 0x0F 0x3A 0x40 /r ib ; s:SSE4, t:SSE, w:RW|R|R, e:2, a:NOREX2
|
||||
DPPD ; Vdq,Wdq,Ib ; ; 0x66 0x0F 0x3A 0x41 /r ib ; s:SSE4, t:SSE, w:RW|R|R, e:2, a:NOREX2
|
||||
DPPS ; Vx,Wx,Ib ; ; 0x66 0x0F 0x3A 0x40 /r ib ; s:SSE4, t:SSE, w:RW|R|R, e:2, a:NOREX2, x:IE|OE|UE|PE|DE
|
||||
DPPD ; Vdq,Wdq,Ib ; ; 0x66 0x0F 0x3A 0x41 /r ib ; s:SSE4, t:SSE, w:RW|R|R, e:2, a:NOREX2, x:IE|OE|UE|PE|DE
|
||||
MPSADBW ; Vdq,Wdq,Ib ; ; 0x66 0x0F 0x3A 0x42 /r ib ; s:SSE4, t:SSE, w:RW|R|R, e:4, a:NOREX2
|
||||
PCLMULQDQ ; Vdq,Wdq,Ib ; ; 0x66 0x0F 0x3A 0x44 /r ib ; s:PCLMULQDQ, t:PCLMULQDQ, w:RW|R|R, e:4, a:NOREX2
|
||||
|
||||
|
||||
@ -42,18 +42,18 @@ VMOVAPS ; Vx,Wx ; ; vex m:1 p:0 l:x w:i
|
||||
VMOVAPD ; Vx,Wx ; ; vex m:1 p:1 l:x w:i 0x28 /r ; s:AVX, t:DATAXFER, w:W|R, e:1
|
||||
VMOVAPS ; Wx,Vx ; ; vex m:1 p:0 l:x w:i 0x29 /r ; s:AVX, t:DATAXFER, w:W|R, e:1
|
||||
VMOVAPD ; Wx,Vx ; ; vex m:1 p:1 l:x w:i 0x29 /r ; s:AVX, t:DATAXFER, w:W|R, e:1
|
||||
VCVTSI2SS ; Vss,Hss,Ey ; ; vex m:1 p:2 l:i w:x 0x2A /r ; s:AVX, t:CONVERT, w:W|R|R, e:3, a:IWO64
|
||||
VCVTSI2SD ; Vsd,Hsd,Ey ; ; vex m:1 p:3 l:i w:x 0x2A /r ; s:AVX, t:CONVERT, w:W|R|R, e:3, a:IWO64
|
||||
VCVTSI2SS ; Vss,Hss,Ey ; ; vex m:1 p:2 l:i w:x 0x2A /r ; s:AVX, t:CONVERT, w:W|R|R, e:3, a:IWO64, x:PE
|
||||
VCVTSI2SD ; Vsd,Hsd,Ey ; ; vex m:1 p:3 l:i w:x 0x2A /r ; s:AVX, t:CONVERT, w:W|R|R, e:3, a:IWO64, x:PE
|
||||
VMOVNTPS ; Mx,Vx ; ; vex m:1 p:0 l:x w:i 0x2B /r:mem ; s:AVX, t:AVX, w:W|R, e:1
|
||||
VMOVNTPD ; Mx,Vx ; ; vex m:1 p:1 l:x w:i 0x2B /r:mem ; s:AVX, t:AVX, w:W|R, e:1
|
||||
VCVTTSS2SI ; Gy,Wss ; ; vex m:1 p:2 l:i w:x 0x2C /r ; s:AVX, t:CONVERT, w:W|R, e:3, a:IWO64
|
||||
VCVTTSD2SI ; Gy,Wsd ; ; vex m:1 p:3 l:i w:x 0x2C /r ; s:AVX, t:CONVERT, w:W|R, e:3, a:IWO64
|
||||
VCVTSS2SI ; Gy,Wss ; ; vex m:1 p:2 l:i w:x 0x2D /r ; s:AVX, t:CONVERT, w:W|R, e:3, a:IWO64
|
||||
VCVTSD2SI ; Gy,Wsd ; ; vex m:1 p:3 l:i w:x 0x2D /r ; s:AVX, t:CONVERT, w:W|R, e:3, a:IWO64
|
||||
VUCOMISS ; Vss,Wss ; Fv ; vex m:1 p:0 l:i w:i 0x2E /r ; s:AVX, t:AVX, w:R|R|W, f:COMIS, e:3
|
||||
VUCOMISD ; Vsd,Wsd ; Fv ; vex m:1 p:1 l:i w:i 0x2E /r ; s:AVX, t:AVX, w:R|R|W, f:COMIS, e:3
|
||||
VCOMISS ; Vss,Wss ; Fv ; vex m:1 p:0 l:i w:i 0x2F /r ; s:AVX, t:AVX, w:R|R|W, f:COMIS, e:3
|
||||
VCOMISD ; Vsd,Wsd ; Fv ; vex m:1 p:1 l:i w:i 0x2F /r ; s:AVX, t:AVX, w:R|R|W, f:COMIS, e:3
|
||||
VCVTTSS2SI ; Gy,Wss ; ; vex m:1 p:2 l:i w:x 0x2C /r ; s:AVX, t:CONVERT, w:W|R, e:3, a:IWO64, x:IE|PE
|
||||
VCVTTSD2SI ; Gy,Wsd ; ; vex m:1 p:3 l:i w:x 0x2C /r ; s:AVX, t:CONVERT, w:W|R, e:3, a:IWO64, x:IE|PE
|
||||
VCVTSS2SI ; Gy,Wss ; ; vex m:1 p:2 l:i w:x 0x2D /r ; s:AVX, t:CONVERT, w:W|R, e:3, a:IWO64, x:IE|PE
|
||||
VCVTSD2SI ; Gy,Wsd ; ; vex m:1 p:3 l:i w:x 0x2D /r ; s:AVX, t:CONVERT, w:W|R, e:3, a:IWO64, x:IE|PE
|
||||
VUCOMISS ; Vss,Wss ; Fv ; vex m:1 p:0 l:i w:i 0x2E /r ; s:AVX, t:AVX, w:R|R|W, f:COMIS, e:3, x:IE|DE
|
||||
VUCOMISD ; Vsd,Wsd ; Fv ; vex m:1 p:1 l:i w:i 0x2E /r ; s:AVX, t:AVX, w:R|R|W, f:COMIS, e:3, x:IE|DE
|
||||
VCOMISS ; Vss,Wss ; Fv ; vex m:1 p:0 l:i w:i 0x2F /r ; s:AVX, t:AVX, w:R|R|W, f:COMIS, e:3, x:IE|DE
|
||||
VCOMISD ; Vsd,Wsd ; Fv ; vex m:1 p:1 l:i w:i 0x2F /r ; s:AVX, t:AVX, w:R|R|W, f:COMIS, e:3, x:IE|DE
|
||||
|
||||
# 0x30 - 0x3F
|
||||
|
||||
@ -124,10 +124,10 @@ KTESTD ; rKd,mKd ; ; vex m:1 p:1 l:0 w:1
|
||||
# 0x50 - 0x5F
|
||||
VMOVMSKPS ; Gy,Ux ; ; vex m:1 p:0 l:x w:i 0x50 /r:reg ; s:AVX, t:DATAXFER, w:W|R, e:7, a:D64
|
||||
VMOVMSKPD ; Gy,Ux ; ; vex m:1 p:1 l:x w:i 0x50 /r:reg ; s:AVX, t:DATAXFER, w:W|R, e:7, a:D64
|
||||
VSQRTPS ; Vx,Wx ; ; vex m:1 p:0 l:x w:i 0x51 /r ; s:AVX, t:AVX, w:W|R, e:2
|
||||
VSQRTPD ; Vx,Wx ; ; vex m:1 p:1 l:x w:i 0x51 /r ; s:AVX, t:AVX, w:W|R, e:2
|
||||
VSQRTSS ; Vss,Hss,Wss ; ; vex m:1 p:2 l:i w:i 0x51 /r ; s:AVX, t:AVX, w:W|R|R, e:3
|
||||
VSQRTSD ; Vsd,Hsd,Wsd ; ; vex m:1 p:3 l:i w:i 0x51 /r ; s:AVX, t:AVX, w:W|R|R, e:3
|
||||
VSQRTPS ; Vx,Wx ; ; vex m:1 p:0 l:x w:i 0x51 /r ; s:AVX, t:AVX, w:W|R, e:2, x:IE|PE|DE
|
||||
VSQRTPD ; Vx,Wx ; ; vex m:1 p:1 l:x w:i 0x51 /r ; s:AVX, t:AVX, w:W|R, e:2, x:IE|PE|DE
|
||||
VSQRTSS ; Vss,Hss,Wss ; ; vex m:1 p:2 l:i w:i 0x51 /r ; s:AVX, t:AVX, w:W|R|R, e:3, x:IE|PE|DE
|
||||
VSQRTSD ; Vsd,Hsd,Wsd ; ; vex m:1 p:3 l:i w:i 0x51 /r ; s:AVX, t:AVX, w:W|R|R, e:3, x:IE|PE|DE
|
||||
VRSQRTPS ; Vx,Wx ; ; vex m:1 p:0 l:x w:i 0x52 /r ; s:AVX, t:AVX, w:W|R, e:4
|
||||
VRSQRTSS ; Vss,Hss,Wss ; ; vex m:1 p:2 l:i w:i 0x52 /r ; s:AVX, t:AVX, w:W|R|R, e:5
|
||||
VRCPPS ; Vps,Wps ; ; vex m:1 p:0 l:x w:i 0x53 /r ; s:AVX, t:AVX, w:W|R, e:4
|
||||
@ -140,39 +140,39 @@ VORPS ; Vps,Hps,Wps ; ; vex m:1 p:0 l:x w:i
|
||||
VORPD ; Vpd,Hpd,Wpd ; ; vex m:1 p:1 l:x w:i 0x56 /r ; s:AVX, t:LOGICAL_FP, w:W|R|R, e:4
|
||||
VXORPS ; Vps,Hps,Wps ; ; vex m:1 p:0 l:x w:i 0x57 /r ; s:AVX, t:LOGICAL_FP, w:W|R|R, e:4
|
||||
VXORPD ; Vpd,Hpd,Wpd ; ; vex m:1 p:1 l:x w:i 0x57 /r ; s:AVX, t:LOGICAL_FP, w:W|R|R, e:4
|
||||
VADDPS ; Vps,Hps,Wps ; ; vex m:1 p:0 l:x w:i 0x58 /r ; s:AVX, t:AVX, w:W|R|R, e:2
|
||||
VADDPD ; Vpd,Hpd,Wpd ; ; vex m:1 p:1 l:x w:i 0x58 /r ; s:AVX, t:AVX, w:W|R|R, e:2
|
||||
VADDSS ; Vss,Hss,Wss ; ; vex m:1 p:2 l:i w:i 0x58 /r ; s:AVX, t:AVX, w:W|R|R, e:2
|
||||
VADDSD ; Vsd,Hsd,Wsd ; ; vex m:1 p:3 l:i w:i 0x58 /r ; s:AVX, t:AVX, w:W|R|R, e:2
|
||||
VMULPS ; Vps,Hps,Wps ; ; vex m:1 p:0 l:x w:i 0x59 /r ; s:AVX, t:AVX, w:W|R|R, e:2
|
||||
VMULPD ; Vpd,Hpd,Wpd ; ; vex m:1 p:1 l:x w:i 0x59 /r ; s:AVX, t:AVX, w:W|R|R, e:2
|
||||
VMULSS ; Vss,Hss,Wss ; ; vex m:1 p:2 l:i w:i 0x59 /r ; s:AVX, t:AVX, w:W|R|R, e:2
|
||||
VMULSD ; Vsd,Hsd,Wsd ; ; vex m:1 p:3 l:i w:i 0x59 /r ; s:AVX, t:AVX, w:W|R|R, e:2
|
||||
VCVTPS2PD ; Vpd,Wq ; ; vex m:1 p:0 l:0 w:i 0x5A /r ; s:AVX, t:CONVERT, w:W|R, e:2
|
||||
VCVTPS2PD ; Vqq,Wdq ; ; vex m:1 p:0 l:1 w:i 0x5A /r ; s:AVX, t:CONVERT, w:W|R, e:2
|
||||
VCVTPD2PS ; Vdq,Wdq ; ; vex m:1 p:1 l:0 w:i 0x5A /r ; s:AVX, t:CONVERT, w:W|R, e:2
|
||||
VCVTPD2PS ; Vdq,Wqq ; ; vex m:1 p:1 l:1 w:i 0x5A /r ; s:AVX, t:CONVERT, w:W|R, e:2
|
||||
VCVTSS2SD ; Vsd,Hx,Wss ; ; vex m:1 p:2 l:i w:i 0x5A /r ; s:AVX, t:CONVERT, w:W|R|R, e:3
|
||||
VCVTSD2SS ; Vss,Hx,Wsd ; ; vex m:1 p:3 l:i w:i 0x5A /r ; s:AVX, t:CONVERT, w:W|R|R, e:3
|
||||
VCVTDQ2PS ; Vps,Wps ; ; vex m:1 p:0 l:x w:i 0x5B /r ; s:AVX, t:CONVERT, w:W|R, e:2
|
||||
VCVTPS2DQ ; Vps,Wps ; ; vex m:1 p:1 l:x w:i 0x5B /r ; s:AVX, t:CONVERT, w:W|R, e:2
|
||||
VCVTTPS2DQ ; Vps,Wps ; ; vex m:1 p:2 l:x w:i 0x5B /r ; s:AVX, t:CONVERT, w:W|R, e:2
|
||||
VSUBPS ; Vps,Hps,Wps ; ; vex m:1 p:0 l:x w:i 0x5C /r ; s:AVX, t:AVX, w:W|R|R, e:2
|
||||
VSUBPD ; Vpd,Hpd,Wpd ; ; vex m:1 p:1 l:x w:i 0x5C /r ; s:AVX, t:AVX, w:W|R|R, e:2
|
||||
VSUBSS ; Vss,Hss,Wss ; ; vex m:1 p:2 l:i w:i 0x5C /r ; s:AVX, t:AVX, w:W|R|R, e:2
|
||||
VSUBSD ; Vsd,Hsd,Wsd ; ; vex m:1 p:3 l:i w:i 0x5C /r ; s:AVX, t:AVX, w:W|R|R, e:2
|
||||
VMINPS ; Vps,Hps,Wps ; ; vex m:1 p:0 l:x w:i 0x5D /r ; s:AVX, t:AVX, w:W|R|R, e:2
|
||||
VMINPD ; Vpd,Hpd,Wpd ; ; vex m:1 p:1 l:x w:i 0x5D /r ; s:AVX, t:AVX, w:W|R|R, e:2
|
||||
VMINSS ; Vss,Hss,Wss ; ; vex m:1 p:2 l:i w:i 0x5D /r ; s:AVX, t:AVX, w:W|R|R, e:2
|
||||
VMINSD ; Vsd,Hsd,Wsd ; ; vex m:1 p:3 l:i w:i 0x5D /r ; s:AVX, t:AVX, w:W|R|R, e:2
|
||||
VDIVPS ; Vps,Hps,Wps ; ; vex m:1 p:0 l:x w:i 0x5E /r ; s:AVX, t:AVX, w:W|R|R, e:2
|
||||
VDIVPD ; Vpd,Hpd,Wpd ; ; vex m:1 p:1 l:x w:i 0x5E /r ; s:AVX, t:AVX, w:W|R|R, e:2
|
||||
VDIVSS ; Vss,Hss,Wss ; ; vex m:1 p:2 l:i w:i 0x5E /r ; s:AVX, t:AVX, w:W|R|R, e:2
|
||||
VDIVSD ; Vsd,Hsd,Wsd ; ; vex m:1 p:3 l:i w:i 0x5E /r ; s:AVX, t:AVX, w:W|R|R, e:2
|
||||
VMAXPS ; Vps,Hps,Wps ; ; vex m:1 p:0 l:x w:i 0x5F /r ; s:AVX, t:AVX, w:W|R|R, e:2
|
||||
VMAXPD ; Vpd,Hpd,Wpd ; ; vex m:1 p:1 l:x w:i 0x5F /r ; s:AVX, t:AVX, w:W|R|R, e:2
|
||||
VMAXSS ; Vss,Hss,Wss ; ; vex m:1 p:2 l:i w:i 0x5F /r ; s:AVX, t:AVX, w:W|R|R, e:2
|
||||
VMAXSD ; Vsd,Hsd,Wsd ; ; vex m:1 p:3 l:i w:i 0x5F /r ; s:AVX, t:AVX, w:W|R|R, e:2
|
||||
VADDPS ; Vps,Hps,Wps ; ; vex m:1 p:0 l:x w:i 0x58 /r ; s:AVX, t:AVX, w:W|R|R, e:2, x:IE|OE|UE|PE|DE
|
||||
VADDPD ; Vpd,Hpd,Wpd ; ; vex m:1 p:1 l:x w:i 0x58 /r ; s:AVX, t:AVX, w:W|R|R, e:2, x:IE|OE|UE|PE|DE
|
||||
VADDSS ; Vss,Hss,Wss ; ; vex m:1 p:2 l:i w:i 0x58 /r ; s:AVX, t:AVX, w:W|R|R, e:2, x:IE|OE|UE|PE|DE
|
||||
VADDSD ; Vsd,Hsd,Wsd ; ; vex m:1 p:3 l:i w:i 0x58 /r ; s:AVX, t:AVX, w:W|R|R, e:2, x:IE|OE|UE|PE|DE
|
||||
VMULPS ; Vps,Hps,Wps ; ; vex m:1 p:0 l:x w:i 0x59 /r ; s:AVX, t:AVX, w:W|R|R, e:2, x:IE|OE|UE|PE|DE
|
||||
VMULPD ; Vpd,Hpd,Wpd ; ; vex m:1 p:1 l:x w:i 0x59 /r ; s:AVX, t:AVX, w:W|R|R, e:2, x:IE|OE|UE|PE|DE
|
||||
VMULSS ; Vss,Hss,Wss ; ; vex m:1 p:2 l:i w:i 0x59 /r ; s:AVX, t:AVX, w:W|R|R, e:2, x:IE|OE|UE|PE|DE
|
||||
VMULSD ; Vsd,Hsd,Wsd ; ; vex m:1 p:3 l:i w:i 0x59 /r ; s:AVX, t:AVX, w:W|R|R, e:2, x:IE|OE|UE|PE|DE
|
||||
VCVTPS2PD ; Vpd,Wq ; ; vex m:1 p:0 l:0 w:i 0x5A /r ; s:AVX, t:CONVERT, w:W|R, e:2, x:IE|DE
|
||||
VCVTPS2PD ; Vqq,Wdq ; ; vex m:1 p:0 l:1 w:i 0x5A /r ; s:AVX, t:CONVERT, w:W|R, e:2, x:IE|DE
|
||||
VCVTPD2PS ; Vdq,Wdq ; ; vex m:1 p:1 l:0 w:i 0x5A /r ; s:AVX, t:CONVERT, w:W|R, e:2, x:IE|OE|UE|PE|DE
|
||||
VCVTPD2PS ; Vdq,Wqq ; ; vex m:1 p:1 l:1 w:i 0x5A /r ; s:AVX, t:CONVERT, w:W|R, e:2, x:IE|OE|UE|PE|DE
|
||||
VCVTSS2SD ; Vsd,Hx,Wss ; ; vex m:1 p:2 l:i w:i 0x5A /r ; s:AVX, t:CONVERT, w:W|R|R, e:3, x:IE|DE
|
||||
VCVTSD2SS ; Vss,Hx,Wsd ; ; vex m:1 p:3 l:i w:i 0x5A /r ; s:AVX, t:CONVERT, w:W|R|R, e:3, x:IE|OE|UE|PE|DE
|
||||
VCVTDQ2PS ; Vps,Wps ; ; vex m:1 p:0 l:x w:i 0x5B /r ; s:AVX, t:CONVERT, w:W|R, e:2, x:PE
|
||||
VCVTPS2DQ ; Vps,Wps ; ; vex m:1 p:1 l:x w:i 0x5B /r ; s:AVX, t:CONVERT, w:W|R, e:2, x:IE|PE
|
||||
VCVTTPS2DQ ; Vps,Wps ; ; vex m:1 p:2 l:x w:i 0x5B /r ; s:AVX, t:CONVERT, w:W|R, e:2, x:IE|PE
|
||||
VSUBPS ; Vps,Hps,Wps ; ; vex m:1 p:0 l:x w:i 0x5C /r ; s:AVX, t:AVX, w:W|R|R, e:2, x:IE|OE|UE|PE|DE
|
||||
VSUBPD ; Vpd,Hpd,Wpd ; ; vex m:1 p:1 l:x w:i 0x5C /r ; s:AVX, t:AVX, w:W|R|R, e:2, x:IE|OE|UE|PE|DE
|
||||
VSUBSS ; Vss,Hss,Wss ; ; vex m:1 p:2 l:i w:i 0x5C /r ; s:AVX, t:AVX, w:W|R|R, e:2, x:IE|OE|UE|PE|DE
|
||||
VSUBSD ; Vsd,Hsd,Wsd ; ; vex m:1 p:3 l:i w:i 0x5C /r ; s:AVX, t:AVX, w:W|R|R, e:2, x:IE|OE|UE|PE|DE
|
||||
VMINPS ; Vps,Hps,Wps ; ; vex m:1 p:0 l:x w:i 0x5D /r ; s:AVX, t:AVX, w:W|R|R, e:2, x:IE|DE
|
||||
VMINPD ; Vpd,Hpd,Wpd ; ; vex m:1 p:1 l:x w:i 0x5D /r ; s:AVX, t:AVX, w:W|R|R, e:2, x:IE|DE
|
||||
VMINSS ; Vss,Hss,Wss ; ; vex m:1 p:2 l:i w:i 0x5D /r ; s:AVX, t:AVX, w:W|R|R, e:2, x:IE|DE
|
||||
VMINSD ; Vsd,Hsd,Wsd ; ; vex m:1 p:3 l:i w:i 0x5D /r ; s:AVX, t:AVX, w:W|R|R, e:2, x:IE|DE
|
||||
VDIVPS ; Vps,Hps,Wps ; ; vex m:1 p:0 l:x w:i 0x5E /r ; s:AVX, t:AVX, w:W|R|R, e:2, x:IE|OE|UE|PE|DE|ZE
|
||||
VDIVPD ; Vpd,Hpd,Wpd ; ; vex m:1 p:1 l:x w:i 0x5E /r ; s:AVX, t:AVX, w:W|R|R, e:2, x:IE|OE|UE|PE|DE|ZE
|
||||
VDIVSS ; Vss,Hss,Wss ; ; vex m:1 p:2 l:i w:i 0x5E /r ; s:AVX, t:AVX, w:W|R|R, e:2, x:IE|OE|UE|PE|DE|ZE
|
||||
VDIVSD ; Vsd,Hsd,Wsd ; ; vex m:1 p:3 l:i w:i 0x5E /r ; s:AVX, t:AVX, w:W|R|R, e:2, x:IE|OE|UE|PE|DE|ZE
|
||||
VMAXPS ; Vps,Hps,Wps ; ; vex m:1 p:0 l:x w:i 0x5F /r ; s:AVX, t:AVX, w:W|R|R, e:2, x:IE|DE
|
||||
VMAXPD ; Vpd,Hpd,Wpd ; ; vex m:1 p:1 l:x w:i 0x5F /r ; s:AVX, t:AVX, w:W|R|R, e:2, x:IE|DE
|
||||
VMAXSS ; Vss,Hss,Wss ; ; vex m:1 p:2 l:i w:i 0x5F /r ; s:AVX, t:AVX, w:W|R|R, e:2, x:IE|DE
|
||||
VMAXSD ; Vsd,Hsd,Wsd ; ; vex m:1 p:3 l:i w:i 0x5F /r ; s:AVX, t:AVX, w:W|R|R, e:2, x:IE|DE
|
||||
|
||||
|
||||
# 0x60 - 0x6F
|
||||
@ -206,10 +206,10 @@ VPCMPEQW ; Vx,Hx,Wx ; ; vex m:1 p:1 l:x w:i
|
||||
VPCMPEQD ; Vx,Hx,Wx ; ; vex m:1 p:1 l:x w:i 0x76 /r ; s:AVX, t:AVX, w:W|R|R, e:4
|
||||
VZEROUPPER ; ; BANK ; vex m:1 p:0 l:0 0x77 ; s:AVX, t:AVX, w:W, e:8
|
||||
VZEROALL ; ; BANK ; vex m:1 p:0 l:1 0x77 ; s:AVX, t:AVX, w:W, e:8
|
||||
VHADDPD ; Vpd,Hpd,Wpd ; ; vex m:1 p:1 l:x w:i 0x7C /r ; s:AVX, t:AVX, w:W|R|R, e:2
|
||||
VHADDPS ; Vps,Hps,Wps ; ; vex m:1 p:3 l:x w:i 0x7C /r ; s:AVX, t:AVX, w:W|R|R, e:2
|
||||
VHSUBPD ; Vpd,Hpd,Wpd ; ; vex m:1 p:1 l:x w:i 0x7D /r ; s:AVX, t:AVX, w:W|R|R, e:2
|
||||
VHSUBPS ; Vps,Hps,Wps ; ; vex m:1 p:3 l:x w:i 0x7D /r ; s:AVX, t:AVX, w:W|R|R, e:2
|
||||
VHADDPD ; Vpd,Hpd,Wpd ; ; vex m:1 p:1 l:x w:i 0x7C /r ; s:AVX, t:AVX, w:W|R|R, e:2, x:IE|OE|UE|PE|DE
|
||||
VHADDPS ; Vps,Hps,Wps ; ; vex m:1 p:3 l:x w:i 0x7C /r ; s:AVX, t:AVX, w:W|R|R, e:2, x:IE|OE|UE|PE|DE
|
||||
VHSUBPD ; Vpd,Hpd,Wpd ; ; vex m:1 p:1 l:x w:i 0x7D /r ; s:AVX, t:AVX, w:W|R|R, e:2, x:IE|OE|UE|PE|DE
|
||||
VHSUBPS ; Vps,Hps,Wps ; ; vex m:1 p:3 l:x w:i 0x7D /r ; s:AVX, t:AVX, w:W|R|R, e:2, x:IE|OE|UE|PE|DE
|
||||
VMOVD ; Ey,Vd ; ; vex m:1 p:1 l:0 w:0 0x7E /r ; s:AVX, t:DATAXFER, w:W|R, e:5, a:IWO64
|
||||
VMOVQ ; Ey,Vq ; ; vex m:1 p:1 l:0 w:1 0x7E /r ; s:AVX, t:DATAXFER, w:W|R, e:5, a:IWO64
|
||||
VMOVQ ; Vdq,Wq ; ; vex m:1 p:2 l:0 w:i 0x7E /r ; s:AVX, t:DATAXFER, w:W|R, e:5
|
||||
@ -241,10 +241,10 @@ CLEVICT1 ; M? ; ; vex m:1 p:2 0xAE /7
|
||||
# 0xB0 - 0xBF
|
||||
|
||||
# 0xC0 - 0xCF
|
||||
VCMPPS ; Vss,Hss,Wss,Ib ; ; vex m:1 p:0 l:i w:i 0xC2 /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:3
|
||||
VCMPPD ; Vpd,Hpd,Wpd,Ib ; ; vex m:1 p:1 l:x w:i 0xC2 /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:3
|
||||
VCMPSS ; Vss,Hss,Wss,Ib ; ; vex m:1 p:2 l:i w:i 0xC2 /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:3
|
||||
VCMPSD ; Vsd,Hsd,Wsd,Ib ; ; vex m:1 p:3 l:i w:i 0xC2 /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:3
|
||||
VCMPPS ; Vss,Hss,Wss,Ib ; ; vex m:1 p:0 l:i w:i 0xC2 /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:3, x:IE|DE
|
||||
VCMPPD ; Vpd,Hpd,Wpd,Ib ; ; vex m:1 p:1 l:x w:i 0xC2 /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:3, x:IE|DE
|
||||
VCMPSS ; Vss,Hss,Wss,Ib ; ; vex m:1 p:2 l:i w:i 0xC2 /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:3, x:IE|DE
|
||||
VCMPSD ; Vsd,Hsd,Wsd,Ib ; ; vex m:1 p:3 l:i w:i 0xC2 /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:3, x:IE|DE
|
||||
VPINSRW ; Vdq,Hdq,Mw,Ib ; ; vex m:1 p:1 l:0 w:i 0xC4 /r:mem ib ; s:AVX, t:AVX, w:W|R|R|R, e:5
|
||||
VPINSRW ; Vdq,Hdq,Rd,Ib ; ; vex m:1 p:1 l:0 w:i 0xC4 /r:reg ib ; s:AVX, t:AVX, w:W|R|R|R, e:5
|
||||
VPEXTRW ; Gy,Udq,Ib ; ; vex m:1 p:1 l:0 w:i 0xC5 /r:reg ib ; s:AVX, t:AVX, w:W|R|R, e:5, a:D64
|
||||
@ -252,8 +252,8 @@ VSHUFPS ; Vps,Hps,Wps,Ib ; ; vex m:1 p:0 l:x w:i
|
||||
VSHUFPD ; Vpd,Hpd,Wpd,Ib ; ; vex m:1 p:1 l:x w:i 0xC6 /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:4
|
||||
|
||||
# 0xD0 - 0xDF
|
||||
VADDSUBPD ; Vpd,Hpd,Wpd ; ; vex m:1 p:1 l:x w:i 0xD0 /r ; s:AVX, t:AVX, w:W|R|R, e:2
|
||||
VADDSUBPS ; Vps,Hps,Wps ; ; vex m:1 p:3 l:x w:i 0xD0 /r ; s:AVX, t:AVX, w:W|R|R, e:2
|
||||
VADDSUBPD ; Vpd,Hpd,Wpd ; ; vex m:1 p:1 l:x w:i 0xD0 /r ; s:AVX, t:AVX, w:W|R|R, e:2, x:IE|OE|UE|PE|DE
|
||||
VADDSUBPS ; Vps,Hps,Wps ; ; vex m:1 p:3 l:x w:i 0xD0 /r ; s:AVX, t:AVX, w:W|R|R, e:2, x:IE|OE|UE|PE|DE
|
||||
VPSRLW ; Vx,Hx,Wdq ; ; vex m:1 p:1 l:x w:i 0xD1 /r ; s:AVX, t:AVX, w:W|R|R, e:4
|
||||
VPSRLD ; Vx,Hx,Wdq ; ; vex m:1 p:1 l:x w:i 0xD2 /r ; s:AVX, t:AVX, w:W|R|R, e:4
|
||||
VPSRLQ ; Vx,Hx,Wdq ; ; vex m:1 p:1 l:x w:i 0xD3 /r ; s:AVX, t:AVX, w:W|R|R, e:4
|
||||
@ -277,10 +277,10 @@ VPSRAD ; Vx,Hx,Wdq ; ; vex m:1 p:1 l:x w:i
|
||||
VPAVGW ; Vx,Hx,Wx ; ; vex m:1 p:1 l:x w:i 0xE3 /r ; s:AVX, t:AVX, w:W|R|R, e:4
|
||||
VPMULHUW ; Vx,Hx,Wx ; ; vex m:1 p:1 l:x w:i 0xE4 /r ; s:AVX, t:AVX, w:W|R|R, e:4
|
||||
VPMULHW ; Vx,Hx,Wx ; ; vex m:1 p:1 l:x w:i 0xE5 /r ; s:AVX, t:AVX, w:W|R|R, e:4
|
||||
VCVTTPD2DQ ; Vdq,Wx ; ; vex m:1 p:1 l:x w:i 0xE6 /r ; s:AVX, t:CONVERT, w:W|R, e:2
|
||||
VCVTTPD2DQ ; Vdq,Wx ; ; vex m:1 p:1 l:x w:i 0xE6 /r ; s:AVX, t:CONVERT, w:W|R, e:2, x:IE|PE
|
||||
VCVTDQ2PD ; Vdq,Wq ; ; vex m:1 p:2 l:0 w:i 0xE6 /r ; s:AVX, t:CONVERT, w:W|R, e:5
|
||||
VCVTDQ2PD ; Vqq,Wdq ; ; vex m:1 p:2 l:1 w:i 0xE6 /r ; s:AVX, t:CONVERT, w:W|R, e:5
|
||||
VCVTPD2DQ ; Vdq,Wx ; ; vex m:1 p:3 l:x w:i 0xE6 /r ; s:AVX, t:CONVERT, w:W|R, e:2
|
||||
VCVTPD2DQ ; Vdq,Wx ; ; vex m:1 p:3 l:x w:i 0xE6 /r ; s:AVX, t:CONVERT, w:W|R, e:2, x:IE|PE
|
||||
VMOVNTDQ ; Mx,Vx ; ; vex m:1 p:1 l:x w:i 0xE7 /r:mem ; s:AVX, t:AVX, w:W|R, e:1
|
||||
VPSUBSB ; Vx,Hx,Wx ; ; vex m:1 p:1 l:x w:i 0xE8 /r ; s:AVX, t:AVX, w:W|R|R, e:4
|
||||
VPSUBSW ; Vx,Hx,Wx ; ; vex m:1 p:1 l:x w:i 0xE9 /r ; s:AVX, t:AVX, w:W|R|R, e:4
|
||||
|
||||
@ -22,8 +22,8 @@ VTESTPS ; Vx,Wx ; Fv ; vex m:2 p:1 l:x w:0
|
||||
VTESTPD ; Vx,Wx ; Fv ; vex m:2 p:1 l:x w:0 0x0F /r ; s:AVX, t:LOGICAL_FP, w:R|R|W, f:VPTEST, e:4
|
||||
|
||||
# 0x10 - 0x1F
|
||||
VCVTPH2PS ; Vdq,Wq ; ; vex m:2 p:1 l:0 w:0 0x13 /r ; s:F16C, t:CONVERT, w:W|R, e:11
|
||||
VCVTPH2PS ; Vqq,Wdq ; ; vex m:2 p:1 l:1 w:0 0x13 /r ; s:F16C, t:CONVERT, w:W|R, e:11
|
||||
VCVTPH2PS ; Vdq,Wq ; ; vex m:2 p:1 l:0 w:0 0x13 /r ; s:F16C, t:CONVERT, w:W|R, e:11, x:IE
|
||||
VCVTPH2PS ; Vqq,Wdq ; ; vex m:2 p:1 l:1 w:0 0x13 /r ; s:F16C, t:CONVERT, w:W|R, e:11, x:IE
|
||||
VPERMPS ; Vqq,Hqq,Wqq ; ; vex m:2 p:1 l:1 w:0 0x16 /r ; s:AVX2, t:AVX2, w:W|R|R, e:4
|
||||
VPTEST ; Vx,Wx ; Fv ; vex m:2 p:1 l:x w:i 0x17 /r ; s:AVX, t:LOGICAL, w:R|R|W, f:VPTEST, e:4
|
||||
VBROADCASTSS ; Vx,Wss ; ; vex m:2 p:1 l:x w:0 0x18 /r ; s:AVX, t:BROADCAST, w:W|R, e:6
|
||||
@ -88,6 +88,8 @@ VPSRAVD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0
|
||||
VPSLLVD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0x47 /r ; s:AVX2, t:AVX2, w:W|R|R, e:4
|
||||
VPSLLVQ ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0x47 /r ; s:AVX2, t:AVX2, w:W|R|R, e:4
|
||||
|
||||
TTMMULTF32PS ; rTt,mTt,vTt ; ; vex m:2 p:0 l:0 w:0 0x48 /r:reg ; s:AMXTRANSPOSE, t:AMX, w:RW|R|R, m:NOTSX|O64, e:AMX_E10
|
||||
TMMULTF32PS ; rTt,mTt,vTt ; ; vex m:2 p:1 l:0 w:0 0x48 /r:reg ; s:AMXTF32, t:AMX, w:RW|R|R, m:NOTSX|O64, e:AMX_E4
|
||||
LDTILECFG ; Moq ; ; vex m:2 p:0 l:0 w:0 0x49 /0:mem ; s:AMXTILE, t:AMX, w:R, m:NOTSX|O64, e:AMX_E1
|
||||
STTILECFG ; Moq ; ; vex m:2 p:1 l:0 w:0 0x49 /0:mem ; s:AMXTILE, t:AMX, w:W, m:NOTSX|O64, e:AMX_E2
|
||||
TILELOADD ; rTt,Mt ; ; vex m:2 p:3 l:0 w:0 0x4B /r:mem sibmem ;s:AMXTILE, t:AMX, w:W|R, m:NOTSX|O64, e:AMX_E3
|
||||
@ -95,6 +97,8 @@ TILESTORED ; Mt,rTt ; ; vex m:2 p:2 l:0 w:0
|
||||
TILELOADDT1 ; rTt,Mt ; ; vex m:2 p:1 l:0 w:0 0x4B /r:mem sibmem ;s:AMXTILE, t:AMX, w:W|R, m:NOTSX|O64, e:AMX_E3
|
||||
TILERELEASE ; ; ; vex m:2 p:0 l:0 w:0 0x49 /0xC0 ; s:AMXTILE, t:AMX, m:NOTSX|O64, e:AMX_E6
|
||||
TILEZERO ; rTt ; ; vex m:2 p:3 l:0 w:0 0x49 /r:reg rm:0 ; s:AMXTILE, t:AMX, w:W, m:NOTSX|O64, e:AMX_E5
|
||||
TILELOADDRST1 ; rTt,Mt ; ; vex m:2 p:1 l:0 w:0 0x4A /r:mem sibmem ; s:AMXMOVRS, t:AMX, w:W|R, m:NOTSX|O64, e:AMX_E3
|
||||
TILELOADDRS ; rTt,Mt ; ; vex m:2 p:3 l:0 w:0 0x4A /r:mem sibmem ; s:AMXMOVRS, t:AMX, w:W|R, m:NOTSX|O64, e:AMX_E3
|
||||
|
||||
# 0x50 - 0x5F
|
||||
VPDPBUUD ; Vx,Hx,Wx ; ; vex m:2 p:0 l:x w:0 0x50 /r ; s:AVXVNNIINT8, t:AVXVNNIINT8, w:RW|R|R, e:4
|
||||
@ -118,10 +122,22 @@ TDPBUUD ; rTt,mTt,vTt ; ; vex m:2 p:0 l:0 w:0
|
||||
TDPBUSD ; rTt,mTt,vTt ; ; vex m:2 p:1 l:0 w:0 0x5E /r:reg ; s:AMXINT8, t:AMX, w:RW|R|R, m:NOTSX|O64, e:AMX_E4
|
||||
TDPBSUD ; rTt,mTt,vTt ; ; vex m:2 p:2 l:0 w:0 0x5E /r:reg ; s:AMXINT8, t:AMX, w:RW|R|R, m:NOTSX|O64, e:AMX_E4
|
||||
TDPBSSD ; rTt,mTt,vTt ; ; vex m:2 p:3 l:0 w:0 0x5E /r:reg ; s:AMXINT8, t:AMX, w:RW|R|R, m:NOTSX|O64, e:AMX_E4
|
||||
TTRANSPOSED ; rTt,mTt ; ; vex m:2 p:2 l:0 w:0 0x5F /r:reg ; s:AMXTRANSPOSE, t:AMX, w:W|R, m:NOTSX|O64, e:AMX_E9
|
||||
|
||||
# 0x60 - 0x6F
|
||||
TCONJTCMMIMFP16PS ; rTt,mTt,vTt ; ; vex m:2 p:0 l:0 w:0 0x6B /r:reg ; s:AMXTRANSPOSE, t:AMX, w:RW|R|R, m:NOTSX|O64, e:AMX_E10
|
||||
TCONJTFP16 ; rTt,mTt ; ; vex m:2 p:1 l:0 w:0 0x6B /r:reg ; s:AMXTRANSPOSE, t:AMX, w:W|R, m:NOTSX|O64, e:AMX_E9
|
||||
TTCMMRLFP16PS ; rTt,mTt,vTt ; ; vex m:2 p:2 l:0 w:0 0x6B /r:reg ; s:AMXTRANSPOSE, t:AMX, w:RW|R|R, m:NOTSX|O64, e:AMX_E10
|
||||
TTCMMIMFP16PS ; rTt,mTt,vTt ; ; vex m:2 p:3 l:0 w:0 0x6B /r:reg ; s:AMXTRANSPOSE, t:AMX, w:RW|R|R, m:NOTSX|O64, e:AMX_E10
|
||||
TCMMRLFP16PS ; rTt,mTt,vTt ; ; vex m:2 p:0 l:0 w:0 0x6C /r:reg ; s:AMXCOMPLEX, t:AMX, w:RW|R|R, m:NOTSX|O64, e:AMX_E4
|
||||
TCMMIMFP16PS ; rTt,mTt,vTt ; ; vex m:2 p:1 l:0 w:0 0x6C /r:reg ; s:AMXCOMPLEX, t:AMX, w:RW|R|R, m:NOTSX|O64, e:AMX_E4
|
||||
TTDPBF16PS ; rTt,mTt,vTt ; ; vex m:2 p:2 l:0 w:0 0x6C /r:reg ; s:AMXTRANSPOSE, t:AMX, w:RW|R|R, m:NOTSX|O64, e:AMX_E10
|
||||
TTDPFP16PS ; rTt,mTt,vTt ; ; vex m:2 p:3 l:0 w:0 0x6C /r:reg ; s:AMXTRANSPOSE, t:AMX, w:RW|R|R, m:NOTSX|O64, e:AMX_E10
|
||||
T2RPNTLVWZ0 ; rTt+1,Mt ; ; vex m:2 p:0 l:0 w:0 0x6E /r:mem sibmem ; s:AMXTRANSPOSE, t:AMX, w:W|R, m:NOTSX|O64, e:AMX_E11
|
||||
T2RPNTLVWZ1 ; rTt+1,Mt ; ; vex m:2 p:1 l:0 w:0 0x6E /r:mem sibmem ; s:AMXTRANSPOSE, t:AMX, w:W|R, m:NOTSX|O64, e:AMX_E11
|
||||
T2RPNTLVWZ0T1 ; rTt+1,Mt ; ; vex m:2 p:0 l:0 w:0 0x6F /r:mem sibmem ; s:AMXTRANSPOSE, t:AMX, w:W|R, m:NOTSX|O64, e:AMX_E11
|
||||
T2RPNTLVWZ1T1 ; rTt+1,Mt ; ; vex m:2 p:1 l:0 w:0 0x6F /r:mem sibmem ; s:AMXTRANSPOSE, t:AMX, w:W|R, m:NOTSX|O64, e:AMX_E11
|
||||
|
||||
|
||||
# 0x70 - 0x7F
|
||||
VCVTNEPS2BF16 ; Vx,Wx ; ; vex m:2 p:2 l:x w:0 0x72 /r ; s:AVXNECONVERT, t:AVXNECONVERT, w:W|R, e:4
|
||||
@ -144,48 +160,48 @@ VGATHERDPD ; Vx,Mvm32h,Hx ; ; vex m:2 p:1 l:x w:1
|
||||
VGATHERQPS ; Vdq,Mvm64n,Hdq ; ; vex m:2 p:1 l:x w:0 0x93 /r:mem vsib ; s:AVX2GATHER, t:AVX2GATHER, w:CRW|R|RW, e:12
|
||||
VGATHERQPD ; Vx,Mvm64n,Hx ; ; vex m:2 p:1 l:x w:1 0x93 /r:mem vsib ; s:AVX2GATHER, t:AVX2GATHER, w:CRW|R|RW, e:12
|
||||
|
||||
VFMADDSUB132PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0x96 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2
|
||||
VFMADDSUB132PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0x96 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2
|
||||
VFMSUBADD132PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0x97 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2
|
||||
VFMSUBADD132PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0x97 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2
|
||||
VFMADD132PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0x98 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2
|
||||
VFMADD132PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0x98 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2
|
||||
VFMADD132SS ; Vdq,Hdq,Wss ; ; vex m:2 p:1 l:i w:0 0x99 /r ; s:FMA, t:VFMA, w:RW|R|R, e:3
|
||||
VFMADD132SD ; Vdq,Hdq,Wsd ; ; vex m:2 p:1 l:i w:1 0x99 /r ; s:FMA, t:VFMA, w:RW|R|R, e:3
|
||||
VFMSUB132PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0x9A /r ; s:FMA, t:VFMA, w:RW|R|R, e:2
|
||||
VFMSUB132PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0x9A /r ; s:FMA, t:VFMA, w:RW|R|R, e:2
|
||||
VFMSUB132SS ; Vdq,Hdq,Wss ; ; vex m:2 p:1 l:i w:0 0x9B /r ; s:FMA, t:VFMA, w:RW|R|R, e:3
|
||||
VFMSUB132SD ; Vdq,Hdq,Wsd ; ; vex m:2 p:1 l:i w:1 0x9B /r ; s:FMA, t:VFMA, w:RW|R|R, e:3
|
||||
VFNMADD132PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0x9C /r ; s:FMA, t:VFMA, w:RW|R|R, e:2
|
||||
VFNMADD132PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0x9C /r ; s:FMA, t:VFMA, w:RW|R|R, e:2
|
||||
VFNMADD132SS ; Vdq,Hdq,Wss ; ; vex m:2 p:1 l:i w:0 0x9D /r ; s:FMA, t:VFMA, w:RW|R|R, e:3
|
||||
VFNMADD132SD ; Vdq,Hdq,Wsd ; ; vex m:2 p:1 l:i w:1 0x9D /r ; s:FMA, t:VFMA, w:RW|R|R, e:3
|
||||
VFNMSUB132PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0x9E /r ; s:FMA, t:VFMA, w:RW|R|R, e:2
|
||||
VFNMSUB132PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0x9E /r ; s:FMA, t:VFMA, w:RW|R|R, e:2
|
||||
VFNMSUB132SS ; Vdq,Hdq,Wss ; ; vex m:2 p:1 l:i w:0 0x9F /r ; s:FMA, t:VFMA, w:RW|R|R, e:3
|
||||
VFNMSUB132SD ; Vdq,Hdq,Wsd ; ; vex m:2 p:1 l:i w:1 0x9F /r ; s:FMA, t:VFMA, w:RW|R|R, e:3
|
||||
VFMADDSUB132PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0x96 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2, x:IE|OE|UE|PE|DE
|
||||
VFMADDSUB132PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0x96 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2, x:IE|OE|UE|PE|DE
|
||||
VFMSUBADD132PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0x97 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2, x:IE|OE|UE|PE|DE
|
||||
VFMSUBADD132PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0x97 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2, x:IE|OE|UE|PE|DE
|
||||
VFMADD132PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0x98 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2, x:IE|OE|UE|PE|DE
|
||||
VFMADD132PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0x98 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2, x:IE|OE|UE|PE|DE
|
||||
VFMADD132SS ; Vdq,Hdq,Wss ; ; vex m:2 p:1 l:i w:0 0x99 /r ; s:FMA, t:VFMA, w:RW|R|R, e:3, x:IE|OE|UE|PE|DE
|
||||
VFMADD132SD ; Vdq,Hdq,Wsd ; ; vex m:2 p:1 l:i w:1 0x99 /r ; s:FMA, t:VFMA, w:RW|R|R, e:3, x:IE|OE|UE|PE|DE
|
||||
VFMSUB132PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0x9A /r ; s:FMA, t:VFMA, w:RW|R|R, e:2, x:IE|OE|UE|PE|DE
|
||||
VFMSUB132PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0x9A /r ; s:FMA, t:VFMA, w:RW|R|R, e:2, x:IE|OE|UE|PE|DE
|
||||
VFMSUB132SS ; Vdq,Hdq,Wss ; ; vex m:2 p:1 l:i w:0 0x9B /r ; s:FMA, t:VFMA, w:RW|R|R, e:3, x:IE|OE|UE|PE|DE
|
||||
VFMSUB132SD ; Vdq,Hdq,Wsd ; ; vex m:2 p:1 l:i w:1 0x9B /r ; s:FMA, t:VFMA, w:RW|R|R, e:3, x:IE|OE|UE|PE|DE
|
||||
VFNMADD132PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0x9C /r ; s:FMA, t:VFMA, w:RW|R|R, e:2, x:IE|OE|UE|PE|DE
|
||||
VFNMADD132PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0x9C /r ; s:FMA, t:VFMA, w:RW|R|R, e:2, x:IE|OE|UE|PE|DE
|
||||
VFNMADD132SS ; Vdq,Hdq,Wss ; ; vex m:2 p:1 l:i w:0 0x9D /r ; s:FMA, t:VFMA, w:RW|R|R, e:3, x:IE|OE|UE|PE|DE
|
||||
VFNMADD132SD ; Vdq,Hdq,Wsd ; ; vex m:2 p:1 l:i w:1 0x9D /r ; s:FMA, t:VFMA, w:RW|R|R, e:3, x:IE|OE|UE|PE|DE
|
||||
VFNMSUB132PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0x9E /r ; s:FMA, t:VFMA, w:RW|R|R, e:2, x:IE|OE|UE|PE|DE
|
||||
VFNMSUB132PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0x9E /r ; s:FMA, t:VFMA, w:RW|R|R, e:2, x:IE|OE|UE|PE|DE
|
||||
VFNMSUB132SS ; Vdq,Hdq,Wss ; ; vex m:2 p:1 l:i w:0 0x9F /r ; s:FMA, t:VFMA, w:RW|R|R, e:3, x:IE|OE|UE|PE|DE
|
||||
VFNMSUB132SD ; Vdq,Hdq,Wsd ; ; vex m:2 p:1 l:i w:1 0x9F /r ; s:FMA, t:VFMA, w:RW|R|R, e:3, x:IE|OE|UE|PE|DE
|
||||
|
||||
# 0xA0 - 0xAF
|
||||
VFMADDSUB213PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0xA6 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2
|
||||
VFMADDSUB213PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0xA6 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2
|
||||
VFMSUBADD213PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0xA7 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2
|
||||
VFMSUBADD213PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0xA7 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2
|
||||
VFMADD213PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0xA8 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2
|
||||
VFMADD213PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0xA8 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2
|
||||
VFMADD213SS ; Vdq,Hdq,Wss ; ; vex m:2 p:1 l:i w:0 0xA9 /r ; s:FMA, t:VFMA, w:RW|R|R, e:3
|
||||
VFMADD213SD ; Vdq,Hdq,Wsd ; ; vex m:2 p:1 l:i w:1 0xA9 /r ; s:FMA, t:VFMA, w:RW|R|R, e:3
|
||||
VFMSUB213PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0xAA /r ; s:FMA, t:VFMA, w:RW|R|R, e:2
|
||||
VFMSUB213PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0xAA /r ; s:FMA, t:VFMA, w:RW|R|R, e:2
|
||||
VFMSUB213SS ; Vdq,Hdq,Wss ; ; vex m:2 p:1 l:i w:0 0xAB /r ; s:FMA, t:VFMA, w:RW|R|R, e:3
|
||||
VFMSUB213SD ; Vdq,Hdq,Wsd ; ; vex m:2 p:1 l:i w:1 0xAB /r ; s:FMA, t:VFMA, w:RW|R|R, e:3
|
||||
VFNMADD213PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0xAC /r ; s:FMA, t:VFMA, w:RW|R|R, e:2
|
||||
VFNMADD213PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0xAC /r ; s:FMA, t:VFMA, w:RW|R|R, e:2
|
||||
VFNMADD213SS ; Vdq,Hdq,Wss ; ; vex m:2 p:1 l:i w:0 0xAD /r ; s:FMA, t:VFMA, w:RW|R|R, e:3
|
||||
VFNMADD213SD ; Vdq,Hdq,Wsd ; ; vex m:2 p:1 l:i w:1 0xAD /r ; s:FMA, t:VFMA, w:RW|R|R, e:3
|
||||
VFNMSUB213PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0xAE /r ; s:FMA, t:VFMA, w:RW|R|R, e:2
|
||||
VFNMSUB213PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0xAE /r ; s:FMA, t:VFMA, w:RW|R|R, e:2
|
||||
VFNMSUB213SS ; Vdq,Hdq,Wss ; ; vex m:2 p:1 l:i w:0 0xAF /r ; s:FMA, t:VFMA, w:RW|R|R, e:3
|
||||
VFNMSUB213SD ; Vdq,Hdq,Wsd ; ; vex m:2 p:1 l:i w:1 0xAF /r ; s:FMA, t:VFMA, w:RW|R|R, e:3
|
||||
VFMADDSUB213PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0xA6 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2, x:IE|OE|UE|PE|DE
|
||||
VFMADDSUB213PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0xA6 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2, x:IE|OE|UE|PE|DE
|
||||
VFMSUBADD213PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0xA7 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2, x:IE|OE|UE|PE|DE
|
||||
VFMSUBADD213PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0xA7 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2, x:IE|OE|UE|PE|DE
|
||||
VFMADD213PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0xA8 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2, x:IE|OE|UE|PE|DE
|
||||
VFMADD213PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0xA8 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2, x:IE|OE|UE|PE|DE
|
||||
VFMADD213SS ; Vdq,Hdq,Wss ; ; vex m:2 p:1 l:i w:0 0xA9 /r ; s:FMA, t:VFMA, w:RW|R|R, e:3, x:IE|OE|UE|PE|DE
|
||||
VFMADD213SD ; Vdq,Hdq,Wsd ; ; vex m:2 p:1 l:i w:1 0xA9 /r ; s:FMA, t:VFMA, w:RW|R|R, e:3, x:IE|OE|UE|PE|DE
|
||||
VFMSUB213PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0xAA /r ; s:FMA, t:VFMA, w:RW|R|R, e:2, x:IE|OE|UE|PE|DE
|
||||
VFMSUB213PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0xAA /r ; s:FMA, t:VFMA, w:RW|R|R, e:2, x:IE|OE|UE|PE|DE
|
||||
VFMSUB213SS ; Vdq,Hdq,Wss ; ; vex m:2 p:1 l:i w:0 0xAB /r ; s:FMA, t:VFMA, w:RW|R|R, e:3, x:IE|OE|UE|PE|DE
|
||||
VFMSUB213SD ; Vdq,Hdq,Wsd ; ; vex m:2 p:1 l:i w:1 0xAB /r ; s:FMA, t:VFMA, w:RW|R|R, e:3, x:IE|OE|UE|PE|DE
|
||||
VFNMADD213PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0xAC /r ; s:FMA, t:VFMA, w:RW|R|R, e:2, x:IE|OE|UE|PE|DE
|
||||
VFNMADD213PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0xAC /r ; s:FMA, t:VFMA, w:RW|R|R, e:2, x:IE|OE|UE|PE|DE
|
||||
VFNMADD213SS ; Vdq,Hdq,Wss ; ; vex m:2 p:1 l:i w:0 0xAD /r ; s:FMA, t:VFMA, w:RW|R|R, e:3, x:IE|OE|UE|PE|DE
|
||||
VFNMADD213SD ; Vdq,Hdq,Wsd ; ; vex m:2 p:1 l:i w:1 0xAD /r ; s:FMA, t:VFMA, w:RW|R|R, e:3, x:IE|OE|UE|PE|DE
|
||||
VFNMSUB213PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0xAE /r ; s:FMA, t:VFMA, w:RW|R|R, e:2, x:IE|OE|UE|PE|DE
|
||||
VFNMSUB213PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0xAE /r ; s:FMA, t:VFMA, w:RW|R|R, e:2, x:IE|OE|UE|PE|DE
|
||||
VFNMSUB213SS ; Vdq,Hdq,Wss ; ; vex m:2 p:1 l:i w:0 0xAF /r ; s:FMA, t:VFMA, w:RW|R|R, e:3, x:IE|OE|UE|PE|DE
|
||||
VFNMSUB213SD ; Vdq,Hdq,Wsd ; ; vex m:2 p:1 l:i w:1 0xAF /r ; s:FMA, t:VFMA, w:RW|R|R, e:3, x:IE|OE|UE|PE|DE
|
||||
|
||||
# 0xB0 - 0xBF
|
||||
VCVTNEOPH2PS ; Vx,Mx ; ; vex m:2 p:0 l:x w:0 0xB0 /r:mem ; s:AVXNECONVERT, t:AVXNECONVERT, w:W|R, e:4
|
||||
@ -198,26 +214,26 @@ VBCSTNEBF162PS ; Vx,Mw ; ; vex m:2 p:2 l:x w:0
|
||||
VPMADD52LUQ ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0xB4 /r ; s:AVXIFMA, t:AVXIFMA, w:RW|R|R, e:4
|
||||
VPMADD52HUQ ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0xB5 /r ; s:AVXIFMA, t:AVXIFMA, w:RW|R|R, e:4
|
||||
|
||||
VFMADDSUB231PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0xB6 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2
|
||||
VFMADDSUB231PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0xB6 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2
|
||||
VFMSUBADD231PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0xB7 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2
|
||||
VFMSUBADD231PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0xB7 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2
|
||||
VFMADD231PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0xB8 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2
|
||||
VFMADD231PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0xB8 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2
|
||||
VFMADD231SS ; Vdq,Hdq,Wss ; ; vex m:2 p:1 l:i w:0 0xB9 /r ; s:FMA, t:VFMA, w:RW|R|R, e:3
|
||||
VFMADD231SD ; Vdq,Hdq,Wsd ; ; vex m:2 p:1 l:i w:1 0xB9 /r ; s:FMA, t:VFMA, w:RW|R|R, e:3
|
||||
VFMSUB231PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0xBA /r ; s:FMA, t:VFMA, w:RW|R|R, e:2
|
||||
VFMSUB231PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0xBA /r ; s:FMA, t:VFMA, w:RW|R|R, e:2
|
||||
VFMSUB231SS ; Vdq,Hdq,Wss ; ; vex m:2 p:1 l:i w:0 0xBB /r ; s:FMA, t:VFMA, w:RW|R|R, e:3
|
||||
VFMSUB231SD ; Vdq,Hdq,Wsd ; ; vex m:2 p:1 l:i w:1 0xBB /r ; s:FMA, t:VFMA, w:RW|R|R, e:3
|
||||
VFNMADD231PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0xBC /r ; s:FMA, t:VFMA, w:RW|R|R, e:2
|
||||
VFNMADD231PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0xBC /r ; s:FMA, t:VFMA, w:RW|R|R, e:2
|
||||
VFNMADD231SS ; Vdq,Hdq,Wss ; ; vex m:2 p:1 l:i w:0 0xBD /r ; s:FMA, t:VFMA, w:RW|R|R, e:3
|
||||
VFNMADD231SD ; Vdq,Hdq,Wsd ; ; vex m:2 p:1 l:i w:1 0xBD /r ; s:FMA, t:VFMA, w:RW|R|R, e:3
|
||||
VFNMSUB231PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0xBE /r ; s:FMA, t:VFMA, w:RW|R|R, e:2
|
||||
VFNMSUB231PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0xBE /r ; s:FMA, t:VFMA, w:RW|R|R, e:2
|
||||
VFNMSUB231SS ; Vdq,Hdq,Wss ; ; vex m:2 p:1 l:i w:0 0xBF /r ; s:FMA, t:VFMA, w:RW|R|R, e:3
|
||||
VFNMSUB231SD ; Vdq,Hdq,Wsd ; ; vex m:2 p:1 l:i w:1 0xBF /r ; s:FMA, t:VFMA, w:RW|R|R, e:3
|
||||
VFMADDSUB231PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0xB6 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2, x:IE|OE|UE|PE|DE
|
||||
VFMADDSUB231PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0xB6 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2, x:IE|OE|UE|PE|DE
|
||||
VFMSUBADD231PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0xB7 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2, x:IE|OE|UE|PE|DE
|
||||
VFMSUBADD231PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0xB7 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2, x:IE|OE|UE|PE|DE
|
||||
VFMADD231PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0xB8 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2, x:IE|OE|UE|PE|DE
|
||||
VFMADD231PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0xB8 /r ; s:FMA, t:VFMA, w:RW|R|R, e:2, x:IE|OE|UE|PE|DE
|
||||
VFMADD231SS ; Vdq,Hdq,Wss ; ; vex m:2 p:1 l:i w:0 0xB9 /r ; s:FMA, t:VFMA, w:RW|R|R, e:3, x:IE|OE|UE|PE|DE
|
||||
VFMADD231SD ; Vdq,Hdq,Wsd ; ; vex m:2 p:1 l:i w:1 0xB9 /r ; s:FMA, t:VFMA, w:RW|R|R, e:3, x:IE|OE|UE|PE|DE
|
||||
VFMSUB231PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0xBA /r ; s:FMA, t:VFMA, w:RW|R|R, e:2, x:IE|OE|UE|PE|DE
|
||||
VFMSUB231PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0xBA /r ; s:FMA, t:VFMA, w:RW|R|R, e:2, x:IE|OE|UE|PE|DE
|
||||
VFMSUB231SS ; Vdq,Hdq,Wss ; ; vex m:2 p:1 l:i w:0 0xBB /r ; s:FMA, t:VFMA, w:RW|R|R, e:3, x:IE|OE|UE|PE|DE
|
||||
VFMSUB231SD ; Vdq,Hdq,Wsd ; ; vex m:2 p:1 l:i w:1 0xBB /r ; s:FMA, t:VFMA, w:RW|R|R, e:3, x:IE|OE|UE|PE|DE
|
||||
VFNMADD231PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0xBC /r ; s:FMA, t:VFMA, w:RW|R|R, e:2, x:IE|OE|UE|PE|DE
|
||||
VFNMADD231PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0xBC /r ; s:FMA, t:VFMA, w:RW|R|R, e:2, x:IE|OE|UE|PE|DE
|
||||
VFNMADD231SS ; Vdq,Hdq,Wss ; ; vex m:2 p:1 l:i w:0 0xBD /r ; s:FMA, t:VFMA, w:RW|R|R, e:3, x:IE|OE|UE|PE|DE
|
||||
VFNMADD231SD ; Vdq,Hdq,Wsd ; ; vex m:2 p:1 l:i w:1 0xBD /r ; s:FMA, t:VFMA, w:RW|R|R, e:3, x:IE|OE|UE|PE|DE
|
||||
VFNMSUB231PS ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:0 0xBE /r ; s:FMA, t:VFMA, w:RW|R|R, e:2, x:IE|OE|UE|PE|DE
|
||||
VFNMSUB231PD ; Vx,Hx,Wx ; ; vex m:2 p:1 l:x w:1 0xBE /r ; s:FMA, t:VFMA, w:RW|R|R, e:2, x:IE|OE|UE|PE|DE
|
||||
VFNMSUB231SS ; Vdq,Hdq,Wss ; ; vex m:2 p:1 l:i w:0 0xBF /r ; s:FMA, t:VFMA, w:RW|R|R, e:3, x:IE|OE|UE|PE|DE
|
||||
VFNMSUB231SD ; Vdq,Hdq,Wsd ; ; vex m:2 p:1 l:i w:1 0xBF /r ; s:FMA, t:VFMA, w:RW|R|R, e:3, x:IE|OE|UE|PE|DE
|
||||
|
||||
VSHA512RNDS2 ; Vqq,Hqq,Udq ; ; vex m:2 p:3 l:1 w:0 0xCB /r:reg ; s:SHA512, t:SHA512, w:RW|R|R, e:6
|
||||
VSHA512MSG1 ; Vqq,Udq ; ; vex m:2 p:3 l:1 w:0 0xCC /r:reg ; s:SHA512, t:SHA512, w:RW|R, e:6
|
||||
|
||||
@ -10,10 +10,10 @@ VPBLENDD ; Vx,Hx,Wx,Ib ; ; vex m:3 p:1 l:x w:0
|
||||
VPERMILPS ; Vx,Wx,Ib ; ; vex m:3 p:1 l:x w:0 0x04 /r ib ; s:AVX, t:AVX, w:W|R|R, e:4
|
||||
VPERMILPD ; Vx,Wx,Ib ; ; vex m:3 p:1 l:x w:0 0x05 /r ib ; s:AVX, t:AVX, w:W|R|R, e:4
|
||||
VPERM2F128 ; Vqq,Hqq,Wqq,Ib ; ; vex m:3 p:1 l:1 w:0 0x06 /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:4
|
||||
VROUNDPS ; Vx,Wx,Ib ; ; vex m:3 p:1 l:x w:i 0x08 /r ib ; s:AVX, t:AVX, w:W|R|R, e:2
|
||||
VROUNDPD ; Vx,Wx,Ib ; ; vex m:3 p:1 l:x w:i 0x09 /r ib ; s:AVX, t:AVX, w:W|R|R, e:2
|
||||
VROUNDSS ; Vss,Hss,Wss,Ib ; ; vex m:3 p:1 l:i w:i 0x0A /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:3
|
||||
VROUNDSD ; Vsd,Hsd,Wsd,Ib ; ; vex m:3 p:1 l:i w:i 0x0B /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:3
|
||||
VROUNDPS ; Vx,Wx,Ib ; ; vex m:3 p:1 l:x w:i 0x08 /r ib ; s:AVX, t:AVX, w:W|R|R, e:2, x:IE|PE
|
||||
VROUNDPD ; Vx,Wx,Ib ; ; vex m:3 p:1 l:x w:i 0x09 /r ib ; s:AVX, t:AVX, w:W|R|R, e:2, x:IE|PE
|
||||
VROUNDSS ; Vss,Hss,Wss,Ib ; ; vex m:3 p:1 l:i w:i 0x0A /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:3, x:IE|PE
|
||||
VROUNDSD ; Vsd,Hsd,Wsd,Ib ; ; vex m:3 p:1 l:i w:i 0x0B /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:3, x:IE|PE
|
||||
VBLENDPS ; Vx,Hx,Wx,Ib ; ; vex m:3 p:1 l:x w:i 0x0C /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:4
|
||||
VBLENDPD ; Vx,Hx,Wx,Ib ; ; vex m:3 p:1 l:x w:i 0x0D /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:4
|
||||
VPBLENDW ; Vx,Hx,Wx,Ib ; ; vex m:3 p:1 l:x w:i 0x0E /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:4
|
||||
@ -32,8 +32,8 @@ VEXTRACTPS ; Md,Vdq,Ib ; ; vex m:3 p:1 l:0 w:i
|
||||
VEXTRACTPS ; Ry,Vdq,Ib ; ; vex m:3 p:1 l:0 w:i 0x17 /r:reg ib ; s:AVX, t:AVX, w:W|R|R, e:5
|
||||
VINSERTF128 ; Vqq,Hqq,Wdq,Ib ; ; vex m:3 p:1 l:1 w:0 0x18 /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:6
|
||||
VEXTRACTF128 ; Wdq,Vqq,Ib ; ; vex m:3 p:1 l:1 w:0 0x19 /r ib ; s:AVX, t:AVX, w:W|R|R, e:6
|
||||
VCVTPS2PH ; Wq,Vdq,Ib ; ; vex m:3 p:1 l:0 w:0 0x1D /r ib ; s:F16C, t:CONVERT, w:W|R|R, e:11
|
||||
VCVTPS2PH ; Wdq,Vqq,Ib ; ; vex m:3 p:1 l:1 w:0 0x1D /r ib ; s:F16C, t:CONVERT, w:W|R|R, e:11
|
||||
VCVTPS2PH ; Wq,Vdq,Ib ; ; vex m:3 p:1 l:0 w:0 0x1D /r ib ; s:F16C, t:CONVERT, w:W|R|R, e:11, x:IE|OE|UE|PE|DE
|
||||
VCVTPS2PH ; Wdq,Vqq,Ib ; ; vex m:3 p:1 l:1 w:0 0x1D /r ib ; s:F16C, t:CONVERT, w:W|R|R, e:11, x:IE|OE|UE|PE|DE
|
||||
|
||||
# 0x20 - 0x2F
|
||||
VPINSRB ; Vdq,Hdq,Mb,Ib ; ; vex m:3 p:1 l:0 w:i 0x20 /r:mem ib ; s:AVX, t:AVX, w:W|R|R|R, e:5
|
||||
@ -56,8 +56,8 @@ VINSERTI128 ; Vqq,Hqq,Wdq,Ib ; ; vex m:3 p:1 l:1 w:0
|
||||
VEXTRACTI128 ; Wdq,Vqq,Ib ; ; vex m:3 p:1 l:1 w:0 0x39 /r ib ; s:AVX2, t:AVX2, w:W|R|R|R, e:6
|
||||
|
||||
# 0x40 - 0x4F
|
||||
VDPPS ; Vx,Hx,Wx,Ib ; ; vex m:3 p:1 l:x w:i 0x40 /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:2
|
||||
VDPPD ; Vdq,Hdq,Wdq,Ib ; ; vex m:3 p:1 l:0 w:i 0x41 /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:2
|
||||
VDPPS ; Vx,Hx,Wx,Ib ; ; vex m:3 p:1 l:x w:i 0x40 /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:2, x:IE|OE|UE|PE|DE
|
||||
VDPPD ; Vdq,Hdq,Wdq,Ib ; ; vex m:3 p:1 l:0 w:i 0x41 /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:2, x:IE|OE|UE|PE|DE
|
||||
VMPSADBW ; Vx,Hx,Wx,Ib ; ; vex m:3 p:1 l:x w:i 0x42 /r ib ; s:AVX, t:AVX, w:W|R|R|R, e:4
|
||||
VPCLMULQDQ ; Vx,Hx,Wx,Ib ; ; vex m:3 p:1 l:x w:i 0x44 /r ib ; s:VPCLMULQDQ, t:VPCLMULQDQ, w:W|R|R|R, e:4
|
||||
VPERM2I128 ; Vqq,Hqq,Wqq,Ib ; ; vex m:3 p:1 l:1 w:0 0x46 /r ib ; s:AVX2, t:AVX2, w:W|R|R|R, e:6
|
||||
@ -70,54 +70,54 @@ VBLENDVPD ; Vx,Hx,Wx,Lx ; ; vex m:3 p:1 l:x w:0
|
||||
VPBLENDVB ; Vx,Hx,Wx,Lx ; ; vex m:3 p:1 l:x w:0 0x4C /r is4 ; s:AVX, t:AVX, w:W|R|R|R, e:4
|
||||
|
||||
# 0x50 - 0x5F
|
||||
VFMADDSUBPS ; Vx,Hx,Wx,Lx ; ; vex m:3 p:1 l:x w:0 0x5C /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R
|
||||
VFMADDSUBPS ; Vx,Hx,Lx,Wx ; ; vex m:3 p:1 l:x w:1 0x5C /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R
|
||||
VFMADDSUBPD ; Vx,Hx,Wx,Lx ; ; vex m:3 p:1 l:x w:0 0x5D /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R
|
||||
VFMADDSUBPD ; Vx,Hx,Lx,Wx ; ; vex m:3 p:1 l:x w:1 0x5D /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R
|
||||
VFMSUBADDPS ; Vx,Hx,Wx,Lx ; ; vex m:3 p:1 l:x w:0 0x5E /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R
|
||||
VFMSUBADDPS ; Vx,Hx,Lx,Wx ; ; vex m:3 p:1 l:x w:1 0x5E /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R
|
||||
VFMSUBADDPD ; Vx,Hx,Wx,Lx ; ; vex m:3 p:1 l:x w:0 0x5F /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R
|
||||
VFMSUBADDPD ; Vx,Hx,Lx,Wx ; ; vex m:3 p:1 l:x w:1 0x5F /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R
|
||||
VFMADDSUBPS ; Vx,Hx,Wx,Lx ; ; vex m:3 p:1 l:x w:0 0x5C /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFMADDSUBPS ; Vx,Hx,Lx,Wx ; ; vex m:3 p:1 l:x w:1 0x5C /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFMADDSUBPD ; Vx,Hx,Wx,Lx ; ; vex m:3 p:1 l:x w:0 0x5D /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFMADDSUBPD ; Vx,Hx,Lx,Wx ; ; vex m:3 p:1 l:x w:1 0x5D /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFMSUBADDPS ; Vx,Hx,Wx,Lx ; ; vex m:3 p:1 l:x w:0 0x5E /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFMSUBADDPS ; Vx,Hx,Lx,Wx ; ; vex m:3 p:1 l:x w:1 0x5E /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFMSUBADDPD ; Vx,Hx,Wx,Lx ; ; vex m:3 p:1 l:x w:0 0x5F /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFMSUBADDPD ; Vx,Hx,Lx,Wx ; ; vex m:3 p:1 l:x w:1 0x5F /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
|
||||
# 0x60 - 0x6F
|
||||
VPCMPESTRM ; Vdq,Wdq,Ib ; yAX,yDX,XMM0,Fv ; vex m:3 p:1 l:0 w:i 0x60 /r ib ; s:AVX, t:STTNI, w:R|R|R|R|R|W|W, f:PCMPSTR, e:4
|
||||
VPCMPESTRI ; Vdq,Wdq,Ib ; yAX,yDX,yCX,Fv ; vex m:3 p:1 l:0 w:i 0x61 /r ib ; s:AVX, t:STTNI, w:R|R|R|R|R|W|W, f:PCMPSTR, e:4
|
||||
VPCMPISTRM ; Vdq,Wdq,Ib ; XMM0,Fv ; vex m:3 p:1 l:0 w:i 0x62 /r ib ; s:AVX, t:STTNI, w:R|R|R|W|W, f:PCMPSTR, e:4
|
||||
VPCMPISTRI ; Vdq,Wdq,Ib ; yCX,Fv ; vex m:3 p:1 l:0 w:i 0x63 /r ib ; s:AVX, t:STTNI, w:R|R|R|W|W, f:PCMPSTR, e:4
|
||||
VFMADDPS ; Vx,Hx,Wx,Lx ; ; vex m:3 p:1 l:x w:0 0x68 /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R
|
||||
VFMADDPS ; Vx,Hx,Lx,Wx ; ; vex m:3 p:1 l:x w:1 0x68 /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R
|
||||
VFMADDPD ; Vx,Hx,Wx,Lx ; ; vex m:3 p:1 l:x w:0 0x69 /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R
|
||||
VFMADDPD ; Vx,Hx,Lx,Wx ; ; vex m:3 p:1 l:x w:1 0x69 /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R
|
||||
VFMADDSS ; Vdq,Hdq,Wss,Ldq ; ; vex m:3 p:1 l:x w:0 0x6A /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R
|
||||
VFMADDSS ; Vdq,Hdq,Ldq,Wss ; ; vex m:3 p:1 l:x w:1 0x6A /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R
|
||||
VFMADDSD ; Vdq,Hdq,Wsd,Ldq ; ; vex m:3 p:1 l:x w:0 0x6B /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R
|
||||
VFMADDSD ; Vdq,Hdq,Ldq,Wsd ; ; vex m:3 p:1 l:x w:1 0x6B /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R
|
||||
VFMSUBPS ; Vx,Hx,Wx,Lx ; ; vex m:3 p:1 l:x w:0 0x6C /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R
|
||||
VFMSUBPS ; Vx,Hx,Lx,Wx ; ; vex m:3 p:1 l:x w:1 0x6C /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R
|
||||
VFMSUBPD ; Vx,Hx,Wx,Lx ; ; vex m:3 p:1 l:x w:0 0x6D /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R
|
||||
VFMSUBPD ; Vx,Hx,Lx,Wx ; ; vex m:3 p:1 l:x w:1 0x6D /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R
|
||||
VFMSUBSS ; Vdq,Hdq,Wss,Ldq ; ; vex m:3 p:1 l:x w:0 0x6E /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R
|
||||
VFMSUBSS ; Vdq,Hdq,Ldq,Wss ; ; vex m:3 p:1 l:x w:1 0x6E /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R
|
||||
VFMSUBSD ; Vdq,Hdq,Wsd,Ldq ; ; vex m:3 p:1 l:x w:0 0x6F /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R
|
||||
VFMSUBSD ; Vdq,Hdq,Ldq,Wsd ; ; vex m:3 p:1 l:x w:1 0x6F /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R
|
||||
VFMADDPS ; Vx,Hx,Wx,Lx ; ; vex m:3 p:1 l:x w:0 0x68 /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFMADDPS ; Vx,Hx,Lx,Wx ; ; vex m:3 p:1 l:x w:1 0x68 /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFMADDPD ; Vx,Hx,Wx,Lx ; ; vex m:3 p:1 l:x w:0 0x69 /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFMADDPD ; Vx,Hx,Lx,Wx ; ; vex m:3 p:1 l:x w:1 0x69 /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFMADDSS ; Vdq,Hdq,Wss,Ldq ; ; vex m:3 p:1 l:x w:0 0x6A /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFMADDSS ; Vdq,Hdq,Ldq,Wss ; ; vex m:3 p:1 l:x w:1 0x6A /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFMADDSD ; Vdq,Hdq,Wsd,Ldq ; ; vex m:3 p:1 l:x w:0 0x6B /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFMADDSD ; Vdq,Hdq,Ldq,Wsd ; ; vex m:3 p:1 l:x w:1 0x6B /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFMSUBPS ; Vx,Hx,Wx,Lx ; ; vex m:3 p:1 l:x w:0 0x6C /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFMSUBPS ; Vx,Hx,Lx,Wx ; ; vex m:3 p:1 l:x w:1 0x6C /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFMSUBPD ; Vx,Hx,Wx,Lx ; ; vex m:3 p:1 l:x w:0 0x6D /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFMSUBPD ; Vx,Hx,Lx,Wx ; ; vex m:3 p:1 l:x w:1 0x6D /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFMSUBSS ; Vdq,Hdq,Wss,Ldq ; ; vex m:3 p:1 l:x w:0 0x6E /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFMSUBSS ; Vdq,Hdq,Ldq,Wss ; ; vex m:3 p:1 l:x w:1 0x6E /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFMSUBSD ; Vdq,Hdq,Wsd,Ldq ; ; vex m:3 p:1 l:x w:0 0x6F /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFMSUBSD ; Vdq,Hdq,Ldq,Wsd ; ; vex m:3 p:1 l:x w:1 0x6F /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
|
||||
# 0x70 - 0x7F
|
||||
VFNMADDPS ; Vx,Hx,Wx,Lx ; ; vex m:3 p:1 l:x w:0 0x78 /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R
|
||||
VFNMADDPS ; Vx,Hx,Lx,Wx ; ; vex m:3 p:1 l:x w:1 0x78 /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R
|
||||
VFNMADDPD ; Vx,Hx,Wx,Lx ; ; vex m:3 p:1 l:x w:0 0x79 /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R
|
||||
VFNMADDPD ; Vx,Hx,Lx,Wx ; ; vex m:3 p:1 l:x w:1 0x79 /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R
|
||||
VFNMADDSS ; Vdq,Hdq,Wss,Ldq ; ; vex m:3 p:1 l:x w:0 0x7A /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R
|
||||
VFNMADDSS ; Vdq,Hdq,Ldq,Wss ; ; vex m:3 p:1 l:x w:1 0x7A /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R
|
||||
VFNMADDSD ; Vdq,Hdq,Wsd,Ldq ; ; vex m:3 p:1 l:x w:0 0x7B /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R
|
||||
VFNMADDSD ; Vdq,Hdq,Ldq,Wsd ; ; vex m:3 p:1 l:x w:1 0x7B /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R
|
||||
VFNMSUBPS ; Vx,Hx,Wx,Lx ; ; vex m:3 p:1 l:x w:0 0x7C /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R
|
||||
VFNMSUBPS ; Vx,Hx,Lx,Wx ; ; vex m:3 p:1 l:x w:1 0x7C /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R
|
||||
VFNMSUBPD ; Vx,Hx,Wx,Lx ; ; vex m:3 p:1 l:x w:0 0x7D /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R
|
||||
VFNMSUBPD ; Vx,Hx,Lx,Wx ; ; vex m:3 p:1 l:x w:1 0x7D /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R
|
||||
VFNMSUBSS ; Vdq,Hdq,Wss,Ldq ; ; vex m:3 p:1 l:x w:0 0x7E /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R
|
||||
VFNMSUBSS ; Vdq,Hdq,Ldq,Wss ; ; vex m:3 p:1 l:x w:1 0x7E /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R
|
||||
VFNMSUBSD ; Vdq,Hdq,Wsd,Ldq ; ; vex m:3 p:1 l:x w:0 0x7F /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R
|
||||
VFNMSUBSD ; Vdq,Hdq,Ldq,Wsd ; ; vex m:3 p:1 l:x w:1 0x7F /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R
|
||||
VFNMADDPS ; Vx,Hx,Wx,Lx ; ; vex m:3 p:1 l:x w:0 0x78 /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFNMADDPS ; Vx,Hx,Lx,Wx ; ; vex m:3 p:1 l:x w:1 0x78 /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFNMADDPD ; Vx,Hx,Wx,Lx ; ; vex m:3 p:1 l:x w:0 0x79 /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFNMADDPD ; Vx,Hx,Lx,Wx ; ; vex m:3 p:1 l:x w:1 0x79 /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFNMADDSS ; Vdq,Hdq,Wss,Ldq ; ; vex m:3 p:1 l:x w:0 0x7A /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFNMADDSS ; Vdq,Hdq,Ldq,Wss ; ; vex m:3 p:1 l:x w:1 0x7A /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFNMADDSD ; Vdq,Hdq,Wsd,Ldq ; ; vex m:3 p:1 l:x w:0 0x7B /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFNMADDSD ; Vdq,Hdq,Ldq,Wsd ; ; vex m:3 p:1 l:x w:1 0x7B /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFNMSUBPS ; Vx,Hx,Wx,Lx ; ; vex m:3 p:1 l:x w:0 0x7C /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFNMSUBPS ; Vx,Hx,Lx,Wx ; ; vex m:3 p:1 l:x w:1 0x7C /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFNMSUBPD ; Vx,Hx,Wx,Lx ; ; vex m:3 p:1 l:x w:0 0x7D /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFNMSUBPD ; Vx,Hx,Lx,Wx ; ; vex m:3 p:1 l:x w:1 0x7D /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFNMSUBSS ; Vdq,Hdq,Wss,Ldq ; ; vex m:3 p:1 l:x w:0 0x7E /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFNMSUBSS ; Vdq,Hdq,Ldq,Wss ; ; vex m:3 p:1 l:x w:1 0x7E /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFNMSUBSD ; Vdq,Hdq,Wsd,Ldq ; ; vex m:3 p:1 l:x w:0 0x7F /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
VFNMSUBSD ; Vdq,Hdq,Ldq,Wsd ; ; vex m:3 p:1 l:x w:1 0x7F /r is4 ; s:FMA4, t:FMA4, w:W|R|R|R, x:IE|OE|UE|PE|DE
|
||||
|
||||
# 0xC0 - 0xCF
|
||||
VGF2P8AFFINEQB ; Vx,Hx,Wx,Ib ; ; vex m:3 p:1 l:x w:1 0xCE /r ib ; s:GFNI, t:GFNI, w:W|R|R|R, e:4
|
||||
|
||||
14
isagenerator/instructions/table_vex_5.dat
Normal file
14
isagenerator/instructions/table_vex_5.dat
Normal file
@ -0,0 +1,14 @@
|
||||
#
|
||||
# Copyright (c) 2024 Bitdefender
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
#
|
||||
|
||||
T2RPNTLVWZ0RS ; rTt+1,Mt ; ; vex m:5 p:0 l:0 w:0 0xF8 /r:mem sibmem ; s:AMXTRANSPOSE, t:AMX, w:W|R, m:NOTSX|O64, e:AMX_E11
|
||||
T2RPNTLVWZ1RS ; rTt+1,Mt ; ; vex m:5 p:1 l:0 w:0 0xF8 /r:mem sibmem ; s:AMXTRANSPOSE, t:AMX, w:W|R, m:NOTSX|O64, e:AMX_E11
|
||||
T2RPNTLVWZ0RST1 ; rTt+1,Mt ; ; vex m:5 p:0 l:0 w:0 0xF9 /r:mem sibmem ; s:AMXTRANSPOSE, t:AMX, w:W|R, m:NOTSX|O64, e:AMX_E11
|
||||
T2RPNTLVWZ1RST1 ; rTt+1,Mt ; ; vex m:5 p:1 l:0 w:0 0xF9 /r:mem sibmem ; s:AMXTRANSPOSE, t:AMX, w:W|R, m:NOTSX|O64, e:AMX_E11
|
||||
|
||||
TDPBF8PS ; rTt,mTt,vTt ; ; vex m:5 p:0 l:0 w:0 0xFD /r:reg ; s:AMXFP8, t:AMX, w:RW|R|R, m:NOTSX|O64, e:AMX_E4
|
||||
TDPHF8PS ; rTt,mTt,vTt ; ; vex m:5 p:1 l:0 w:0 0xFD /r:reg ; s:AMXFP8, t:AMX, w:RW|R|R, m:NOTSX|O64, e:AMX_E4
|
||||
TDPHBF8PS ; rTt,mTt,vTt ; ; vex m:5 p:2 l:0 w:0 0xFD /r:reg ; s:AMXFP8, t:AMX, w:RW|R|R, m:NOTSX|O64, e:AMX_E4
|
||||
TDPBHF8PS ; rTt,mTt,vTt ; ; vex m:5 p:3 l:0 w:0 0xFD /r:reg ; s:AMXFP8, t:AMX, w:RW|R|R, m:NOTSX|O64, e:AMX_E4
|
||||
@ -3,5 +3,7 @@
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
#
|
||||
|
||||
WRMSRNS ; Id,Rq ; MSR ; vex m:7 p:2 l:0 w:0 0xF6 /0:reg id ; s:MSR_IMM, t:SYSTEM, w:R|R|W, m:KERNEL|O64
|
||||
RDMSR ; Rq,Id ; MSR ; vex m:7 p:3 l:0 w:0 0xF6 /0:reg id ; s:MSR_IMM, t:SYSTEM, w:W|R|R, m:KERNEL|O64
|
||||
UWRMSR ; Id,Rq ; MSR ; vex m:7 p:2 l:0 w:0 0xF8 /0:reg id ; s:USER_MSR, t:USER_MSR, w:R|R|W, m:O64
|
||||
URDMSR ; Rq,Id ; MSR ; vex m:7 p:3 l:0 w:0 0xF8 /0:reg id ; s:USER_MSR, t:USER_MSR, w:W|R|R, m:O64
|
||||
@ -200,7 +200,6 @@
|
||||
</ItemDefinitionGroup>
|
||||
<ItemGroup>
|
||||
<None Include="disasmlib.py" />
|
||||
<None Include="generate_encodings.py" />
|
||||
<None Include="generate_tables.py" />
|
||||
<None Include="instructions\cpuid.dat" />
|
||||
<None Include="instructions\flags.dat" />
|
||||
@ -221,6 +220,7 @@
|
||||
<None Include="instructions\table_vex_1.dat" />
|
||||
<None Include="instructions\table_vex_2.dat" />
|
||||
<None Include="instructions\table_vex_3.dat" />
|
||||
<None Include="instructions\table_vex_5.dat" />
|
||||
<None Include="instructions\table_vex_7.dat" />
|
||||
<None Include="instructions\table_xop.dat" />
|
||||
</ItemGroup>
|
||||
|
||||
@ -96,14 +96,14 @@
|
||||
<None Include="instructions\table_evex_4.dat">
|
||||
<Filter>data\table evex</Filter>
|
||||
</None>
|
||||
<None Include="generate_encodings.py">
|
||||
<Filter>Source Files</Filter>
|
||||
</None>
|
||||
<None Include="instructions\table_vex_7.dat">
|
||||
<Filter>data\table vex</Filter>
|
||||
</None>
|
||||
<None Include="instructions\table_evex_7.dat">
|
||||
<Filter>data\table evex</Filter>
|
||||
</None>
|
||||
<None Include="instructions\table_vex_5.dat">
|
||||
<Filter>data\table vex</Filter>
|
||||
</None>
|
||||
</ItemGroup>
|
||||
</Project>
|
||||
Loading…
Reference in New Issue
Block a user