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Author SHA1 Message Date
BITDEFENDER\vlutas
7a254037b0 Added support for AMD RMPQUERY instruction. 2022-10-27 12:37:02 +03:00
Ionel-Cristinel ANICHITEI
f75e1e28cd bdshemu_fuzz: Build with -maes 2022-10-04 13:31:02 +03:00
Ionel-Cristinel ANICHITEI
22d7c14c51 rsbddisasm: Update bindings 2022-10-04 13:17:54 +03:00
BITDEFENDER\vlutas
9ba1e6a2f9 Added support for new Intel instructions, per Intel ISA extensions document #319433-046 (September 2022): PREFETCHITI, RAO-INT, CMPCCXADD, WRMSRNS, MSRLIST, AMX-FP16, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8. 
Multiple minor fixes to existing instructions.
Moved x86 decoding tests in a separate directory & improved the test script.
 2022-10-04 12:22:59 +03:00
BITDEFENDER\vlutas
4596dbda51 Add copyright info when auto-generating files. 2022-09-10 23:15:00 +03:00
BITDEFENDER\vlutas
b109990ba2 Removed some unneeded code. 2022-08-09 20:15:30 +03:00
BITDEFENDER\vlutas
47da322ea5 Improved upper bits handling for SSE/AVX operations. 
Improved POPF handling when 16 bit operand size is used.
Fixed typo in PUNPCKLBW emulation.
 2022-08-09 20:02:45 +03:00
BITDEFENDER\vlutas
2fc491d51d Handle reserved bits in RFLAGS when setting the entire register value. 2022-08-08 12:02:00 +03:00
BITDEFENDER\vlutas
f62c8a2238 https://github.com/bitdefender/bddisasm/issues/70 - fixed OF setting on ROR. 2022-08-01 15:46:38 +03:00
BITDEFENDER\vlutas
9c6b5429c9 Fixed pybddisasm version. 2022-08-01 14:17:07 +03:00
BITDEFENDER\vlutas
d3fd900903 Fixed OF on SHL and SHR with one bit shifts. 2022-08-01 14:13:27 +03:00
BITDEFENDER\vlutas
bf81c647e3 Make sure all flags are set for CMPXCHG (this was left intentionally incomplete). 
Make sure we clear upper bits of the 256/512 bit SSE register.
 2022-07-19 11:03:17 +03:00
BITDEFENDER\vlutas
6dda2c122c Make sure upper 32 bit of a CMOV destination register is cleared to 0 even if the condition is not satisfied 2022-07-16 12:21:46 +03:00
BITDEFENDER\vlutas
1805a9edec Fixed flag setting for ADC, SBB, SAR and IMUL instructions. 2022-07-14 13:42:37 +03:00
vlutas
e930d49713
Merge pull request #54 from ianichitei/master 
ci: Install Windows SDK 18362 when building on Windows
 2022-02-17 15:47:09 +02:00
Anichitei Ionel-Cristinel
f900388260
Update rust.yml 2022-02-17 11:37:15 +02:00
Anichitei Ionel-Cristinel
59255c4ea6
Update ci.yml 2022-02-17 11:33:26 +02:00
Anichitei Ionel-Cristinel
90820faba4
ci: Setup Windows SDK 18362 2022-02-17 11:12:30 +02:00
Anichitei Ionel-Cristinel
f0804645f3
Update ci.yml 2022-02-17 10:59:04 +02:00
Anichitei Ionel-Cristinel
4525860ec8
Fix a typo in the install instructions 2022-01-25 17:31:03 +02:00
Ionel-Cristinel ANICHITEI
73b7c4ea96 rsbddisasm: Fix no-std category 2022-01-05 14:40:26 +02:00
Ionel-Cristinel ANICHITEI
21c584b436 rsbddisasm: Change version to 0.2.0 2022-01-05 14:31:30 +02:00
BITDEFENDER\vlutas
70db095765 Updates Rust binding to the latest version. 
Fixed build in disasmtool_lix.
 2022-01-05 14:17:13 +02:00
BITDEFENDER\vlutas
fe6a937f51 Switched to internally defined types. 
WRUSSD and WRUSSQ cannot be executed when CPL != 0.
 2022-01-05 14:03:13 +02:00
Anichitei Ionel-Cristinel
08103713b2
Merge pull request #53 from ekilmer/fix-bddisasm-makefile 
Add missing sources to Makefile for bddisasm
 2022-01-04 17:43:15 +02:00
Eric Kilmer
68c7c4a066
Add missing sources to Makefile for bddisasm 2022-01-04 09:52:34 -05:00
BITDEFENDER\vlutas
63e3ee22a9 Fixed High8 handling in NdGetFullAccessMap. 2022-01-03 12:25:35 +02:00
BITDEFENDER\vlutas
c9d4dbca0f Added missing modifications. 2021-12-03 12:53:22 +02:00
BITDEFENDER\vlutas
2f50ce9b4e Improved REG_ID macros - make sure we include block addressing and High8 designator in the reg ID. Alsom, make sure the register size fits in, since the new tile register can be 1K in size, which previously overflowed... 2021-12-03 12:44:57 +02:00
BITDEFENDER\vlutas
4ff620cb76 Added bdhelpers to CMake. 2021-11-03 09:34:04 +02:00
Anichitei Ionel-Cristinel
dac2092c17
Rust bindings: Remove ND_CAT_FRED 2021-11-02 11:39:41 +02:00
BITDEFENDER\vlutas
7572adaeba Fixed INSTRUX size in setup.py. 2021-11-02 11:34:17 +02:00
BITDEFENDER\vlutas
7749e06b9d Removed ND_CAT_FRED. 2021-11-02 11:30:11 +02:00
BITDEFENDER\vlutas
656916d92d Added missing paranthesis. 2021-11-02 11:26:52 +02:00
BITDEFENDER\vlutas
433e723e07 Implemented a reverse oprand lookup table. It holds pointers to relevant operands inside INSTRUX, for quick lookup. 
Moved helper functions in bdhelpers.c.
Added a dedicated BranchInfo field inside INSTRUX, containing the most relevant branch information.
 2021-11-02 11:22:22 +02:00
Ionel-Cristinel ANICHITEI
def76f8633 rsbddisasm: Fix keywords 2021-10-20 12:24:11 +03:00
Ionel-Cristinel ANICHITEI
1e78d15878 bddisasm-sys: Fix keywords 2021-10-20 12:12:02 +03:00
vlutas
62cdbdc068
Merge pull request #52 from ianichitei/master 
Add Rust bindings
 2021-10-20 11:59:02 +03:00
Ionel-Cristinel ANICHITEI
7d50c7edd5 Update README 2021-10-20 10:06:25 +03:00
Ionel-Cristinel ANICHITEI
584150cb44 Move rsbddisasm to the bindings directory 2021-10-20 10:03:16 +03:00
Ionel-Cristinel ANICHITEI
af3d23e3ff Move pybddisasm to the bindings directory 2021-10-20 09:32:50 +03:00
Anichitei Ionel-Cristinel
146ebc55c5
ci: Attempt to fix the Windows build 2021-10-19 18:20:35 +03:00
Anichitei Ionel-Cristinel
5ea879a9a0
ci: Fix cargo fmt step 2021-10-19 18:15:51 +03:00
Anichitei Ionel-Cristinel
b57bf183b1
Add Rust workflow 2021-10-19 18:06:35 +03:00
Ionel-Cristinel ANICHITEI
51dbf5fb0a Initial Rust bindings implementation 2021-10-19 17:54:48 +03:00
BITDEFENDER\vlutas
4a485853b6 Fixed pybddisasm version. 2021-10-19 17:37:43 +03:00
BITDEFENDER\vlutas
412f065965 Moved the formatting function in a dedicated source file. 
Added support for SIDT and RDTSC in bdshemu.
 2021-10-19 17:33:15 +03:00
Andrei Vlad LUTAS
38592edf31 Removed old test files. 2021-08-31 13:49:29 +03:00
Andrei Vlad LUTAS
08096172cc Multiple improvements 
- New shemu flag - SHEMU_FLAG_SIDT, set when sheu encounters a SIDT in ring0.
- Added the CET Tracked flag to SYSCLAL, SYSENTER and INT n instructions.
- Fixed Do Not Track prefix recognition for CALL and JMP in long-mode.
- Fixed MONITOR and MONITORX implicit operands - the rAX register encodes a virtual address that will be used as the monitored range. That address is subject to a 1 byte load.
- Fixed RMPADJUST and RMPUPDATE implicit operands - the rAX register encodes a virtual address, and the rCX register encodes a virtual address of the RMP updated entry.
 2021-08-31 13:37:50 +03:00
Andrei Vlad LUTAS
5a617986b7 Added new shemu flag: SHEMU_FLAG_SUD_ACCESS is raised whenever the code accesses the SharedUserData page. 2021-08-16 12:34:41 +03:00