vlutas
c282f06215
Add support for SIMD Exceptions reporting and new x86 ISAs ( #108 )
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* Add support for SIMD exceptions reporting in INSTRUX.
* Add support for new ISAs: MOVRS, MSR_IMM, AMX-FP8, AMX-TRANSPOSE, AMX-TF32, AMX-AVX512, AMX-MOVRS, EVEX-encoded SM4.
Co-authored-by: ianichitei (Rust bindings)
2024-11-07 12:15:29 +02:00
Andrei KISARI
d8f3046391
Improve bddisasm and bdshemu test scripts.
2024-09-16 12:47:03 +03:00
Andrei Vlad LUTAS
37a8c94bc7
Applied some of the syntax recomandations from https://cdrdv2.intel.com/v1/dl/getContent/817241 .
2024-03-04 12:48:18 +02:00
Andrei Vlad LUTAS
02cbe6a298
https://github.com/bitdefender/bddisasm/issues/87 - added missing R access for the rIP operand for SYSCALL instructions; added missing SCS, rCX and rDX operands for SYSEXIT instruction.
2024-02-27 09:45:05 +02:00
Andrei Vlad LUTAS
3df189f093
https://github.com/bitdefender/bddisasm/issues/87 - Fixed CALL instruction access for rIP operand - it must include read access, as the instruction pointer is saved on the stack.
2024-02-26 20:53:42 +02:00
Andrei Vlad LUTAS
fad9c7e35c
BDDISASM v2.1.0 release - please consult the CHANGELOG for details about the modifications.
2024-02-20 13:39:22 +02:00
Andrei Vlad LUTAS
f53cbc51e2
Added support for new Intel ISA, per Intel® Architecture Instruction Set Extensions and Future Features document #319433-049 (June 2023): AVX-NNI-INT16, SHA512, SM3, SM4, TSE.
2023-07-21 09:38:49 +03:00
BITDEFENDER\vlutas
124521beb5
Added support for Intel AMX-COMPLEX instructions.
2023-04-05 09:45:07 +03:00
BITDEFENDER\vlutas
7a254037b0
Added support for AMD RMPQUERY instruction.
2022-10-27 12:37:02 +03:00
BITDEFENDER\vlutas
9ba1e6a2f9
Added support for new Intel instructions, per Intel ISA extensions document #319433-046 (September 2022): PREFETCHITI, RAO-INT, CMPCCXADD, WRMSRNS, MSRLIST, AMX-FP16, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8.
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Multiple minor fixes to existing instructions.
Moved x86 decoding tests in a separate directory & improved the test script.
2022-10-04 12:22:59 +03:00
