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amx
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Added support for Intel AMX-COMPLEX instructions.
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2023-04-05 09:45:07 +03:00 |
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apx
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BDDISASM v2.1.0 release - please consult the CHANGELOG for details about the modifications.
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2024-02-20 13:39:22 +02:00 |
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avx
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Added support for new Intel ISA, per Intel® Architecture Instruction Set Extensions and Future Features document #319433-049 (June 2023): AVX-NNI-INT16, SHA512, SM3, SM4, TSE.
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2023-07-21 09:38:49 +03:00 |
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avx512
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Added support for new Intel instructions, per Intel ISA extensions document #319433-046 (September 2022): PREFETCHITI, RAO-INT, CMPCCXADD, WRMSRNS, MSRLIST, AMX-FP16, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8.
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2022-10-04 12:22:59 +03:00 |
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basic
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https://github.com/bitdefender/bddisasm/issues/87 - added missing R access for the rIP operand for SYSCALL instructions; added missing SCS, rCX and rDX operands for SYSEXIT instruction.
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2024-02-27 09:45:05 +02:00 |
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cet
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https://github.com/bitdefender/bddisasm/issues/87 - Fixed CALL instruction access for rIP operand - it must include read access, as the instruction pointer is saved on the stack.
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2024-02-26 20:53:42 +02:00 |
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cmpccxadd
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BDDISASM v2.1.0 release - please consult the CHANGELOG for details about the modifications.
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2024-02-20 13:39:22 +02:00 |
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fred
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BDDISASM v2.1.0 release - please consult the CHANGELOG for details about the modifications.
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2024-02-20 13:39:22 +02:00 |
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kl
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Added support for new Intel instructions, per Intel ISA extensions document #319433-046 (September 2022): PREFETCHITI, RAO-INT, CMPCCXADD, WRMSRNS, MSRLIST, AMX-FP16, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8.
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2022-10-04 12:22:59 +03:00 |
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msr
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Added support for new Intel instructions, per Intel ISA extensions document #319433-046 (September 2022): PREFETCHITI, RAO-INT, CMPCCXADD, WRMSRNS, MSRLIST, AMX-FP16, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8.
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2022-10-04 12:22:59 +03:00 |
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prefetchit
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Added support for new Intel instructions, per Intel ISA extensions document #319433-046 (September 2022): PREFETCHITI, RAO-INT, CMPCCXADD, WRMSRNS, MSRLIST, AMX-FP16, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8.
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2022-10-04 12:22:59 +03:00 |
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rao-int
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Added support for new Intel instructions, per Intel ISA extensions document #319433-046 (September 2022): PREFETCHITI, RAO-INT, CMPCCXADD, WRMSRNS, MSRLIST, AMX-FP16, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8.
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2022-10-04 12:22:59 +03:00 |
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sha512
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Added support for new Intel ISA, per Intel® Architecture Instruction Set Extensions and Future Features document #319433-049 (June 2023): AVX-NNI-INT16, SHA512, SM3, SM4, TSE.
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2023-07-21 09:38:49 +03:00 |
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simd
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Added support for new Intel instructions, per Intel ISA extensions document #319433-046 (September 2022): PREFETCHITI, RAO-INT, CMPCCXADD, WRMSRNS, MSRLIST, AMX-FP16, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8.
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2022-10-04 12:22:59 +03:00 |
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sm
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Added support for new Intel ISA, per Intel® Architecture Instruction Set Extensions and Future Features document #319433-049 (June 2023): AVX-NNI-INT16, SHA512, SM3, SM4, TSE.
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2023-07-21 09:38:49 +03:00 |
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special
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https://github.com/bitdefender/bddisasm/issues/87 - added missing R access for the rIP operand for SYSCALL instructions; added missing SCS, rCX and rDX operands for SYSEXIT instruction.
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2024-02-27 09:45:05 +02:00 |
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tdx
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Added support for new Intel instructions, per Intel ISA extensions document #319433-046 (September 2022): PREFETCHITI, RAO-INT, CMPCCXADD, WRMSRNS, MSRLIST, AMX-FP16, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8.
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2022-10-04 12:22:59 +03:00 |
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tse
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Added support for new Intel ISA, per Intel® Architecture Instruction Set Extensions and Future Features document #319433-049 (June 2023): AVX-NNI-INT16, SHA512, SM3, SM4, TSE.
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2023-07-21 09:38:49 +03:00 |
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uintr
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Added support for new Intel instructions, per Intel ISA extensions document #319433-046 (September 2022): PREFETCHITI, RAO-INT, CMPCCXADD, WRMSRNS, MSRLIST, AMX-FP16, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8.
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2022-10-04 12:22:59 +03:00 |
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usermsr
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BDDISASM v2.1.0 release - please consult the CHANGELOG for details about the modifications.
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2024-02-20 13:39:22 +02:00 |
