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bddisasm/isagenerator/instructions/cpuid.dat

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Switched from nil to n/a naming for absent operands, as it is more obvious.
2023-02-08 15:44:45 +00:00
#
# Copyright (c) 2020 Bitdefender
# SPDX-License-Identifier: Apache-2.0
#
Initial commit.
2020-07-21 08:19:18 +00:00
# CPUID feature flags.
Fixed some typos. Added SECURITY.md file.
2020-07-22 18:47:25 +00:00
# Syntax: NAME : leaf, subleaf, register, bit
Initial commit.
2020-07-21 08:19:18 +00:00
# NAME can be anything, but it should match an ISA extension type.
# leaf - CPUID leaf value (eax input value)
# subleaf - CPUID subleaf (ecx input value). Use 0xFFFFFFFF if not used.
# register - CPUID output register containing the bit
# bit - the bit inside the register which indicates if the instruction is present or not
FPU : 0x00000001, 0xFFFFFFFF, EDX, 0
MSR : 0x00000001, 0xFFFFFFFF, EDX, 5
CX8 : 0x00000001, 0xFFFFFFFF, EDX, 8
SEP : 0x00000001, 0xFFFFFFFF, EDX, 11
CMOV : 0x00000001, 0xFFFFFFFF, EDX, 15
CLFSH : 0x00000001, 0xFFFFFFFF, EDX, 19
MMX : 0x00000001, 0xFFFFFFFF, EDX, 23
FXSAVE : 0x00000001, 0xFFFFFFFF, EDX, 24
SSE : 0x00000001, 0xFFFFFFFF, EDX, 25
SSE2 : 0x00000001, 0xFFFFFFFF, EDX, 26
SSE3 : 0x00000001, 0xFFFFFFFF, ECX, 0
PCLMULQDQ : 0x00000001, 0xFFFFFFFF, ECX, 1
MONITOR : 0x00000001, 0xFFFFFFFF, ECX, 3
VTX : 0x00000001, 0xFFFFFFFF, ECX, 5
SMX : 0x00000001, 0xFFFFFFFF, ECX, 6
SSSE3 : 0x00000001, 0xFFFFFFFF, ECX, 9
FMA : 0x00000001, 0xFFFFFFFF, ECX, 12
SSE4 : 0x00000001, 0xFFFFFFFF, ECX, 19
SSE42 : 0x00000001, 0xFFFFFFFF, ECX, 20
MOVBE : 0x00000001, 0xFFFFFFFF, ECX, 22
POPCNT : 0x00000001, 0xFFFFFFFF, ECX, 23
AES : 0x00000001, 0xFFFFFFFF, ECX, 25
XSAVE : 0x00000001, 0xFFFFFFFF, ECX, 26
AVX : 0x00000001, 0xFFFFFFFF, ECX, 28
F16C : 0x00000001, 0xFFFFFFFF, ECX, 29
RDRAND : 0x00000001, 0xFFFFFFFF, ECX, 30
Added support for new Intel instructions, per Intel ISA extensions document #319433-046 (September 2022): PREFETCHITI, RAO-INT, CMPCCXADD, WRMSRNS, MSRLIST, AMX-FP16, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8. Multiple minor fixes to existing instructions. Moved x86 decoding tests in a separate directory & improved the test script.
2022-10-04 09:22:59 +00:00
Initial commit.
2020-07-21 08:19:18 +00:00
RDWRFSGS : 0x00000007, 0x00000000, EBX, 0
SGX : 0x00000007, 0x00000000, EBX, 2
BMI1 : 0x00000007, 0x00000000, EBX, 3
HLE : 0x00000007, 0x00000000, EBX, 4
AVX2 : 0x00000007, 0x00000000, EBX, 5
BMI2 : 0x00000007, 0x00000000, EBX, 8
INVPCID : 0x00000007, 0x00000000, EBX, 10
RTM : 0x00000007, 0x00000000, EBX, 11
MPX : 0x00000007, 0x00000000, EBX, 14
AVX512F : 0x00000007, 0x00000000, EBX, 16
AVX512DQ : 0x00000007, 0x00000000, EBX, 17
RDSEED : 0x00000007, 0x00000000, EBX, 18
ADX : 0x00000007, 0x00000000, EBX, 19
SMAP : 0x00000007, 0x00000000, EBX, 20
AVX512IFMA : 0x00000007, 0x00000000, EBX, 21
Removed support for PCOMMIT and CL1INVMB (not implemented by any x86/x64 CPUs), and marked MOV to/from test registers as being invalid in long mode. Fixed https://github.com/bitdefender/bddisasm/issues/24 Fixed https://github.com/bitdefender/bddisasm/issues/25 Fixed https://github.com/bitdefender/bddisasm/issues/26
2020-11-09 07:18:46 +00:00
# Dropped by Intel.
#PCOMMIT : 0x00000007, 0x00000000, EBX, 22
Initial commit.
2020-07-21 08:19:18 +00:00
CLFSHOPT : 0x00000007, 0x00000000, EBX, 23
CLWB : 0x00000007, 0x00000000, EBX, 24
AVX512PF : 0x00000007, 0x00000000, EBX, 26
AVX512ER : 0x00000007, 0x00000000, EBX, 27
AVX512CD : 0x00000007, 0x00000000, EBX, 28
SHA : 0x00000007, 0x00000000, EBX, 29
AVX512BW : 0x00000007, 0x00000000, EBX, 30
PREFETCHWT1 : 0x00000007, 0x00000000, ECX, 0
AVX512VBMI : 0x00000007, 0x00000000, ECX, 1
PKU : 0x00000007, 0x00000000, ECX, 3
WAITPKG : 0x00000007, 0x00000000, ECX, 5
AVX512VBMI2 : 0x00000007, 0x00000000, ECX, 6
Use the documented byte granularity for cache-line accesses. Fixed CET CPUID feature flag - split into CET_SS and CET_IBT.
2020-07-21 21:47:46 +00:00
CET_SS : 0x00000007, 0x00000000, ECX, 7
Initial commit.
2020-07-21 08:19:18 +00:00
GFNI : 0x00000007, 0x00000000, ECX, 8
VAES : 0x00000007, 0x00000000, ECX, 9
VPCLMULQDQ : 0x00000007, 0x00000000, ECX, 10
AVX512VNNI : 0x00000007, 0x00000000, ECX, 11
AVX512BITALG : 0x00000007, 0x00000000, ECX, 12
AVX512VPOPCNTDQ : 0x00000007, 0x00000000, ECX, 14
RDPID : 0x00000007, 0x00000000, ECX, 22
Added support for Intel Key Locker instructions, as per https://software.intel.com/content/www/us/en/develop/download/intel-key-locker-specification.html.
2020-09-16 08:56:05 +00:00
KL : 0x00000007, 0x00000000, ECX, 23
Initial commit.
2020-07-21 08:19:18 +00:00
CLDEMOTE : 0x00000007, 0x00000000, ECX, 25
MOVDIRI : 0x00000007, 0x00000000, ECX, 27
MOVDIR64B : 0x00000007, 0x00000000, ECX, 28
ENQCMD : 0x00000007, 0x00000000, ECX, 29
AVX5124VNNIW : 0x00000007, 0x00000000, EDX, 2
AVX5124FMAPS : 0x00000007, 0x00000000, EDX, 3
Added support for UINTR, HRESET and AVX-VNNI instructions, as per Intel® Architecture Instruction Set Extensions Programming Reference 41 (October 2020).
2020-10-05 10:19:03 +00:00
UINTR : 0x00000007, 0x00000000, EDX, 5
Initial commit.
2020-07-21 08:19:18 +00:00
AVX512VP2INTERSECT : 0x00000007, 0x00000000, EDX, 8
SERIALIZE : 0x00000007, 0x00000000, EDX, 14
TSXLDTRK : 0x00000007, 0x00000000, EDX, 16
PCONFIG : 0x00000007, 0x00000000, EDX, 18
Use the documented byte granularity for cache-line accesses. Fixed CET CPUID feature flag - split into CET_SS and CET_IBT.
2020-07-21 21:47:46 +00:00
CET_IBT : 0x00000007, 0x00000000, EDX, 20
Initial commit.
2020-07-21 08:19:18 +00:00
AMXBF16 : 0x00000007, 0x00000000, EDX, 22
Added support for UINTR, HRESET and AVX-VNNI instructions, as per Intel® Architecture Instruction Set Extensions Programming Reference 41 (October 2020).
2020-10-05 10:19:03 +00:00
AVX512FP16 : 0x00000007, 0x00000000, EDX, 23
Initial commit.
2020-07-21 08:19:18 +00:00
AMXTILE : 0x00000007, 0x00000000, EDX, 24
AMXINT8 : 0x00000007, 0x00000000, EDX, 25
Added support for new Intel instructions, per Intel ISA extensions document #319433-046 (September 2022): PREFETCHITI, RAO-INT, CMPCCXADD, WRMSRNS, MSRLIST, AMX-FP16, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8. Multiple minor fixes to existing instructions. Moved x86 decoding tests in a separate directory & improved the test script.
2022-10-04 09:22:59 +00:00
Added support for new Intel ISA, per Intel® Architecture Instruction Set Extensions and Future Features document #319433-049 (June 2023): AVX-NNI-INT16, SHA512, SM3, SM4, TSE.
2023-07-21 06:38:49 +00:00
SHA512 : 0x00000007, 0x00000001, EAX, 0
SM3 : 0x00000007, 0x00000001, EAX, 1
SM4 : 0x00000007, 0x00000001, EAX, 2
Added support for new Intel instructions, per Intel ISA extensions document #319433-046 (September 2022): PREFETCHITI, RAO-INT, CMPCCXADD, WRMSRNS, MSRLIST, AMX-FP16, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8. Multiple minor fixes to existing instructions. Moved x86 decoding tests in a separate directory & improved the test script.
2022-10-04 09:22:59 +00:00
RAOINT : 0x00000007, 0x00000001, EAX, 3
Added support for UINTR, HRESET and AVX-VNNI instructions, as per Intel® Architecture Instruction Set Extensions Programming Reference 41 (October 2020).
2020-10-05 10:19:03 +00:00
AVXVNNI : 0x00000007, 0x00000001, EAX, 4
Initial commit.
2020-07-21 08:19:18 +00:00
AVX512BF16 : 0x00000007, 0x00000001, EAX, 5
Added support for new Intel instructions, per Intel ISA extensions document #319433-046 (September 2022): PREFETCHITI, RAO-INT, CMPCCXADD, WRMSRNS, MSRLIST, AMX-FP16, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8. Multiple minor fixes to existing instructions. Moved x86 decoding tests in a separate directory & improved the test script.
2022-10-04 09:22:59 +00:00
CMPCCXADD : 0x00000007, 0x00000001, EAX, 7
Added support for Intel FRED and LKGS instructions.
2021-03-15 12:05:44 +00:00
FRED : 0x00000007, 0x00000001, EAX, 17
LKGS : 0x00000007, 0x00000001, EAX, 18
Added support for new Intel instructions, per Intel ISA extensions document #319433-046 (September 2022): PREFETCHITI, RAO-INT, CMPCCXADD, WRMSRNS, MSRLIST, AMX-FP16, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8. Multiple minor fixes to existing instructions. Moved x86 decoding tests in a separate directory & improved the test script.
2022-10-04 09:22:59 +00:00
WRMSRNS : 0x00000007, 0x00000001, EAX, 19
AMXFP16 : 0x00000007, 0x00000001, EAX, 21
Added support for UINTR, HRESET and AVX-VNNI instructions, as per Intel® Architecture Instruction Set Extensions Programming Reference 41 (October 2020).
2020-10-05 10:19:03 +00:00
HRESET : 0x00000007, 0x00000001, EAX, 22
Added support for new Intel instructions, per Intel ISA extensions document #319433-046 (September 2022): PREFETCHITI, RAO-INT, CMPCCXADD, WRMSRNS, MSRLIST, AMX-FP16, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8. Multiple minor fixes to existing instructions. Moved x86 decoding tests in a separate directory & improved the test script.
2022-10-04 09:22:59 +00:00
AVXIFMA : 0x00000007, 0x00000001, EAX, 23
MSRLIST : 0x00000007, 0x00000001, EAX, 27
Added support for new Intel ISA, per Intel® Architecture Instruction Set Extensions and Future Features document #319433-049 (June 2023): AVX-NNI-INT16, SHA512, SM3, SM4, TSE.
2023-07-21 06:38:49 +00:00
TSE : 0x00000007, 0x00000001, EBX, 1
Added support for new Intel instructions, per Intel ISA extensions document #319433-046 (September 2022): PREFETCHITI, RAO-INT, CMPCCXADD, WRMSRNS, MSRLIST, AMX-FP16, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8. Multiple minor fixes to existing instructions. Moved x86 decoding tests in a separate directory & improved the test script.
2022-10-04 09:22:59 +00:00
AVXVNNIINT8 : 0x00000007, 0x00000001, EDX, 4
AVXNECONVERT : 0x00000007, 0x00000001, EDX, 5
Added support for Intel AMX-COMPLEX instructions.
2023-04-05 06:45:07 +00:00
AMXCOMPLEX : 0x00000007, 0x00000001, EDX, 8
Added support for new Intel ISA, per Intel® Architecture Instruction Set Extensions and Future Features document #319433-049 (June 2023): AVX-NNI-INT16, SHA512, SM3, SM4, TSE.
2023-07-21 06:38:49 +00:00
AVXVNNIINT16 : 0x00000007, 0x00000001, EDX, 10
Added support for new Intel instructions, per Intel ISA extensions document #319433-046 (September 2022): PREFETCHITI, RAO-INT, CMPCCXADD, WRMSRNS, MSRLIST, AMX-FP16, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8. Multiple minor fixes to existing instructions. Moved x86 decoding tests in a separate directory & improved the test script.
2022-10-04 09:22:59 +00:00
PREFETCHITI : 0x00000007, 0x00000001, EDX, 14
BDDISASM v2.1.0 release - please consult the CHANGELOG for details about the modifications.
2024-02-20 11:39:22 +00:00
USER_MSR : 0x00000007, 0x00000001, EDX, 15
APX_F : 0x00000007, 0x00000001, EDX, 21
Added support for new Intel instructions, per Intel ISA extensions document #319433-046 (September 2022): PREFETCHITI, RAO-INT, CMPCCXADD, WRMSRNS, MSRLIST, AMX-FP16, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8. Multiple minor fixes to existing instructions. Moved x86 decoding tests in a separate directory & improved the test script.
2022-10-04 09:22:59 +00:00
Initial commit.
2020-07-21 08:19:18 +00:00
XSAVEOPT : 0x0000000D, 0x00000001, EAX, 0
XSAVEC : 0x0000000D, 0x00000001, EAX, 1
XSAVES : 0x0000000D, 0x00000001, EAX, 3
Added support for new Intel instructions, per Intel ISA extensions document #319433-046 (September 2022): PREFETCHITI, RAO-INT, CMPCCXADD, WRMSRNS, MSRLIST, AMX-FP16, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8. Multiple minor fixes to existing instructions. Moved x86 decoding tests in a separate directory & improved the test script.
2022-10-04 09:22:59 +00:00
Initial commit.
2020-07-21 08:19:18 +00:00
PTWRITE : 0x00000014, 0x00000000, EBX, 4
Added support for new Intel instructions, per Intel ISA extensions document #319433-046 (September 2022): PREFETCHITI, RAO-INT, CMPCCXADD, WRMSRNS, MSRLIST, AMX-FP16, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8. Multiple minor fixes to existing instructions. Moved x86 decoding tests in a separate directory & improved the test script.
2022-10-04 09:22:59 +00:00
Initial commit.
2020-07-21 08:19:18 +00:00
SVM : 0x80000001, 0xFFFFFFFF, ECX, 2
LZCNT : 0x80000001, 0xFFFFFFFF, ECX, 5
SSE4A : 0x80000001, 0xFFFFFFFF, ECX, 6
PREFETCHW : 0x80000001, 0xFFFFFFFF, ECX, 8
FSC : 0x80000001, 0xFFFFFFFF, ECX, 11
XOP : 0x80000001, 0xFFFFFFFF, ECX, 11
LWP : 0x80000001, 0xFFFFFFFF, ECX, 15
FMA4 : 0x80000001, 0xFFFFFFFF, ECX, 16
TBM : 0x80000001, 0xFFFFFFFF, ECX, 21
INVLPGB : 0x80000001, 0xFFFFFFFF, EDX, 24
RDTSCP : 0x80000001, 0xFFFFFFFF, ECX, 27
3DNOW : 0x80000001, 0xFFFFFFFF, EDX, 31
Added support for new Intel instructions, per Intel ISA extensions document #319433-046 (September 2022): PREFETCHITI, RAO-INT, CMPCCXADD, WRMSRNS, MSRLIST, AMX-FP16, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8. Multiple minor fixes to existing instructions. Moved x86 decoding tests in a separate directory & improved the test script.
2022-10-04 09:22:59 +00:00
Initial commit.
2020-07-21 08:19:18 +00:00
WBNOINVD : 0x80000008, 0xFFFFFFFF, EBX, 9
RDPRU : 0x80000008, 0xFFFFFFFF, EBX, 4
MCOMMIT : 0x80000008, 0xFFFFFFFF, EBX, 8
Added support for new Intel instructions, per Intel ISA extensions document #319433-046 (September 2022): PREFETCHITI, RAO-INT, CMPCCXADD, WRMSRNS, MSRLIST, AMX-FP16, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8. Multiple minor fixes to existing instructions. Moved x86 decoding tests in a separate directory & improved the test script.
2022-10-04 09:22:59 +00:00
Initial commit.
2020-07-21 08:19:18 +00:00
SNP : 0x8000001F, 0xFFFFFFFF, EAX, 4
Added support for AMD RMPQUERY instruction.
2022-10-27 09:37:02 +00:00
RMPQUERY : 0x8000001F, 0xFFFFFFFF, EAX, 6
Added support for new Intel AVX 10.2 instructions. Added support for AMD RMPREAD instruction. Improved EVEX decoding, including the new U bit. Fixed ENTER & LEAVE operands.
2024-09-16 09:23:54 +00:00
RMPREAD : 0x8000001F, 0xFFFFFFFF, EAX, 21
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