Commit Graph

25 Commits (ee6cdd6cb6eacf49e68ea3516f8502dceb2f8e40)

Author SHA1 Message Date
BITDEFENDER\vlutas ee6cdd6cb6 Switched to a more parsing-friendly format for the instructions database, where individual components are sepparated by a semicolon.
1 year ago
BITDEFENDER\vlutas 24665b0531 Switched from nil to n/a naming for absent operands, as it is more obvious.
1 year ago
BITDEFENDER\vlutas 7a254037b0 Added support for AMD RMPQUERY instruction.
2 years ago
BITDEFENDER\vlutas 9ba1e6a2f9 Added support for new Intel instructions, per Intel ISA extensions document #319433-046 (September 2022): PREFETCHITI, RAO-INT, CMPCCXADD, WRMSRNS, MSRLIST, AMX-FP16, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8.
2 years ago
BITDEFENDER\vlutas 433e723e07 Implemented a reverse oprand lookup table. It holds pointers to relevant operands inside INSTRUX, for quick lookup.
3 years ago
Andrei Vlad LUTAS 08096172cc Multiple improvements
3 years ago
Andrei Vlad LUTAS c3a6ea1c25 Updated SEAMCALL specs according to Intel® Trust Domain CPU Architectural Extensions 343754-002US May 2021.
3 years ago
Andrei Vlad LUTAS d053de409f Although not stated in the SDM, VMCALL, VMLAUNCH, VMRESUME and VMXOFF refuse any prefix (66, F3, F2).
3 years ago
Andrei Vlad LUTAS f7bf814bbc Flag the rIP operand of conditional branches as being conditionally read/write instead of plain read/write.
3 years ago
Andrei Vlad LUTAS fccf11915d Added support for Intel FRED and LKGS instructions.
3 years ago
Andrei Vlad LUTAS 1eb1c9d0d2 Fixed https://github.com/bitdefender/bddisasm/issues/38.
3 years ago
Andrei Vlad LUTAS 58197cc518 Removed support for PCOMMIT and CL1INVMB (not implemented by any x86/x64 CPUs), and marked MOV to/from test registers as being invalid in long mode.
4 years ago
Andrei Vlad LUTAS bcf9a89d69 Fixed https://github.com/bitdefender/bddisasm/issues/22 and https://github.com/bitdefender/bddisasm/issues/23.
4 years ago
Andrei Vlad LUTAS 9652450125 Added support for UINTR, HRESET and AVX-VNNI instructions, as per Intel® Architecture Instruction Set Extensions Programming Reference 41 (October 2020).
4 years ago
Andrei Vlad LUTAS 33078e4670 Added support for TDX instructions, per https://software.intel.com/content/dam/develop/external/us/en/documents/intel-tdx-cpu-architectural-specification.pdf.
4 years ago
Andrei Vlad LUTAS ed564dba32 Specifically flag multi-byte NOP operands as not-accessed.
4 years ago
Andrei Vlad LUTAS d622f56211 Added SERIAL flag to the SERIALIZE instruction.
4 years ago
Andrei Vlad LUTAS 4b2f2aee66 Added dedicated Prefetch operand access type.
4 years ago
Andrei Vlad LUTAS 752bc626c4 Fixed RET with immediate - the immediate is not sign-extended.
4 years ago
Andrei Vlad LUTAS 94d7894fa5 Added the Shadow Stack Pointer operand to the SYSRET and SYSENTER instructions.
4 years ago
Andrei Vlad LUTAS 8392c97f97 Use the documented byte granularity for cache-line accesses.
4 years ago
Andrei Vlad LUTAS 9ff2543660 Added the Shadow Stack Pointer operand to the SYSCALL and SYSEXIT instructions.
4 years ago
Andrei Vlad LUTAS 811c3d0f7c Fixed several issues with CET instructions specification - shadow stack and shadow stack pointer implicit operands were missing from SETSSBSY instruction, and flags access was missing from them.
4 years ago
Andrei Vlad LUTAS efe359b506 Typo fixes in the instruction tables.
4 years ago
Andrei Vlad LUTAS 698ba367a1 Initial commit.
4 years ago