Commit Graph

10 Commits (7a0fa449bc49e3f706bc4b7da4c724ea22d5fc12)

Author SHA1 Message Date
Andrei Vlad LUTAS 7a0fa449bc Disassemble 4X90 as NOP as long as Rex.B is 0. Disassemble as XCHG only if Rex.B bit is set (promoting the use of R8 register).
4 years ago
Andrei Vlad LUTAS 9652450125 Added support for UINTR, HRESET and AVX-VNNI instructions, as per Intel® Architecture Instruction Set Extensions Programming Reference 41 (October 2020).
4 years ago
Andrei Vlad LUTAS 4f8b030ddd Added support for Intel Key Locker instructions, as per https://software.intel.com/content/www/us/en/develop/download/intel-key-locker-specification.html.
4 years ago
Andrei Vlad LUTAS 33078e4670 Added support for TDX instructions, per https://software.intel.com/content/dam/develop/external/us/en/documents/intel-tdx-cpu-architectural-specification.pdf.
4 years ago
Andrei Vlad LUTAS ed564dba32 Specifically flag multi-byte NOP operands as not-accessed.
4 years ago
Andrei Vlad LUTAS 4b2f2aee66 Added dedicated Prefetch operand access type.
4 years ago
Andrei Vlad LUTAS 752bc626c4 Fixed RET with immediate - the immediate is not sign-extended.
4 years ago
Andrei Vlad LUTAS 9ff2543660 Added the Shadow Stack Pointer operand to the SYSCALL and SYSEXIT instructions.
4 years ago
Andrei Vlad LUTAS 811c3d0f7c Fixed several issues with CET instructions specification - shadow stack and shadow stack pointer implicit operands were missing from SETSSBSY instruction, and flags access was missing from them.
4 years ago
Andrei Vlad LUTAS 698ba367a1 Initial commit.
4 years ago