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Disassemble 4X90 as NOP as long as Rex.B is 0. Disassemble as XCHG only if Rex.B bit is set (promoting the use of R8 register).

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This commit is contained in:
Andrei Vlad LUTAS 2020-10-09 14:55:39 +03:00
parent 9652450125
commit 7a0fa449bc
7 changed files with 13 additions and 13 deletions
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4
bddisasm/bddisasm.c
View File

@ -3398,9 +3398,9 @@ NdFindInstruction(
case ND_ILUT_AUXILIARY:
// Auxiliary redirection. Default to table[0] if nothing matches.
if (Instrux->HasRex && (NULL != pTable->Table[ND_ILUT_INDEX_AUX_REX]))
if (Instrux->HasRex && Instrux->Rex.b && (NULL != pTable->Table[ND_ILUT_INDEX_AUX_REXB]))
{
nextIndex = ND_ILUT_INDEX_AUX_REX;
nextIndex = ND_ILUT_INDEX_AUX_REXB;
}
else if (Instrux->HasRex && Instrux->Rex.w && (NULL != pTable->Table[ND_ILUT_INDEX_AUX_REXW]))
{

2
bddisasm/include/instructions.h
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@ -42820,7 +42820,7 @@ const ND_INSTRUCTION gInstructions[2586] =
},
},
// Pos:2539 Instruction:"XCHG rAX,Zv" Encoding:"rex 0x90"/"O"
// Pos:2539 Instruction:"XCHG rAX,Zv" Encoding:"rexb 0x90"/"O"
{
ND_INS_XCHG, ND_CAT_DATAXFER, ND_SET_I86, 1557,
0,

4
bddisasm/include/table_root.h
View File

@ -14536,7 +14536,7 @@ const ND_TABLE_INSTRUCTION gRootTable_root_90_aF3_leaf =
(const void *)&gInstructions[848]
};
const ND_TABLE_INSTRUCTION gRootTable_root_90_rex_leaf =
const ND_TABLE_INSTRUCTION gRootTable_root_90_rexb_leaf =
{
ND_ILUT_INSTRUCTION,
(const void *)&gInstructions[2539]
@ -14547,7 +14547,7 @@ const ND_TABLE_AUXILIARY gRootTable_root_90_auxiliary =
ND_ILUT_AUXILIARY,
{
/* 00 */ (const void *)&gRootTable_root_90_None_leaf,
/* 01 */ (const void *)&gRootTable_root_90_rex_leaf,
/* 01 */ (const void *)&gRootTable_root_90_rexb_leaf,
/* 02 */ NULL,
/* 03 */ NULL,
/* 04 */ (const void *)&gRootTable_root_90_aF3_leaf,

2
bddisasm/include/tabledefs.h
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@ -62,7 +62,7 @@ typedef enum _ND_ILUT_TYPE
#define ND_ILUT_INDEX_ASIZE_64 3
#define ND_ILUT_INDEX_AUX_NONE 0
#define ND_ILUT_INDEX_AUX_REX 1
#define ND_ILUT_INDEX_AUX_REXB 1
#define ND_ILUT_INDEX_AUX_REXW 2
#define ND_ILUT_INDEX_AUX_O64 3
#define ND_ILUT_INDEX_AUX_F3 4

10
isagenerator/disasmlib.py
View File

@ -663,7 +663,7 @@ class Instruction():
# Sixth redirection class: default address size
self.RedAs16 = self.RedAs32 = self.RedAs64 = False
# Seventh redirecton class: rex, rex.w, rep, repz
self.RedRex = self.RedRexW = self.RedRep = self.Red64 = self.RedF3 = False
self.RedRexB = self.RedRexW = self.RedRep = self.Red64 = self.RedF3 = False
# Misc - vendor
self.Vendor = None
# Misc - feature.
@ -693,8 +693,8 @@ class Instruction():
self.Red64 = True
elif 'rexw' == t:
self.RedRexW = True
elif 'rex' == t:
self.RedRex = True
elif 'rexb' == t:
self.RedRexB = True
elif 'rep' == t:
self.RedRep = True
elif 'ds16' == t:
@ -1003,8 +1003,8 @@ class Instruction():
# the other classes, this is not exhaustive - if an instruction does not fit in any of the entries, it
# will default to index 0 (and it will not return invalid encoding, unless entry 0 is invalid).
oprefixes = []
if self.RedRex:
oprefixes.append('rex')
if self.RedRexB:
oprefixes.append('rexb')
if self.RedRexW:
oprefixes.append('rexw')
if self.Red64:

2
isagenerator/generate_tables.py
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@ -380,7 +380,7 @@ indexes = {
"F2" : 3,
# other prefixes
"rex" : 1,
"rexb" : 1,
"rexw" : 2,
"64" : 3,
"aF3" : 4,

2
isagenerator/instructions/table_base.dat
View File

@ -212,7 +212,7 @@ POP Ev Kv [ 0x8F /0] s:I86
# 0x90 - 0x9F
NOP nil nil [ 0x90] s:I86, t:NOP,
PAUSE nil nil [ a0xF3 0x90] s:PAUSE, t:MISC, m:NOTSX
XCHG rAX,Zv nil [ rex 0x90] s:I86, t:DATAXFER, w:RW|RW
XCHG rAX,Zv nil [ rexb 0x90] s:I86, t:DATAXFER, w:RW|RW
XCHG rAX,Zv nil [ 0x91] s:I86, t:DATAXFER, w:RW|RW
XCHG rAX,Zv nil [ 0x92] s:I86, t:DATAXFER, w:RW|RW
XCHG rAX,Zv nil [ 0x93] s:I86, t:DATAXFER, w:RW|RW