arno/bddisasm
1
0
Fork 0
mirror of https://github.com/bitdefender/bddisasm.git synced 2024-12-22 22:18:09 +00:00
Code Issues Releases Wiki Activity
314 Commits 3 Branches 16 Tags 8.6 MiB
3b620c2dba
Commit Graph

41 Commits

Author SHA1 Message Date
Andrei Vlad LUTAS
91f04ed43b Fixed potential unaligned load, as reported by UBSAN. 2024-05-28 19:20:38 +03:00
Andrei Vlad LUTAS
44dc7c6cbb Updated changelog & Python binding version. 2024-03-27 09:21:00 +02:00
Andrei Vlad LUTAS
37a8c94bc7 Applied some of the syntax recomandations from https://cdrdv2.intel.com/v1/dl/getContent/817241. 2024-03-04 12:48:18 +02:00
Andrei Vlad LUTAS
02cbe6a298 https://github.com/bitdefender/bddisasm/issues/87 - added missing R access for the rIP operand for SYSCALL instructions; added missing SCS, rCX and rDX operands for SYSEXIT instruction. 2024-02-27 09:45:05 +02:00
Andrei Vlad LUTAS
f6f93c4112 Fixed pybddisasm version. 2024-02-26 21:03:14 +02:00
Anichitei Ionel-Cristinel
00a9640b73
rsbddisasm: Update bddisasm-sys dependency version 2024-02-21 08:04:25 +02:00
Anichitei Ionel-Cristinel
abc9657c78
rsbddisasm: Bump version in install instructions 2024-02-21 08:02:20 +02:00
Anichitei Ionel-Cristinel
b5ac0a30b9
Update Cargo.toml 2024-02-21 08:00:40 +02:00
Anichitei Ionel-Cristinel
ba14104087
rsbddisasm: Update bindgen to 0.62.0 
See https://github.com/rust-lang/rust-bindgen/issues/2312
 2024-02-20 14:46:59 +02:00
Andrei KISARI
698686ab14 Update headers for pybddisasm. 2024-02-20 14:35:21 +02:00
Andrei Vlad LUTAS
fad9c7e35c BDDISASM v2.1.0 release - please consult the CHANGELOG for details about the modifications. 2024-02-20 13:39:22 +02:00
Ionel-Cristinel ANICHITEI
727c87ecc4 rsbddisasm: Update bindings 2023-07-21 10:14:31 +03:00
Andrei Vlad LUTAS
f53cbc51e2 Added support for new Intel ISA, per Intel® Architecture Instruction Set Extensions and Future Features document #319433-049 (June 2023): AVX-NNI-INT16, SHA512, SM3, SM4, TSE. 2023-07-21 09:38:49 +03:00
Ionel-Cristinel ANICHITEI
be0969824c rsbddisasm: Update CHANGELOG 2023-07-01 10:50:49 +03:00
Ionel-Cristinel ANICHITEI
fbb38f1518 #82: Handle 0 in OpSize::from_raw 2023-07-01 10:44:37 +03:00
Andrei KISARI
1384893052 Update copyright. 2023-06-26 10:40:30 +03:00
Andrei KISARI
455286ca13 Fix build. 2023-06-22 15:14:05 +03:00
Andrei KISARI
4f182b2c11 Use SWIG to create bindings between C and Python. 2023-06-22 14:54:41 +03:00
Ionel-Cristinel ANICHITEI
3beaac8ae2 Update bindings 2023-04-05 10:02:41 +03:00
BITDEFENDER\vlutas
124521beb5 Added support for Intel AMX-COMPLEX instructions. 2023-04-05 09:45:07 +03:00
Ionel-Cristinel ANICHITEI
00c9ebc341 rsbddisasm: Add RMPQUERY 2022-10-27 12:57:13 +03:00
BITDEFENDER\vlutas
7a254037b0 Added support for AMD RMPQUERY instruction. 2022-10-27 12:37:02 +03:00
Ionel-Cristinel ANICHITEI
22d7c14c51 rsbddisasm: Update bindings 2022-10-04 13:17:54 +03:00
BITDEFENDER\vlutas
9ba1e6a2f9 Added support for new Intel instructions, per Intel ISA extensions document #319433-046 (September 2022): PREFETCHITI, RAO-INT, CMPCCXADD, WRMSRNS, MSRLIST, AMX-FP16, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8. 
Multiple minor fixes to existing instructions.
Moved x86 decoding tests in a separate directory & improved the test script.
 2022-10-04 12:22:59 +03:00
BITDEFENDER\vlutas
9c6b5429c9 Fixed pybddisasm version. 2022-08-01 14:17:07 +03:00
BITDEFENDER\vlutas
bf81c647e3 Make sure all flags are set for CMPXCHG (this was left intentionally incomplete). 
Make sure we clear upper bits of the 256/512 bit SSE register.
 2022-07-19 11:03:17 +03:00
BITDEFENDER\vlutas
6dda2c122c Make sure upper 32 bit of a CMOV destination register is cleared to 0 even if the condition is not satisfied 2022-07-16 12:21:46 +03:00
BITDEFENDER\vlutas
1805a9edec Fixed flag setting for ADC, SBB, SAR and IMUL instructions. 2022-07-14 13:42:37 +03:00
Ionel-Cristinel ANICHITEI
73b7c4ea96 rsbddisasm: Fix no-std category 2022-01-05 14:40:26 +02:00
Ionel-Cristinel ANICHITEI
21c584b436 rsbddisasm: Change version to 0.2.0 2022-01-05 14:31:30 +02:00
BITDEFENDER\vlutas
70db095765 Updates Rust binding to the latest version. 
Fixed build in disasmtool_lix.
 2022-01-05 14:17:13 +02:00
BITDEFENDER\vlutas
fe6a937f51 Switched to internally defined types. 
WRUSSD and WRUSSQ cannot be executed when CPL != 0.
 2022-01-05 14:03:13 +02:00
BITDEFENDER\vlutas
63e3ee22a9 Fixed High8 handling in NdGetFullAccessMap. 2022-01-03 12:25:35 +02:00
BITDEFENDER\vlutas
2f50ce9b4e Improved REG_ID macros - make sure we include block addressing and High8 designator in the reg ID. Alsom, make sure the register size fits in, since the new tile register can be 1K in size, which previously overflowed... 2021-12-03 12:44:57 +02:00
Anichitei Ionel-Cristinel
dac2092c17
Rust bindings: Remove ND_CAT_FRED 2021-11-02 11:39:41 +02:00
BITDEFENDER\vlutas
7572adaeba Fixed INSTRUX size in setup.py. 2021-11-02 11:34:17 +02:00
BITDEFENDER\vlutas
433e723e07 Implemented a reverse oprand lookup table. It holds pointers to relevant operands inside INSTRUX, for quick lookup. 
Moved helper functions in bdhelpers.c.
Added a dedicated BranchInfo field inside INSTRUX, containing the most relevant branch information.
 2021-11-02 11:22:22 +02:00
Ionel-Cristinel ANICHITEI
def76f8633 rsbddisasm: Fix keywords 2021-10-20 12:24:11 +03:00
Ionel-Cristinel ANICHITEI
1e78d15878 bddisasm-sys: Fix keywords 2021-10-20 12:12:02 +03:00
Ionel-Cristinel ANICHITEI
584150cb44 Move rsbddisasm to the bindings directory 2021-10-20 10:03:16 +03:00
Ionel-Cristinel ANICHITEI
af3d23e3ff Move pybddisasm to the bindings directory 2021-10-20 09:32:50 +03:00