Andrei Vlad LUTAS
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37a8c94bc7
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Applied some of the syntax recomandations from https://cdrdv2.intel.com/v1/dl/getContent/817241.
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2024-03-04 12:48:18 +02:00 |
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Andrei Vlad LUTAS
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02cbe6a298
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https://github.com/bitdefender/bddisasm/issues/87 - added missing R access for the rIP operand for SYSCALL instructions; added missing SCS, rCX and rDX operands for SYSEXIT instruction.
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2024-02-27 09:45:05 +02:00 |
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Andrei Vlad LUTAS
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f6f93c4112
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Fixed pybddisasm version.
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2024-02-26 21:03:14 +02:00 |
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Andrei KISARI
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698686ab14
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Update headers for pybddisasm.
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2024-02-20 14:35:21 +02:00 |
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Andrei Vlad LUTAS
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fad9c7e35c
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BDDISASM v2.1.0 release - please consult the CHANGELOG for details about the modifications.
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2024-02-20 13:39:22 +02:00 |
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Andrei Vlad LUTAS
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f53cbc51e2
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Added support for new Intel ISA, per Intel® Architecture Instruction Set Extensions and Future Features document #319433-049 (June 2023): AVX-NNI-INT16, SHA512, SM3, SM4, TSE.
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2023-07-21 09:38:49 +03:00 |
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Andrei KISARI
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1384893052
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Update copyright.
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2023-06-26 10:40:30 +03:00 |
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Andrei KISARI
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455286ca13
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Fix build.
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2023-06-22 15:14:05 +03:00 |
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Andrei KISARI
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4f182b2c11
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Use SWIG to create bindings between C and Python.
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2023-06-22 14:54:41 +03:00 |
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BITDEFENDER\vlutas
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124521beb5
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Added support for Intel AMX-COMPLEX instructions.
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2023-04-05 09:45:07 +03:00 |
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BITDEFENDER\vlutas
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7a254037b0
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Added support for AMD RMPQUERY instruction.
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2022-10-27 12:37:02 +03:00 |
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BITDEFENDER\vlutas
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9ba1e6a2f9
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Added support for new Intel instructions, per Intel ISA extensions document #319433-046 (September 2022): PREFETCHITI, RAO-INT, CMPCCXADD, WRMSRNS, MSRLIST, AMX-FP16, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8.
Multiple minor fixes to existing instructions.
Moved x86 decoding tests in a separate directory & improved the test script.
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2022-10-04 12:22:59 +03:00 |
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BITDEFENDER\vlutas
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9c6b5429c9
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Fixed pybddisasm version.
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2022-08-01 14:17:07 +03:00 |
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BITDEFENDER\vlutas
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bf81c647e3
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Make sure all flags are set for CMPXCHG (this was left intentionally incomplete).
Make sure we clear upper bits of the 256/512 bit SSE register.
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2022-07-19 11:03:17 +03:00 |
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BITDEFENDER\vlutas
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6dda2c122c
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Make sure upper 32 bit of a CMOV destination register is cleared to 0 even if the condition is not satisfied
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2022-07-16 12:21:46 +03:00 |
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BITDEFENDER\vlutas
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1805a9edec
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Fixed flag setting for ADC, SBB, SAR and IMUL instructions.
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2022-07-14 13:42:37 +03:00 |
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BITDEFENDER\vlutas
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fe6a937f51
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Switched to internally defined types.
WRUSSD and WRUSSQ cannot be executed when CPL != 0.
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2022-01-05 14:03:13 +02:00 |
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BITDEFENDER\vlutas
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63e3ee22a9
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Fixed High8 handling in NdGetFullAccessMap.
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2022-01-03 12:25:35 +02:00 |
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BITDEFENDER\vlutas
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2f50ce9b4e
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Improved REG_ID macros - make sure we include block addressing and High8 designator in the reg ID. Alsom, make sure the register size fits in, since the new tile register can be 1K in size, which previously overflowed...
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2021-12-03 12:44:57 +02:00 |
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BITDEFENDER\vlutas
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7572adaeba
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Fixed INSTRUX size in setup.py.
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2021-11-02 11:34:17 +02:00 |
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BITDEFENDER\vlutas
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433e723e07
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Implemented a reverse oprand lookup table. It holds pointers to relevant operands inside INSTRUX, for quick lookup.
Moved helper functions in bdhelpers.c.
Added a dedicated BranchInfo field inside INSTRUX, containing the most relevant branch information.
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2021-11-02 11:22:22 +02:00 |
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Ionel-Cristinel ANICHITEI
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af3d23e3ff
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Move pybddisasm to the bindings directory
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2021-10-20 09:32:50 +03:00 |
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