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Author SHA1 Message Date
vlutas
2b12d0ab4b
Merge pull request #86 from oberrich/patch-1 
Fix typo in bdshemu.c
 2024-02-26 10:52:33 +02:00
oberrich
f7410a083a
Fix typo in bdshemu.c 2024-02-26 05:13:24 +01:00
vlutas
8f95a2828d
Merge pull request #85 from ianichitei/master 
Various build improvements
 2024-02-23 15:44:04 +02:00
Anichitei Ionel-Cristinel
aeeafc414a
build: Fix ci.yml 2024-02-23 12:22:18 +02:00
Anichitei Ionel-Cristinel
afc3e94801
build: Try to build on macos 2024-02-23 12:21:11 +02:00
Anichitei Ionel-Cristinel
357b95d652
build: Remove rapidjson dependency 2024-02-23 12:16:08 +02:00
Anichitei Ionel-Cristinel
3beab3a3ee
build: Use -march=native 2024-02-23 11:44:03 +02:00
Andrei Vlad LUTAS
40d53c6433 Removed unused declaration. 2024-02-22 15:03:19 +02:00
Anichitei Ionel-Cristinel
00a9640b73
rsbddisasm: Update bddisasm-sys dependency version 2024-02-21 08:04:25 +02:00
Anichitei Ionel-Cristinel
abc9657c78
rsbddisasm: Bump version in install instructions 2024-02-21 08:02:20 +02:00
Anichitei Ionel-Cristinel
b5ac0a30b9
Update Cargo.toml 2024-02-21 08:00:40 +02:00
Anichitei Ionel-Cristinel
ba14104087
rsbddisasm: Update bindgen to 0.62.0 
See https://github.com/rust-lang/rust-bindgen/issues/2312
 2024-02-20 14:46:59 +02:00
Andrei KISARI
698686ab14 Update headers for pybddisasm. 2024-02-20 14:35:21 +02:00
Anichitei Ionel-Cristinel
fbe5c1375d
Update ci.yml 2024-02-20 14:06:32 +02:00
Anichitei Ionel-Cristinel
570fa2bb62
ci: Suppress cppcheck objectIndex warning 2024-02-20 14:05:45 +02:00
Andrei Vlad LUTAS
fad9c7e35c BDDISASM v2.1.0 release - please consult the CHANGELOG for details about the modifications. 2024-02-20 13:39:22 +02:00
Ionel-Cristinel ANICHITEI
727c87ecc4 rsbddisasm: Update bindings 2023-07-21 10:14:31 +03:00
Andrei Vlad LUTAS
f53cbc51e2 Added support for new Intel ISA, per Intel® Architecture Instruction Set Extensions and Future Features document #319433-049 (June 2023): AVX-NNI-INT16, SHA512, SM3, SM4, TSE. 2023-07-21 09:38:49 +03:00
Ionel-Cristinel ANICHITEI
be0969824c rsbddisasm: Update CHANGELOG 2023-07-01 10:50:49 +03:00
Ionel-Cristinel ANICHITEI
fbb38f1518 #82: Handle 0 in OpSize::from_raw 2023-07-01 10:44:37 +03:00
Anichitei Ionel-Cristinel
935e2dfe5b
Merge pull request #81 from bitdefender/ci-updates 
CI actions updates
 2023-06-27 14:57:15 +03:00
Anichitei Ionel-Cristinel
b90ed49d33
ci: Update setup-msbuild to 1.3 2023-06-27 14:52:22 +03:00
Anichitei Ionel-Cristinel
b71ad7e6d9
ci: Update upload-release-assets to v2.0.2 2023-06-27 14:45:14 +03:00
Anichitei Ionel-Cristinel
aa362fa43e
ci: Update checkout to v3 2023-06-27 14:32:31 +03:00
Andrei KISARI
11e6a3e208
Merge pull request #80 from akisari/master 
Use SWIG to create bindings between C and Python.
 2023-06-26 11:42:01 +03:00
Andrei KISARI
1384893052 Update copyright. 2023-06-26 10:40:30 +03:00
Andrei KISARI
455286ca13 Fix build. 2023-06-22 15:14:05 +03:00
Andrei KISARI
4f182b2c11 Use SWIG to create bindings between C and Python. 2023-06-22 14:54:41 +03:00
BITDEFENDER\vlutas
096b583c25 Tiny comment fix. 2023-06-02 11:22:52 +03:00
BITDEFENDER\vlutas
f293c936ee Optimized ror/rol/rcr/rcl instruction emulation - don't use slow loops anymore. 2023-06-01 21:28:30 +03:00
Ionel-Cristinel ANICHITEI
d16f1d8ba3 bdshemu_fuzz: Update build scripts 2023-04-05 11:06:10 +03:00
Ionel-Cristinel ANICHITEI
3beaac8ae2 Update bindings 2023-04-05 10:02:41 +03:00
BITDEFENDER\vlutas
124521beb5 Added support for Intel AMX-COMPLEX instructions. 2023-04-05 09:45:07 +03:00
BITDEFENDER\vlutas
ee6cdd6cb6 Switched to a more parsing-friendly format for the instructions database, where individual components are sepparated by a semicolon. 2023-02-09 10:54:45 +02:00
BITDEFENDER\vlutas
24665b0531 Switched from nil to n/a naming for absent operands, as it is more obvious. 2023-02-08 17:44:45 +02:00
BITDEFENDER\vlutas
fc6059109d Improved comments & improved vector length specifiers. 2023-02-04 12:02:05 +02:00
BITDEFENDER\vlutas
0093439855 Added some comments. 2023-02-02 22:10:56 +02:00
BITDEFENDER\vlutas
089e6d5e7e Significant cleanup in disasmtool: the obsolete search functionality, and supplying registers for shemu from a file are no longer supported. 2023-02-02 21:46:24 +02:00
BITDEFENDER\vlutas
61382e95f0 Since all the shemu test file are synthetic and clean, I removed the password from the test archive. 2022-12-16 15:17:39 +02:00
Anichitei Ionel-Cristinel
102b43dd00
Merge pull request #78 from ianichitei/master 
Fix `clang-cl` and `mingw` builds
 2022-12-05 14:25:25 +01:00
Ionel-Cristinel ANICHITEI
31457a0c02 Fix clang-cl and mingw builds 2022-12-05 12:10:30 +02:00
Ionel-Cristinel ANICHITEI
e67584241b Revert "Fix clang-cl and mingw builds" 
This reverts commit add871993f.

I'll make a PR with these changes.
 2022-12-05 12:07:22 +02:00
Ionel-Cristinel ANICHITEI
add871993f Fix clang-cl and mingw builds 2022-12-05 12:05:15 +02:00
BITDEFENDER\vlutas
ab3461fd06 Regenerated test archive. 2022-12-05 11:25:39 +02:00
Ionel-Cristinel ANICHITEI
00c9ebc341 rsbddisasm: Add RMPQUERY 2022-10-27 12:57:13 +03:00
BITDEFENDER\vlutas
7a254037b0 Added support for AMD RMPQUERY instruction. 2022-10-27 12:37:02 +03:00
Ionel-Cristinel ANICHITEI
f75e1e28cd bdshemu_fuzz: Build with -maes 2022-10-04 13:31:02 +03:00
Ionel-Cristinel ANICHITEI
22d7c14c51 rsbddisasm: Update bindings 2022-10-04 13:17:54 +03:00
BITDEFENDER\vlutas
9ba1e6a2f9 Added support for new Intel instructions, per Intel ISA extensions document #319433-046 (September 2022): PREFETCHITI, RAO-INT, CMPCCXADD, WRMSRNS, MSRLIST, AMX-FP16, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8. 
Multiple minor fixes to existing instructions.
Moved x86 decoding tests in a separate directory & improved the test script.
 2022-10-04 12:22:59 +03:00
BITDEFENDER\vlutas
4596dbda51 Add copyright info when auto-generating files. 2022-09-10 23:15:00 +03:00