Andrei Vlad LUTAS
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37a8c94bc7
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Applied some of the syntax recomandations from https://cdrdv2.intel.com/v1/dl/getContent/817241.
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2024-03-04 12:48:18 +02:00 |
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Andrei Vlad LUTAS
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02cbe6a298
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https://github.com/bitdefender/bddisasm/issues/87 - added missing R access for the rIP operand for SYSCALL instructions; added missing SCS, rCX and rDX operands for SYSEXIT instruction.
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2024-02-27 09:45:05 +02:00 |
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Andrei Vlad LUTAS
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3df189f093
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https://github.com/bitdefender/bddisasm/issues/87 - Fixed CALL instruction access for rIP operand - it must include read access, as the instruction pointer is saved on the stack.
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2024-02-26 20:53:42 +02:00 |
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Andrei Vlad LUTAS
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fad9c7e35c
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BDDISASM v2.1.0 release - please consult the CHANGELOG for details about the modifications.
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2024-02-20 13:39:22 +02:00 |
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Andrei Vlad LUTAS
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f53cbc51e2
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Added support for new Intel ISA, per Intel® Architecture Instruction Set Extensions and Future Features document #319433-049 (June 2023): AVX-NNI-INT16, SHA512, SM3, SM4, TSE.
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2023-07-21 09:38:49 +03:00 |
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BITDEFENDER\vlutas
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124521beb5
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Added support for Intel AMX-COMPLEX instructions.
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2023-04-05 09:45:07 +03:00 |
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BITDEFENDER\vlutas
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7a254037b0
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Added support for AMD RMPQUERY instruction.
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2022-10-27 12:37:02 +03:00 |
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BITDEFENDER\vlutas
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9ba1e6a2f9
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Added support for new Intel instructions, per Intel ISA extensions document #319433-046 (September 2022): PREFETCHITI, RAO-INT, CMPCCXADD, WRMSRNS, MSRLIST, AMX-FP16, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8.
Multiple minor fixes to existing instructions.
Moved x86 decoding tests in a separate directory & improved the test script.
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2022-10-04 12:22:59 +03:00 |
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