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bddisasm/inc/bdx86_cpuidflags.h

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Add copyright info when auto-generating files.
2022-09-10 20:15:00 +00:00
/*
BDDISASM v2.1.0 release - please consult the CHANGELOG for details about the modifications.
2024-02-20 11:39:22 +00:00
* Copyright (c) 2024 Bitdefender
Add copyright info when auto-generating files.
2022-09-10 20:15:00 +00:00
* SPDX-License-Identifier: Apache-2.0
*/
Added support for new Intel instructions, per Intel ISA extensions document #319433-046 (September 2022): PREFETCHITI, RAO-INT, CMPCCXADD, WRMSRNS, MSRLIST, AMX-FP16, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8. Multiple minor fixes to existing instructions. Moved x86 decoding tests in a separate directory & improved the test script.
2022-10-04 09:22:59 +00:00
//
// This file was auto-generated by generate_tables.py. DO NOT MODIFY!
//
BDDISASM v2.1.0 release - please consult the CHANGELOG for details about the modifications.
2024-02-20 11:39:22 +00:00
#ifndef BDX86_CPUID_FLAGS_H
#define BDX86_CPUID_FLAGS_H
Initial commit.
2020-07-21 08:19:18 +00:00
#define ND_CFF_NO_LEAF 0xFFFFFFFF
#define ND_CFF_NO_SUBLEAF 0x00FFFFFF
Switched to internally defined types. WRUSSD and WRUSSQ cannot be executed when CPL != 0.
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#define ND_CFF(leaf, subleaf, reg, bit) ((ND_UINT64)(leaf) | ((ND_UINT64)((subleaf) & 0xFFFFFF) << 32) | ((ND_UINT64)(reg) << 56) | ((ND_UINT64)(bit) << 59))
Renamed REG_* fields to NDR_*, so that we don't conflict with _GNU_SOURCES.
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#define ND_CFF_FPU ND_CFF(0x00000001, 0xFFFFFFFF, NDR_EDX, 0)
#define ND_CFF_MSR ND_CFF(0x00000001, 0xFFFFFFFF, NDR_EDX, 5)
#define ND_CFF_CX8 ND_CFF(0x00000001, 0xFFFFFFFF, NDR_EDX, 8)
#define ND_CFF_SEP ND_CFF(0x00000001, 0xFFFFFFFF, NDR_EDX, 11)
#define ND_CFF_CMOV ND_CFF(0x00000001, 0xFFFFFFFF, NDR_EDX, 15)
#define ND_CFF_CLFSH ND_CFF(0x00000001, 0xFFFFFFFF, NDR_EDX, 19)
#define ND_CFF_MMX ND_CFF(0x00000001, 0xFFFFFFFF, NDR_EDX, 23)
#define ND_CFF_FXSAVE ND_CFF(0x00000001, 0xFFFFFFFF, NDR_EDX, 24)
#define ND_CFF_SSE ND_CFF(0x00000001, 0xFFFFFFFF, NDR_EDX, 25)
#define ND_CFF_SSE2 ND_CFF(0x00000001, 0xFFFFFFFF, NDR_EDX, 26)
#define ND_CFF_SSE3 ND_CFF(0x00000001, 0xFFFFFFFF, NDR_ECX, 0)
#define ND_CFF_PCLMULQDQ ND_CFF(0x00000001, 0xFFFFFFFF, NDR_ECX, 1)
#define ND_CFF_MONITOR ND_CFF(0x00000001, 0xFFFFFFFF, NDR_ECX, 3)
#define ND_CFF_VTX ND_CFF(0x00000001, 0xFFFFFFFF, NDR_ECX, 5)
#define ND_CFF_SMX ND_CFF(0x00000001, 0xFFFFFFFF, NDR_ECX, 6)
#define ND_CFF_SSSE3 ND_CFF(0x00000001, 0xFFFFFFFF, NDR_ECX, 9)
#define ND_CFF_FMA ND_CFF(0x00000001, 0xFFFFFFFF, NDR_ECX, 12)
#define ND_CFF_SSE4 ND_CFF(0x00000001, 0xFFFFFFFF, NDR_ECX, 19)
#define ND_CFF_SSE42 ND_CFF(0x00000001, 0xFFFFFFFF, NDR_ECX, 20)
#define ND_CFF_MOVBE ND_CFF(0x00000001, 0xFFFFFFFF, NDR_ECX, 22)
#define ND_CFF_POPCNT ND_CFF(0x00000001, 0xFFFFFFFF, NDR_ECX, 23)
#define ND_CFF_AES ND_CFF(0x00000001, 0xFFFFFFFF, NDR_ECX, 25)
#define ND_CFF_XSAVE ND_CFF(0x00000001, 0xFFFFFFFF, NDR_ECX, 26)
#define ND_CFF_AVX ND_CFF(0x00000001, 0xFFFFFFFF, NDR_ECX, 28)
#define ND_CFF_F16C ND_CFF(0x00000001, 0xFFFFFFFF, NDR_ECX, 29)
#define ND_CFF_RDRAND ND_CFF(0x00000001, 0xFFFFFFFF, NDR_ECX, 30)
#define ND_CFF_RDWRFSGS ND_CFF(0x00000007, 0x00000000, NDR_EBX, 0)
#define ND_CFF_SGX ND_CFF(0x00000007, 0x00000000, NDR_EBX, 2)
#define ND_CFF_BMI1 ND_CFF(0x00000007, 0x00000000, NDR_EBX, 3)
#define ND_CFF_HLE ND_CFF(0x00000007, 0x00000000, NDR_EBX, 4)
#define ND_CFF_AVX2 ND_CFF(0x00000007, 0x00000000, NDR_EBX, 5)
#define ND_CFF_BMI2 ND_CFF(0x00000007, 0x00000000, NDR_EBX, 8)
#define ND_CFF_INVPCID ND_CFF(0x00000007, 0x00000000, NDR_EBX, 10)
#define ND_CFF_RTM ND_CFF(0x00000007, 0x00000000, NDR_EBX, 11)
#define ND_CFF_MPX ND_CFF(0x00000007, 0x00000000, NDR_EBX, 14)
#define ND_CFF_AVX512F ND_CFF(0x00000007, 0x00000000, NDR_EBX, 16)
#define ND_CFF_AVX512DQ ND_CFF(0x00000007, 0x00000000, NDR_EBX, 17)
#define ND_CFF_RDSEED ND_CFF(0x00000007, 0x00000000, NDR_EBX, 18)
#define ND_CFF_ADX ND_CFF(0x00000007, 0x00000000, NDR_EBX, 19)
#define ND_CFF_SMAP ND_CFF(0x00000007, 0x00000000, NDR_EBX, 20)
#define ND_CFF_AVX512IFMA ND_CFF(0x00000007, 0x00000000, NDR_EBX, 21)
#define ND_CFF_CLFSHOPT ND_CFF(0x00000007, 0x00000000, NDR_EBX, 23)
#define ND_CFF_CLWB ND_CFF(0x00000007, 0x00000000, NDR_EBX, 24)
#define ND_CFF_AVX512PF ND_CFF(0x00000007, 0x00000000, NDR_EBX, 26)
#define ND_CFF_AVX512ER ND_CFF(0x00000007, 0x00000000, NDR_EBX, 27)
#define ND_CFF_AVX512CD ND_CFF(0x00000007, 0x00000000, NDR_EBX, 28)
#define ND_CFF_SHA ND_CFF(0x00000007, 0x00000000, NDR_EBX, 29)
#define ND_CFF_AVX512BW ND_CFF(0x00000007, 0x00000000, NDR_EBX, 30)
#define ND_CFF_PREFETCHWT1 ND_CFF(0x00000007, 0x00000000, NDR_ECX, 0)
#define ND_CFF_AVX512VBMI ND_CFF(0x00000007, 0x00000000, NDR_ECX, 1)
#define ND_CFF_PKU ND_CFF(0x00000007, 0x00000000, NDR_ECX, 3)
#define ND_CFF_WAITPKG ND_CFF(0x00000007, 0x00000000, NDR_ECX, 5)
#define ND_CFF_AVX512VBMI2 ND_CFF(0x00000007, 0x00000000, NDR_ECX, 6)
#define ND_CFF_CET_SS ND_CFF(0x00000007, 0x00000000, NDR_ECX, 7)
#define ND_CFF_GFNI ND_CFF(0x00000007, 0x00000000, NDR_ECX, 8)
#define ND_CFF_VAES ND_CFF(0x00000007, 0x00000000, NDR_ECX, 9)
#define ND_CFF_VPCLMULQDQ ND_CFF(0x00000007, 0x00000000, NDR_ECX, 10)
#define ND_CFF_AVX512VNNI ND_CFF(0x00000007, 0x00000000, NDR_ECX, 11)
#define ND_CFF_AVX512BITALG ND_CFF(0x00000007, 0x00000000, NDR_ECX, 12)
#define ND_CFF_AVX512VPOPCNTDQ ND_CFF(0x00000007, 0x00000000, NDR_ECX, 14)
#define ND_CFF_RDPID ND_CFF(0x00000007, 0x00000000, NDR_ECX, 22)
Added support for Intel Key Locker instructions, as per https://software.intel.com/content/www/us/en/develop/download/intel-key-locker-specification.html.
2020-09-16 08:56:05 +00:00
#define ND_CFF_KL ND_CFF(0x00000007, 0x00000000, NDR_ECX, 23)
Renamed REG_* fields to NDR_*, so that we don't conflict with _GNU_SOURCES.
2020-07-29 08:05:27 +00:00
#define ND_CFF_CLDEMOTE ND_CFF(0x00000007, 0x00000000, NDR_ECX, 25)
#define ND_CFF_MOVDIRI ND_CFF(0x00000007, 0x00000000, NDR_ECX, 27)
#define ND_CFF_MOVDIR64B ND_CFF(0x00000007, 0x00000000, NDR_ECX, 28)
#define ND_CFF_ENQCMD ND_CFF(0x00000007, 0x00000000, NDR_ECX, 29)
#define ND_CFF_AVX5124VNNIW ND_CFF(0x00000007, 0x00000000, NDR_EDX, 2)
#define ND_CFF_AVX5124FMAPS ND_CFF(0x00000007, 0x00000000, NDR_EDX, 3)
Added support for UINTR, HRESET and AVX-VNNI instructions, as per Intel® Architecture Instruction Set Extensions Programming Reference 41 (October 2020).
2020-10-05 10:19:03 +00:00
#define ND_CFF_UINTR ND_CFF(0x00000007, 0x00000000, NDR_EDX, 5)
Renamed REG_* fields to NDR_*, so that we don't conflict with _GNU_SOURCES.
2020-07-29 08:05:27 +00:00
#define ND_CFF_AVX512VP2INTERSECT ND_CFF(0x00000007, 0x00000000, NDR_EDX, 8)
#define ND_CFF_SERIALIZE ND_CFF(0x00000007, 0x00000000, NDR_EDX, 14)
#define ND_CFF_TSXLDTRK ND_CFF(0x00000007, 0x00000000, NDR_EDX, 16)
#define ND_CFF_PCONFIG ND_CFF(0x00000007, 0x00000000, NDR_EDX, 18)
#define ND_CFF_CET_IBT ND_CFF(0x00000007, 0x00000000, NDR_EDX, 20)
#define ND_CFF_AMXBF16 ND_CFF(0x00000007, 0x00000000, NDR_EDX, 22)
Added support for UINTR, HRESET and AVX-VNNI instructions, as per Intel® Architecture Instruction Set Extensions Programming Reference 41 (October 2020).
2020-10-05 10:19:03 +00:00
#define ND_CFF_AVX512FP16 ND_CFF(0x00000007, 0x00000000, NDR_EDX, 23)
Renamed REG_* fields to NDR_*, so that we don't conflict with _GNU_SOURCES.
2020-07-29 08:05:27 +00:00
#define ND_CFF_AMXTILE ND_CFF(0x00000007, 0x00000000, NDR_EDX, 24)
#define ND_CFF_AMXINT8 ND_CFF(0x00000007, 0x00000000, NDR_EDX, 25)
Added support for new Intel ISA, per Intel® Architecture Instruction Set Extensions and Future Features document #319433-049 (June 2023): AVX-NNI-INT16, SHA512, SM3, SM4, TSE.
2023-07-21 06:38:49 +00:00
#define ND_CFF_SHA512 ND_CFF(0x00000007, 0x00000001, NDR_EAX, 0)
#define ND_CFF_SM3 ND_CFF(0x00000007, 0x00000001, NDR_EAX, 1)
#define ND_CFF_SM4 ND_CFF(0x00000007, 0x00000001, NDR_EAX, 2)
Added support for new Intel instructions, per Intel ISA extensions document #319433-046 (September 2022): PREFETCHITI, RAO-INT, CMPCCXADD, WRMSRNS, MSRLIST, AMX-FP16, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8. Multiple minor fixes to existing instructions. Moved x86 decoding tests in a separate directory & improved the test script.
2022-10-04 09:22:59 +00:00
#define ND_CFF_RAOINT ND_CFF(0x00000007, 0x00000001, NDR_EAX, 3)
Added support for UINTR, HRESET and AVX-VNNI instructions, as per Intel® Architecture Instruction Set Extensions Programming Reference 41 (October 2020).
2020-10-05 10:19:03 +00:00
#define ND_CFF_AVXVNNI ND_CFF(0x00000007, 0x00000001, NDR_EAX, 4)
Renamed REG_* fields to NDR_*, so that we don't conflict with _GNU_SOURCES.
2020-07-29 08:05:27 +00:00
#define ND_CFF_AVX512BF16 ND_CFF(0x00000007, 0x00000001, NDR_EAX, 5)
Added support for new Intel instructions, per Intel ISA extensions document #319433-046 (September 2022): PREFETCHITI, RAO-INT, CMPCCXADD, WRMSRNS, MSRLIST, AMX-FP16, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8. Multiple minor fixes to existing instructions. Moved x86 decoding tests in a separate directory & improved the test script.
2022-10-04 09:22:59 +00:00
#define ND_CFF_CMPCCXADD ND_CFF(0x00000007, 0x00000001, NDR_EAX, 7)
Added support for Intel FRED and LKGS instructions.
2021-03-15 12:05:44 +00:00
#define ND_CFF_FRED ND_CFF(0x00000007, 0x00000001, NDR_EAX, 17)
#define ND_CFF_LKGS ND_CFF(0x00000007, 0x00000001, NDR_EAX, 18)
Added support for new Intel instructions, per Intel ISA extensions document #319433-046 (September 2022): PREFETCHITI, RAO-INT, CMPCCXADD, WRMSRNS, MSRLIST, AMX-FP16, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8. Multiple minor fixes to existing instructions. Moved x86 decoding tests in a separate directory & improved the test script.
2022-10-04 09:22:59 +00:00
#define ND_CFF_WRMSRNS ND_CFF(0x00000007, 0x00000001, NDR_EAX, 19)
#define ND_CFF_AMXFP16 ND_CFF(0x00000007, 0x00000001, NDR_EAX, 21)
Added support for UINTR, HRESET and AVX-VNNI instructions, as per Intel® Architecture Instruction Set Extensions Programming Reference 41 (October 2020).
2020-10-05 10:19:03 +00:00
#define ND_CFF_HRESET ND_CFF(0x00000007, 0x00000001, NDR_EAX, 22)
Added support for new Intel instructions, per Intel ISA extensions document #319433-046 (September 2022): PREFETCHITI, RAO-INT, CMPCCXADD, WRMSRNS, MSRLIST, AMX-FP16, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8. Multiple minor fixes to existing instructions. Moved x86 decoding tests in a separate directory & improved the test script.
2022-10-04 09:22:59 +00:00
#define ND_CFF_AVXIFMA ND_CFF(0x00000007, 0x00000001, NDR_EAX, 23)
#define ND_CFF_MSRLIST ND_CFF(0x00000007, 0x00000001, NDR_EAX, 27)
Added support for new Intel ISA, per Intel® Architecture Instruction Set Extensions and Future Features document #319433-049 (June 2023): AVX-NNI-INT16, SHA512, SM3, SM4, TSE.
2023-07-21 06:38:49 +00:00
#define ND_CFF_TSE ND_CFF(0x00000007, 0x00000001, NDR_EBX, 1)
Added support for new Intel instructions, per Intel ISA extensions document #319433-046 (September 2022): PREFETCHITI, RAO-INT, CMPCCXADD, WRMSRNS, MSRLIST, AMX-FP16, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8. Multiple minor fixes to existing instructions. Moved x86 decoding tests in a separate directory & improved the test script.
2022-10-04 09:22:59 +00:00
#define ND_CFF_AVXVNNIINT8 ND_CFF(0x00000007, 0x00000001, NDR_EDX, 4)
#define ND_CFF_AVXNECONVERT ND_CFF(0x00000007, 0x00000001, NDR_EDX, 5)
Added support for Intel AMX-COMPLEX instructions.
2023-04-05 06:45:07 +00:00
#define ND_CFF_AMXCOMPLEX ND_CFF(0x00000007, 0x00000001, NDR_EDX, 8)
Added support for new Intel ISA, per Intel® Architecture Instruction Set Extensions and Future Features document #319433-049 (June 2023): AVX-NNI-INT16, SHA512, SM3, SM4, TSE.
2023-07-21 06:38:49 +00:00
#define ND_CFF_AVXVNNIINT16 ND_CFF(0x00000007, 0x00000001, NDR_EDX, 10)
Added support for new Intel instructions, per Intel ISA extensions document #319433-046 (September 2022): PREFETCHITI, RAO-INT, CMPCCXADD, WRMSRNS, MSRLIST, AMX-FP16, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8. Multiple minor fixes to existing instructions. Moved x86 decoding tests in a separate directory & improved the test script.
2022-10-04 09:22:59 +00:00
#define ND_CFF_PREFETCHITI ND_CFF(0x00000007, 0x00000001, NDR_EDX, 14)
BDDISASM v2.1.0 release - please consult the CHANGELOG for details about the modifications.
2024-02-20 11:39:22 +00:00
#define ND_CFF_USER_MSR ND_CFF(0x00000007, 0x00000001, NDR_EDX, 15)
#define ND_CFF_APX_F ND_CFF(0x00000007, 0x00000001, NDR_EDX, 21)
Renamed REG_* fields to NDR_*, so that we don't conflict with _GNU_SOURCES.
2020-07-29 08:05:27 +00:00
#define ND_CFF_XSAVEOPT ND_CFF(0x0000000D, 0x00000001, NDR_EAX, 0)
#define ND_CFF_XSAVEC ND_CFF(0x0000000D, 0x00000001, NDR_EAX, 1)
#define ND_CFF_XSAVES ND_CFF(0x0000000D, 0x00000001, NDR_EAX, 3)
#define ND_CFF_PTWRITE ND_CFF(0x00000014, 0x00000000, NDR_EBX, 4)
#define ND_CFF_SVM ND_CFF(0x80000001, 0xFFFFFFFF, NDR_ECX, 2)
#define ND_CFF_LZCNT ND_CFF(0x80000001, 0xFFFFFFFF, NDR_ECX, 5)
#define ND_CFF_SSE4A ND_CFF(0x80000001, 0xFFFFFFFF, NDR_ECX, 6)
#define ND_CFF_PREFETCHW ND_CFF(0x80000001, 0xFFFFFFFF, NDR_ECX, 8)
#define ND_CFF_FSC ND_CFF(0x80000001, 0xFFFFFFFF, NDR_ECX, 11)
#define ND_CFF_XOP ND_CFF(0x80000001, 0xFFFFFFFF, NDR_ECX, 11)
#define ND_CFF_LWP ND_CFF(0x80000001, 0xFFFFFFFF, NDR_ECX, 15)
#define ND_CFF_FMA4 ND_CFF(0x80000001, 0xFFFFFFFF, NDR_ECX, 16)
#define ND_CFF_TBM ND_CFF(0x80000001, 0xFFFFFFFF, NDR_ECX, 21)
#define ND_CFF_INVLPGB ND_CFF(0x80000001, 0xFFFFFFFF, NDR_EDX, 24)
#define ND_CFF_RDTSCP ND_CFF(0x80000001, 0xFFFFFFFF, NDR_ECX, 27)
#define ND_CFF_3DNOW ND_CFF(0x80000001, 0xFFFFFFFF, NDR_EDX, 31)
#define ND_CFF_WBNOINVD ND_CFF(0x80000008, 0xFFFFFFFF, NDR_EBX, 9)
#define ND_CFF_RDPRU ND_CFF(0x80000008, 0xFFFFFFFF, NDR_EBX, 4)
#define ND_CFF_MCOMMIT ND_CFF(0x80000008, 0xFFFFFFFF, NDR_EBX, 8)
#define ND_CFF_SNP ND_CFF(0x8000001F, 0xFFFFFFFF, NDR_EAX, 4)
Added support for AMD RMPQUERY instruction.
2022-10-27 09:37:02 +00:00
#define ND_CFF_RMPQUERY ND_CFF(0x8000001F, 0xFFFFFFFF, NDR_EAX, 6)
Initial commit.
2020-07-21 08:19:18 +00:00
Don't use reserved identifiers for include guards This fixes #5
2020-07-27 13:51:16 +00:00
#endif // CPUID_FLAGS_H
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