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mirror of https://github.com/trezor/trezor-firmware.git synced 2024-11-10 09:39:00 +00:00
Commit Graph

26 Commits

Author SHA1 Message Date
tychovrahe
9166dc330e refactor(core): reorganize model-specific files in embed/models
[no changelog]
2024-05-21 19:01:31 +02:00
tychovrahe
6b31b8eec3 chore(core): change USB manufacturer and product strings for new models
[no changelog]
2024-05-06 13:10:36 +02:00
matejcik
867300b8c6 chore(core): include T3T1 boardloader / bootloader production keys 2024-04-12 16:13:52 +02:00
tychovrahe
1600759457 refactor(core): simplify secret.h api, hide platform differences
[no changelog]
2024-04-11 16:13:58 +02:00
tychovrahe
ffccf849eb chore(core): fill T3T1 model full name
[no changelog]
2024-04-04 12:46:44 +02:00
cepetr
1e3e7f808b fix(core): fix build on disc2 model 2024-03-27 10:44:56 +01:00
tychovrahe
1909d1ebdb feat(core): improve flexibility of combine script, add combine fw make targets
[no changelog]
2024-03-13 22:12:57 +01:00
tychovrahe
b62dc27f06 feat(core): add translations support for U5 models
[no changelog]
2024-02-29 23:05:56 +01:00
tychovrahe
c3f84e2949 perf(core): optimize boot speed on U5 by using has processor to calculate image hashes, switches to sha256
[no changelog]
2024-02-29 23:05:56 +01:00
tychovrahe
a71a608ea7 feat(core): add basic support for T3T1 2024-02-29 23:05:56 +01:00
tychovrahe
8815e764d2 feat(core): add support for STM32U585
[no changelog]
2024-02-29 23:05:56 +01:00
cepetr
4cf781abb2 chore(core, legacy, storage): refactor flash drivers
[no changelog]
2024-02-29 23:05:56 +01:00
tychovrahe
353095ae95 feat(core): add support for STM32U5A9J-DK board
[no changelog]
2024-02-29 23:05:56 +01:00
tychovrahe
8150636a81 feat(core): add basic support for STM32U5 2024-02-29 23:05:56 +01:00
grdddj
b8ea21d24a feat(all): implement translations into Trezor
Co-authored-by matejcik <ja@matejcik.cz>
2024-02-12 14:49:32 +01:00
tychovrahe
8a4f376f20 refactor(core): prepare fw for differently sized fw chunks
[no changelog]
2023-10-20 16:33:53 +02:00
Martin Milata
040f6c2c8e Merge branch 'master' into release/23.09 2023-09-29 16:42:23 +02:00
matejcik
c892d4b0ba refactor(core): inject full model name from build script
so that we don't have to do awkward string operations when we need it

[no changelog]
2023-09-29 16:27:27 +02:00
Martin Milata
07027a69e9 Merge branch 'master' into release/23.09 2023-09-15 14:33:20 +02:00
tychovrahe
bd0b0b2d15 refactor(core): move model specific norcow config to model header
[no changelog]
2023-08-29 11:17:19 +02:00
tychovrahe
c9a657b074 feat(core): set final name for Safe 3
[no changelog]
2023-08-18 16:14:47 +02:00
tychovrahe
5a86add884 refactor(core): differentiate models by internal name in python
[no changelog]
2023-08-15 22:08:11 +02:00
tychovrahe
e8281385f6 feat(core): implement secret handling in bootloader 2023-08-15 09:37:38 +02:00
tychovrahe
238e3fd7c1 refactor(core): add abstraction over flash memory layout
[no changelog]
2023-07-25 10:25:20 +02:00
tychovrahe
d3284baf21 feat(core): support STM32F429 discovery board 2023-06-15 17:08:14 +02:00
tychovrahe
a2f8cb9d1c feat(core): add internal model field to features
[no changelog]
2023-06-06 09:39:45 +02:00