parent
4cf781abb2
commit
8815e764d2
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/* Trezor v2 boardloader linker script */
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ENTRY(reset_handler)
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MEMORY {
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FLASH (rx) : ORIGIN = 0x0C004000, LENGTH = 48K
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SRAM1 (wal) : ORIGIN = 0x30000000, LENGTH = 192K - 0x100
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BOOT_ARGS (wal) : ORIGIN = 0x3002FF00, LENGTH = 0x100
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SRAM2 (wal) : ORIGIN = 0x30030000, LENGTH = 64K
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SRAM3 (wal) : ORIGIN = 0x30040000, LENGTH = 512K
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SRAM5 (wal) : ORIGIN = 0x30080000, LENGTH = 0K /* SRAM5 is not available */
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SRAM6 (wal) : ORIGIN = 0x30080000, LENGTH = 0K /* SRAM6 is not available */
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SRAM4 (wal) : ORIGIN = 0x38000000, LENGTH = 16K
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}
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main_stack_base = ORIGIN(SRAM2) + SIZEOF(.stack); /* 8-byte aligned full descending stack */
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_sstack = ORIGIN(SRAM2);
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_estack = main_stack_base;
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/* used by the startup code to populate variables used by the C code */
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data_lma = LOADADDR(.data);
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data_vma = ADDR(.data);
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data_size = SIZEOF(.data);
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/* used by the startup code to populate variables used by the C code */
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sensitive_lma = LOADADDR(.sensitive);
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sensitive_vma = ADDR(.sensitive);
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sensitive_size = SIZEOF(.sensitive);
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/* used by the startup code to wipe memory */
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sram1_start = ORIGIN(SRAM1);
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sram1_end = ORIGIN(SRAM1) + LENGTH(SRAM1);
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sram2_start = ORIGIN(SRAM2);
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sram2_end = ORIGIN(SRAM2) + LENGTH(SRAM2);
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sram3_start = ORIGIN(SRAM3);
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sram3_end = ORIGIN(SRAM3) + LENGTH(SRAM3);
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sram4_start = ORIGIN(SRAM4);
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sram4_end = ORIGIN(SRAM4) + LENGTH(SRAM4);
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sram5_start = ORIGIN(SRAM5);
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sram5_end = ORIGIN(SRAM5) + LENGTH(SRAM5);
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sram6_start = ORIGIN(SRAM6);
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sram6_end = ORIGIN(SRAM6) + LENGTH(SRAM6);
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/* reserve 256 bytes for bootloader arguments */
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boot_args_start = ORIGIN(BOOT_ARGS);
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boot_args_end = ORIGIN(BOOT_ARGS) + LENGTH(BOOT_ARGS);
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SECTIONS {
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.vector_table : ALIGN(512) {
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KEEP(*(.vector_table));
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} >FLASH AT>FLASH
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.text : ALIGN(4) {
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*(.text*);
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. = ALIGN(4); /* make the section size a multiple of the word size */
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} >FLASH AT>FLASH
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.rodata : ALIGN(4) {
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*(.rodata*);
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. = ALIGN(4); /* make the section size a multiple of the word size */
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} >FLASH AT>FLASH
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.data : ALIGN(4) {
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*(.data*);
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. = ALIGN(8);
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} >SRAM1 AT>FLASH
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/DISCARD/ : {
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*(.ARM.exidx*);
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}
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.bss : ALIGN(4) {
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*(.bss*);
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. = ALIGN(4);
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} >SRAM1
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.buf : ALIGN(4) {
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*(.buf*);
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. = ALIGN(4);
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} >SRAM1
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.stack : ALIGN(8) {
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. = 16K; /* Overflow causes UsageFault */
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} >SRAM2
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.sensitive : ALIGN(8) {
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*(.sensitive*);
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. = ALIGN(4);
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} >SRAM2 AT>FLASH
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.fb : ALIGN(4) {
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__fb_start = .;
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*(.fb1*);
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*(.fb2*);
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__fb_end = .;
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. = ALIGN(4);
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} >SRAM3
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.boot_args : ALIGN(8) {
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*(.boot_command*);
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. = ALIGN(8);
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*(.boot_args*);
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. = ALIGN(8);
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} >BOOT_ARGS
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/* Hard-coded address for capabilities structure */
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.capabilities 0x0C00FF00 : {KEEP(*(.capabilities_section))}
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}
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/* Trezor v2 bootloader linker script */
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ENTRY(reset_handler)
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MEMORY {
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FLASH (rx) : ORIGIN = 0x0C010000, LENGTH = 128K
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SRAM1 (wal) : ORIGIN = 0x30000000, LENGTH = 192K - 0x100
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BOOT_ARGS (wal) : ORIGIN = 0x3002FF00, LENGTH = 0x100
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SRAM2 (wal) : ORIGIN = 0x30030000, LENGTH = 64K
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SRAM3 (wal) : ORIGIN = 0x30040000, LENGTH = 512K
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SRAM5 (wal) : ORIGIN = 0x30080000, LENGTH = 0K /* SRAM5 is not available */
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SRAM6 (wal) : ORIGIN = 0x30080000, LENGTH = 0K /* SRAM6 is not available */
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SRAM4 (wal) : ORIGIN = 0x38000000, LENGTH = 16K
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}
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main_stack_base = ORIGIN(SRAM2) + SIZEOF(.stack); /* 8-byte aligned full descending stack */
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_sstack = ORIGIN(SRAM2);
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_estack = main_stack_base;
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/* used by the startup code to populate variables used by the C code */
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data_lma = LOADADDR(.data);
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data_vma = ADDR(.data);
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data_size = SIZEOF(.data);
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/* used by the startup code to populate variables used by the C code */
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sensitive_lma = LOADADDR(.sensitive);
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sensitive_vma = ADDR(.sensitive);
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sensitive_size = SIZEOF(.sensitive);
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/* used by the startup code to wipe memory */
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sram1_start = ORIGIN(SRAM1);
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sram1_end = ORIGIN(SRAM1) + LENGTH(SRAM1);
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sram2_start = ORIGIN(SRAM2);
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sram2_end = ORIGIN(SRAM2) + LENGTH(SRAM2);
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sram3_start = ORIGIN(SRAM3);
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sram3_end = ORIGIN(SRAM3) + LENGTH(SRAM3);
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sram4_start = ORIGIN(SRAM4);
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sram4_end = ORIGIN(SRAM4) + LENGTH(SRAM4);
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sram5_start = ORIGIN(SRAM5);
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sram5_end = ORIGIN(SRAM5) + LENGTH(SRAM5);
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sram6_start = ORIGIN(SRAM6);
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sram6_end = ORIGIN(SRAM6) + LENGTH(SRAM6);
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/* reserve 256 bytes for bootloader arguments */
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boot_args_start = ORIGIN(BOOT_ARGS);
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boot_args_end = ORIGIN(BOOT_ARGS) + LENGTH(BOOT_ARGS);
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_codelen = SIZEOF(.flash) + SIZEOF(.data) + SIZEOF(.sensitive);
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SECTIONS {
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.header : ALIGN(4) {
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KEEP(*(.header));
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} >FLASH AT>FLASH
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.flash : ALIGN(512) {
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KEEP(*(.vector_table));
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. = ALIGN(4);
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*(.text*);
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. = ALIGN(4);
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*(.rodata*);
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. = ALIGN(512);
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} >FLASH AT>FLASH
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.data : ALIGN(4) {
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*(.data*);
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. = ALIGN(512);
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} >SRAM1 AT>FLASH
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/DISCARD/ : {
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*(.ARM.exidx*);
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}
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.bss : ALIGN(4) {
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*(.bss*);
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. = ALIGN(4);
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} >SRAM1
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.buf : ALIGN(4) {
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*(.buf*);
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. = ALIGN(4);
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} >SRAM1
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.stack : ALIGN(8) {
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. = 16K; /* Overflow causes UsageFault */
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} >SRAM2
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.sensitive : ALIGN(512) {
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*(.sensitive*);
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. = ALIGN(512);
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} >SRAM2 AT>FLASH
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.fb : ALIGN(4) {
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__fb_start = .;
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*(.fb1*);
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*(.fb2*);
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__fb_end = .;
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. = ALIGN(4);
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} >SRAM3
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.boot_args : ALIGN(8) {
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*(.boot_command*);
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. = ALIGN(8);
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*(.boot_args*);
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. = ALIGN(8);
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} >BOOT_ARGS
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}
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/* Trezor v2 bootloader linker script */
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ENTRY(reset_handler)
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MEMORY {
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FLASH (rx) : ORIGIN = 0x0C010000, LENGTH = 128K
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SRAM1 (wal) : ORIGIN = 0x30000000, LENGTH = 192K - 0x100
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BOOT_ARGS (wal) : ORIGIN = 0x3002FF00, LENGTH = 0x100
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SRAM2 (wal) : ORIGIN = 0x30030000, LENGTH = 64K
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SRAM3 (wal) : ORIGIN = 0x30040000, LENGTH = 512K
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SRAM5 (wal) : ORIGIN = 0x30080000, LENGTH = 0K /* SRAM5 is not available */
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SRAM6 (wal) : ORIGIN = 0x30080000, LENGTH = 0K /* SRAM6 is not available */
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SRAM4 (wal) : ORIGIN = 0x38000000, LENGTH = 16K
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}
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main_stack_base = ORIGIN(SRAM2) + SIZEOF(.stack); /* 8-byte aligned full descending stack */
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_sstack = ORIGIN(SRAM2);
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_estack = main_stack_base;
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/* used by the startup code to populate variables used by the C code */
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data_lma = LOADADDR(.data);
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data_vma = ADDR(.data);
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data_size = SIZEOF(.data);
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/* used by the startup code to populate variables used by the C code */
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sensitive_lma = LOADADDR(.sensitive);
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sensitive_vma = ADDR(.sensitive);
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sensitive_size = SIZEOF(.sensitive);
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/* used by the startup code to wipe memory */
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sram1_start = ORIGIN(SRAM1);
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sram1_end = ORIGIN(SRAM1) + LENGTH(SRAM1);
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sram2_start = ORIGIN(SRAM2);
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sram2_end = ORIGIN(SRAM2) + LENGTH(SRAM2);
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sram3_start = ORIGIN(SRAM3);
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sram3_end = ORIGIN(SRAM3) + LENGTH(SRAM3);
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sram4_start = ORIGIN(SRAM4);
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sram4_end = ORIGIN(SRAM4) + LENGTH(SRAM4);
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sram5_start = ORIGIN(SRAM5);
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sram5_end = ORIGIN(SRAM5) + LENGTH(SRAM5);
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sram6_start = ORIGIN(SRAM6);
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sram6_end = ORIGIN(SRAM6) + LENGTH(SRAM6);
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/* reserve 256 bytes for bootloader arguments */
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boot_args_start = ORIGIN(BOOT_ARGS);
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boot_args_end = ORIGIN(BOOT_ARGS) + LENGTH(BOOT_ARGS);
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_codelen = SIZEOF(.flash) + SIZEOF(.data) + SIZEOF(.sensitive);
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SECTIONS {
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.header : ALIGN(4) {
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KEEP(*(.header));
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} >FLASH AT>FLASH
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.flash : ALIGN(512) {
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KEEP(*(.vector_table));
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. = ALIGN(4);
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*(.text*);
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. = ALIGN(4);
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*(.rodata*);
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. = ALIGN(512);
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} >FLASH AT>FLASH
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.data : ALIGN(4) {
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*(.data*);
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. = ALIGN(512);
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} >SRAM1 AT>FLASH
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/DISCARD/ : {
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*(.ARM.exidx*);
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}
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.bss : ALIGN(4) {
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*(.bss*);
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. = ALIGN(4);
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} >SRAM1
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.buf : ALIGN(4) {
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*(.buf*);
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. = ALIGN(4);
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} >SRAM1
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.stack : ALIGN(8) {
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. = 16K; /* Exactly 16K allocated for stack. Overflow causes Usage fault. */
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} >SRAM2
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.sensitive : ALIGN(512) {
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*(.sensitive*);
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. = ALIGN(512);
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} >SRAM2 AT>FLASH
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.fb : ALIGN(4) {
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__fb_start = .;
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*(.fb1*);
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*(.fb2*);
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__fb_end = .;
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. = ALIGN(4);
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} >SRAM3
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.boot_args : ALIGN(8) {
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*(.boot_command*);
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. = ALIGN(8);
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*(.boot_args*);
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. = ALIGN(8);
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} >BOOT_ARGS
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}
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#ifndef SIZEDEFS_H_
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#define SIZEDEFS_H_
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#define SIZE_2K (2 * 1024)
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#define SIZE_16K (16 * 1024)
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#define SIZE_48K (48 * 1024)
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#define SIZE_64K (64 * 1024)
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#define SIZE_128K (128 * 1024)
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#define SIZE_192K (192 * 1024)
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#define SIZE_256K (256 * 1024)
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#define SIZE_320K (320 * 1024)
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#define SIZE_768K (768 * 1024)
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#define SIZE_2496K (2496 * 1024)
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#define SIZE_3712K ((4096 - 384) * 1024)
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#define SIZE_3776K ((4096 - 320) * 1024)
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#define SIZE_3904K ((4096 - 192) * 1024)
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#define SIZE_4032K ((4096 - 64) * 1024)
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#define SIZE_2M (2 * 1024 * 1024)
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#define SIZE_4M (4 * 1024 * 1024)
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#define SIZE_16M (16 * 1024 * 1024)
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#define SIZE_256M (256 * 1024 * 1024)
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#define SIZE_512M (512 * 1024 * 1024)
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#endif
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@ -0,0 +1,121 @@
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/* TREZORv2 firmware linker script */
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ENTRY(reset_handler)
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MEMORY {
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FLASH (rx) : ORIGIN = 0x0C050000, LENGTH = 3648K
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SRAM1 (wal) : ORIGIN = 0x30000000, LENGTH = 192K - 0x100
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BOOT_ARGS (wal) : ORIGIN = 0x3002FF00, LENGTH = 0x100
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SRAM2 (wal) : ORIGIN = 0x30030000, LENGTH = 64K
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SRAM3 (wal) : ORIGIN = 0x30040000, LENGTH = 512K
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SRAM5 (wal) : ORIGIN = 0x30080000, LENGTH = 0K /* SRAM5 is not available */
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SRAM6 (wal) : ORIGIN = 0x30080000, LENGTH = 0K /* SRAM6 is not available */
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SRAM4 (wal) : ORIGIN = 0x38000000, LENGTH = 16K
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}
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main_stack_base = ORIGIN(SRAM2) + SIZEOF(.stack); /* 8-byte aligned full descending stack */
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_sstack = ORIGIN(SRAM2);
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_estack = main_stack_base;
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/* used by the startup code to populate variables used by the C code */
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data_lma = LOADADDR(.data);
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data_vma = ADDR(.data);
|
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data_size = SIZEOF(.data);
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/* used by the startup code to populate variables used by the C code */
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sensitive_lma = LOADADDR(.sensitive);
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sensitive_vma = ADDR(.sensitive);
|
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sensitive_size = SIZEOF(.sensitive);
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/* used by the startup code to wipe memory */
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sram1_start = ORIGIN(SRAM1);
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sram1_end = ORIGIN(SRAM1) + LENGTH(SRAM1);
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sram2_start = ORIGIN(SRAM2);
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sram2_end = ORIGIN(SRAM2) + LENGTH(SRAM2);
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sram3_start = ORIGIN(SRAM3);
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sram3_end = ORIGIN(SRAM3) + LENGTH(SRAM3);
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sram4_start = ORIGIN(SRAM4);
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sram4_end = ORIGIN(SRAM4) + LENGTH(SRAM4);
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sram5_start = ORIGIN(SRAM5);
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sram5_end = ORIGIN(SRAM5) + LENGTH(SRAM5);
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sram6_start = ORIGIN(SRAM6);
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sram6_end = ORIGIN(SRAM6) + LENGTH(SRAM6);
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|
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/* reserve 256 bytes for bootloader arguments */
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boot_args_start = ORIGIN(BOOT_ARGS);
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boot_args_end = ORIGIN(BOOT_ARGS) + LENGTH(BOOT_ARGS);
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_codelen = SIZEOF(.flash) + SIZEOF(.data) + SIZEOF(.sensitive);
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_flash_start = ORIGIN(FLASH);
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_flash_end = ORIGIN(FLASH) + LENGTH(FLASH);
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_heap_start = ADDR(.heap);
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_heap_end = ADDR(.heap) + SIZEOF(.heap);
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SECTIONS {
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.vendorheader : ALIGN(4) {
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KEEP(*(.vendorheader))
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} >FLASH AT>FLASH
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.header : ALIGN(4) {
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KEEP(*(.header));
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} >FLASH AT>FLASH
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.flash : ALIGN(512) {
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KEEP(*(.vector_table));
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. = ALIGN(4);
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*(.text*);
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. = ALIGN(4);
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*(.rodata*);
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. = ALIGN(4);
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KEEP(*(.bootloader));
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*(.bootloader*);
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. = ALIGN(512);
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} >FLASH AT>FLASH
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.data : ALIGN(4) {
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*(.data*);
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. = ALIGN(512);
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} >SRAM1 AT>FLASH
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/DISCARD/ : {
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*(.ARM.exidx*);
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}
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.bss : ALIGN(4) {
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*(.bss*);
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. = ALIGN(4);
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} >SRAM1
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.data_ccm : ALIGN(4) {
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*(.no_dma_buffers*);
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. = ALIGN(4);
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} >SRAM1
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|
||||
.heap : ALIGN(4) {
|
||||
. = 37K; /* this acts as a build time assertion that at least this much memory is available for heap use */
|
||||
. = ABSOLUTE(sram1_end); /* this explicitly sets the end of the heap */
|
||||
} >SRAM1
|
||||
|
||||
.stack : ALIGN(8) {
|
||||
. = 16K; /* Overflow causes UsageFault */
|
||||
} >SRAM2
|
||||
|
||||
.sensitive : ALIGN(512) {
|
||||
*(.sensitive*);
|
||||
. = ALIGN(512);
|
||||
} >SRAM2 AT>FLASH
|
||||
|
||||
.fb : ALIGN(4) {
|
||||
__fb_start = .;
|
||||
*(.fb1*);
|
||||
*(.fb2*);
|
||||
__fb_end = .;
|
||||
. = ALIGN(4);
|
||||
} >SRAM3
|
||||
|
||||
.boot_args : ALIGN(8) {
|
||||
*(.boot_command*);
|
||||
. = ALIGN(8);
|
||||
*(.boot_args*);
|
||||
. = ALIGN(8);
|
||||
} >BOOT_ARGS
|
||||
}
|
@ -0,0 +1,122 @@
|
||||
/* TREZORv2 firmware linker script */
|
||||
|
||||
ENTRY(reset_handler)
|
||||
|
||||
MEMORY {
|
||||
FLASH (rx) : ORIGIN = 0x0C050000, LENGTH = 3648K
|
||||
SRAM1 (wal) : ORIGIN = 0x30000000, LENGTH = 192K - 0x100
|
||||
BOOT_ARGS (wal) : ORIGIN = 0x3002FF00, LENGTH = 0x100
|
||||
SRAM2 (wal) : ORIGIN = 0x30030000, LENGTH = 64K
|
||||
SRAM3 (wal) : ORIGIN = 0x30040000, LENGTH = 512K
|
||||
SRAM5 (wal) : ORIGIN = 0x30080000, LENGTH = 0K /* SRAM5 is not available */
|
||||
SRAM6 (wal) : ORIGIN = 0x30080000, LENGTH = 0K /* SRAM6 is not available */
|
||||
SRAM4 (wal) : ORIGIN = 0x38000000, LENGTH = 16K
|
||||
}
|
||||
|
||||
main_stack_base = ORIGIN(SRAM2) + SIZEOF(.stack); /* 8-byte aligned full descending stack */
|
||||
_sstack = ORIGIN(SRAM2);
|
||||
_estack = main_stack_base;
|
||||
|
||||
/* used by the startup code to populate variables used by the C code */
|
||||
data_lma = LOADADDR(.data);
|
||||
data_vma = ADDR(.data);
|
||||
data_size = SIZEOF(.data);
|
||||
|
||||
/* used by the startup code to populate variables used by the C code */
|
||||
sensitive_lma = LOADADDR(.sensitive);
|
||||
sensitive_vma = ADDR(.sensitive);
|
||||
sensitive_size = SIZEOF(.sensitive);
|
||||
|
||||
/* used by the startup code to wipe memory */
|
||||
sram1_start = ORIGIN(SRAM1);
|
||||
sram1_end = ORIGIN(SRAM1) + LENGTH(SRAM1);
|
||||
sram2_start = ORIGIN(SRAM2);
|
||||
sram2_end = ORIGIN(SRAM2) + LENGTH(SRAM2);
|
||||
sram3_start = ORIGIN(SRAM3);
|
||||
sram3_end = ORIGIN(SRAM3) + LENGTH(SRAM3);
|
||||
sram4_start = ORIGIN(SRAM4);
|
||||
sram4_end = ORIGIN(SRAM4) + LENGTH(SRAM4);
|
||||
sram5_start = ORIGIN(SRAM5);
|
||||
sram5_end = ORIGIN(SRAM5) + LENGTH(SRAM5);
|
||||
sram6_start = ORIGIN(SRAM6);
|
||||
sram6_end = ORIGIN(SRAM6) + LENGTH(SRAM6);
|
||||
|
||||
/* reserve 256 bytes for bootloader arguments */
|
||||
boot_args_start = ORIGIN(BOOT_ARGS);
|
||||
boot_args_end = ORIGIN(BOOT_ARGS) + LENGTH(BOOT_ARGS);
|
||||
|
||||
_codelen = SIZEOF(.flash) + SIZEOF(.data) + SIZEOF(.sensitive);
|
||||
_flash_start = ORIGIN(FLASH);
|
||||
_flash_end = ORIGIN(FLASH) + LENGTH(FLASH);
|
||||
_heap_start = ADDR(.heap);
|
||||
_heap_end = ADDR(.heap) + SIZEOF(.heap);
|
||||
|
||||
SECTIONS {
|
||||
.vendorheader : ALIGN(4) {
|
||||
KEEP(*(.vendorheader))
|
||||
} >FLASH AT>FLASH
|
||||
|
||||
.header : ALIGN(4) {
|
||||
KEEP(*(.header));
|
||||
} >FLASH AT>FLASH
|
||||
|
||||
.flash : ALIGN(512) {
|
||||
KEEP(*(.vector_table));
|
||||
. = ALIGN(4);
|
||||
*(.text*);
|
||||
. = ALIGN(4);
|
||||
*(.rodata*);
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.bootloader));
|
||||
*(.bootloader*);
|
||||
. = ALIGN(512);
|
||||
} >FLASH AT>FLASH
|
||||
|
||||
.data : ALIGN(4) {
|
||||
*(.data*);
|
||||
. = ALIGN(512);
|
||||
} >SRAM1 AT>FLASH
|
||||
|
||||
/DISCARD/ : {
|
||||
*(.ARM.exidx*);
|
||||
}
|
||||
|
||||
.bss : ALIGN(4) {
|
||||
*(.bss*);
|
||||
. = ALIGN(4);
|
||||
} >SRAM1
|
||||
|
||||
.data_ccm : ALIGN(4) {
|
||||
*(.no_dma_buffers*);
|
||||
. = ALIGN(4);
|
||||
} >SRAM1
|
||||
|
||||
.heap : ALIGN(4) {
|
||||
. = 37K; /* this acts as a build time assertion that at least this much memory is available for heap use */
|
||||
. = ABSOLUTE(sram1_end); /* this explicitly sets the end of the heap */
|
||||
} >SRAM1
|
||||
|
||||
.stack : ALIGN(8) {
|
||||
. = 16K + 0x100; /* Overflow causes UsageFault */
|
||||
} >SRAM2
|
||||
|
||||
.sensitive : ALIGN(512) {
|
||||
*(.sensitive*);
|
||||
. = ALIGN(512);
|
||||
} >SRAM2 AT>FLASH
|
||||
|
||||
.fb : ALIGN(4) {
|
||||
__fb_start = .;
|
||||
*(.fb1*);
|
||||
*(.fb2*);
|
||||
__fb_end = .;
|
||||
. = ALIGN(4);
|
||||
} >SRAM3
|
||||
|
||||
.boot_args : ALIGN(8) {
|
||||
*(.boot_command*);
|
||||
. = ALIGN(8);
|
||||
*(.boot_args*);
|
||||
. = ALIGN(8);
|
||||
} >BOOT_ARGS
|
||||
}
|
Loading…
Reference in new issue