Commit Graph

9 Commits (f53cbc51e2a325990acf075f87418c5913bc19d5)

Author SHA1 Message Date
Andrei Vlad LUTAS f53cbc51e2 Added support for new Intel ISA, per Intel® Architecture Instruction Set Extensions and Future Features document #319433-049 (June 2023): AVX-NNI-INT16, SHA512, SM3, SM4, TSE.
11 months ago
BITDEFENDER\vlutas 124521beb5 Added support for Intel AMX-COMPLEX instructions.
1 year ago
BITDEFENDER\vlutas ee6cdd6cb6 Switched to a more parsing-friendly format for the instructions database, where individual components are sepparated by a semicolon.
1 year ago
BITDEFENDER\vlutas 24665b0531 Switched from nil to n/a naming for absent operands, as it is more obvious.
1 year ago
BITDEFENDER\vlutas 9ba1e6a2f9 Added support for new Intel instructions, per Intel ISA extensions document #319433-046 (September 2022): PREFETCHITI, RAO-INT, CMPCCXADD, WRMSRNS, MSRLIST, AMX-FP16, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8.
2 years ago
Andrei Vlad LUTAS 9652450125 Added support for UINTR, HRESET and AVX-VNNI instructions, as per Intel® Architecture Instruction Set Extensions Programming Reference 41 (October 2020).
4 years ago
Andrei Vlad LUTAS 752bc626c4 Fixed RET with immediate - the immediate is not sign-extended.
4 years ago
Andrei Vlad LUTAS efe359b506 Typo fixes in the instruction tables.
4 years ago
Andrei Vlad LUTAS 698ba367a1 Initial commit.
4 years ago