BITDEFENDER\vlutas
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ee6cdd6cb6
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Switched to a more parsing-friendly format for the instructions database, where individual components are sepparated by a semicolon.
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2023-02-09 10:54:45 +02:00 |
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BITDEFENDER\vlutas
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24665b0531
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Switched from nil to n/a naming for absent operands, as it is more obvious.
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2023-02-08 17:44:45 +02:00 |
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BITDEFENDER\vlutas
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9ba1e6a2f9
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Added support for new Intel instructions, per Intel ISA extensions document #319433-046 (September 2022): PREFETCHITI, RAO-INT, CMPCCXADD, WRMSRNS, MSRLIST, AMX-FP16, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8.
Multiple minor fixes to existing instructions.
Moved x86 decoding tests in a separate directory & improved the test script.
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2022-10-04 12:22:59 +03:00 |
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BITDEFENDER\vlutas
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fe6a937f51
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Switched to internally defined types.
WRUSSD and WRUSSQ cannot be executed when CPL != 0.
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2022-01-05 14:03:13 +02:00 |
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Andrei Vlad LUTAS
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4f8b030ddd
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Added support for Intel Key Locker instructions, as per https://software.intel.com/content/www/us/en/develop/download/intel-key-locker-specification.html.
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2020-09-16 11:56:05 +03:00 |
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Andrei Vlad LUTAS
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8392c97f97
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Use the documented byte granularity for cache-line accesses.
Fixed CET CPUID feature flag - split into CET_SS and CET_IBT.
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2020-07-22 00:47:46 +03:00 |
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Andrei Vlad LUTAS
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efe359b506
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Typo fixes in the instruction tables.
Added a reference to the git repo in the documentation.
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2020-07-21 16:38:09 +03:00 |
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Andrei Vlad LUTAS
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698ba367a1
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Initial commit.
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2020-07-21 11:19:18 +03:00 |
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