5 Commits

Author	SHA1	Message	Date
Andrei Vlad LUTAS	42b6eceae6	* Add support for SIMD exceptions reporting in INSTRUX. ... * Add support for new ISAs: MOVRS, MSR_IMM, AMX-FP8, AMX-TRANSPOSE, AMX-TF32, AMX-AVX512, AMX-MOVRS, EVEX-encoded SM4. Co-authored-by: ianichitei (Rust bindings)	2024-11-07 11:58:23 +02:00
Andrei Vlad LUTAS	fad9c7e35c	BDDISASM v2.1.0 release - please consult the CHANGELOG for details about the modifications.	2024-02-20 13:39:22 +02:00
BITDEFENDER\vlutas	fe6a937f51	Switched to internally defined types. ... WRUSSD and WRUSSQ cannot be executed when CPL != 0.	2022-01-05 14:03:13 +02:00
Andrei Vlad LUTAS	76d92e73c2	Multiple changes ... - Add support for AVX512-FP16 instructions, as per https://software.intel.com/content/www/us/en/develop/download/intel-avx512-fp16-architecture-specification.html - Bug fix: zeroing with no masking is not supported, so return an error if we encounter such encodings - Bug fix: ignore VEX/EVEX.W field outside 64 bit mode for some instructions - Several other minor fixes and improvements	2021-07-08 12:40:39 +03:00
Andrei Vlad LUTAS	698ba367a1	Initial commit.	2020-07-21 11:19:18 +03:00