3 Commits

Author	SHA1	Message	Date
Andrei Vlad LUTAS	42b6eceae6	* Add support for SIMD exceptions reporting in INSTRUX. ... * Add support for new ISAs: MOVRS, MSR_IMM, AMX-FP8, AMX-TRANSPOSE, AMX-TF32, AMX-AVX512, AMX-MOVRS, EVEX-encoded SM4. Co-authored-by: ianichitei (Rust bindings)	2024-11-07 11:58:23 +02:00
BITDEFENDER\vlutas	124521beb5	Added support for Intel AMX-COMPLEX instructions.	2023-04-05 09:45:07 +03:00
BITDEFENDER\vlutas	9ba1e6a2f9	Added support for new Intel instructions, per Intel ISA extensions document #319433-046 (September 2022): PREFETCHITI, RAO-INT, CMPCCXADD, WRMSRNS, MSRLIST, AMX-FP16, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8. ... Multiple minor fixes to existing instructions. Moved x86 decoding tests in a separate directory & improved the test script.	2022-10-04 12:22:59 +03:00