4 Commits

Author	SHA1	Message	Date
Andrei Vlad LUTAS	f53cbc51e2	Added support for new Intel ISA, per Intel® Architecture Instruction Set Extensions and Future Features document #319433-049 (June 2023): AVX-NNI-INT16, SHA512, SM3, SM4, TSE.	2023-07-21 09:38:49 +03:00
BITDEFENDER\vlutas	124521beb5	Added support for Intel AMX-COMPLEX instructions.	2023-04-05 09:45:07 +03:00
BITDEFENDER\vlutas	7a254037b0	Added support for AMD RMPQUERY instruction.	2022-10-27 12:37:02 +03:00
BITDEFENDER\vlutas	9ba1e6a2f9	Added support for new Intel instructions, per Intel ISA extensions document #319433-046 (September 2022): PREFETCHITI, RAO-INT, CMPCCXADD, WRMSRNS, MSRLIST, AMX-FP16, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8. ... Multiple minor fixes to existing instructions. Moved x86 decoding tests in a separate directory & improved the test script.	2022-10-04 12:22:59 +03:00