Commit Graph

14 Commits (58197cc518f363772dfb5cdb7e309d139c049be2)

Author SHA1 Message Date
Andrei Vlad LUTAS 58197cc518 Removed support for PCOMMIT and CL1INVMB (not implemented by any x86/x64 CPUs), and marked MOV to/from test registers as being invalid in long mode.
4 years ago
Andrei Vlad LUTAS bcf9a89d69 Fixed https://github.com/bitdefender/bddisasm/issues/22 and https://github.com/bitdefender/bddisasm/issues/23.
4 years ago
Andrei Vlad LUTAS 9652450125 Added support for UINTR, HRESET and AVX-VNNI instructions, as per Intel® Architecture Instruction Set Extensions Programming Reference 41 (October 2020).
4 years ago
Andrei Vlad LUTAS 33078e4670 Added support for TDX instructions, per https://software.intel.com/content/dam/develop/external/us/en/documents/intel-tdx-cpu-architectural-specification.pdf.
4 years ago
Andrei Vlad LUTAS ed564dba32 Specifically flag multi-byte NOP operands as not-accessed.
4 years ago
Andrei Vlad LUTAS d622f56211 Added SERIAL flag to the SERIALIZE instruction.
4 years ago
Andrei Vlad LUTAS 4b2f2aee66 Added dedicated Prefetch operand access type.
4 years ago
Andrei Vlad LUTAS 752bc626c4 Fixed RET with immediate - the immediate is not sign-extended.
4 years ago
Andrei Vlad LUTAS 94d7894fa5 Added the Shadow Stack Pointer operand to the SYSRET and SYSENTER instructions.
4 years ago
Andrei Vlad LUTAS 8392c97f97 Use the documented byte granularity for cache-line accesses.
4 years ago
Andrei Vlad LUTAS 9ff2543660 Added the Shadow Stack Pointer operand to the SYSCALL and SYSEXIT instructions.
4 years ago
Andrei Vlad LUTAS 811c3d0f7c Fixed several issues with CET instructions specification - shadow stack and shadow stack pointer implicit operands were missing from SETSSBSY instruction, and flags access was missing from them.
4 years ago
Andrei Vlad LUTAS efe359b506 Typo fixes in the instruction tables.
4 years ago
Andrei Vlad LUTAS 698ba367a1 Initial commit.
4 years ago