bddisasm

Author	SHA1	Message	Date
$BITDEFENDER\vlutas$ BITDEFENDER\vlutas	9ba1e6a2f9	Added support for new Intel instructions, per Intel ISA extensions document #319433-046 (September 2022): PREFETCHITI, RAO-INT, CMPCCXADD, WRMSRNS, MSRLIST, AMX-FP16, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8. Multiple minor fixes to existing instructions. Moved x86 decoding tests in a separate directory & improved the test script.	2 years ago
Andrei Vlad LUTAS	76d92e73c2	Multiple changes - Add support for AVX512-FP16 instructions, as per https://software.intel.com/content/www/us/en/develop/download/intel-avx512-fp16-architecture-specification.html - Bug fix: zeroing with no masking is not supported, so return an error if we encounter such encodings - Bug fix: ignore VEX/EVEX.W field outside 64 bit mode for some instructions - Several other minor fixes and improvements	3 years ago
Andrei Vlad LUTAS	698ba367a1	Initial commit.	4 years ago

Author

SHA1

Message

Date

$BITDEFENDER\vlutas$ BITDEFENDER\vlutas

Added support for new Intel instructions, per Intel ISA extensions document #319433-046 (September 2022): PREFETCHITI, RAO-INT, CMPCCXADD, WRMSRNS, MSRLIST, AMX-FP16, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8.

Multiple minor fixes to existing instructions.
Moved x86 decoding tests in a separate directory & improved the test script.

Andrei Vlad LUTAS

76d92e73c2

Multiple changes

- Add support for AVX512-FP16 instructions, as per https://software.intel.com/content/www/us/en/develop/download/intel-avx512-fp16-architecture-specification.html
- Bug fix: zeroing with no masking is not supported, so return an error if we encounter such encodings
- Bug fix: ignore VEX/EVEX.W field outside 64 bit mode for some instructions
- Several other minor fixes and improvements

Andrei Vlad LUTAS

698ba367a1

Initial commit.

3 Commits (master)