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bddisasm/isagenerator/instructions/table_evex_3.dat

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Switched from nil to n/a naming for absent operands, as it is more obvious.
2023-02-08 15:44:45 +00:00
#
# Copyright (c) 2020 Bitdefender
# SPDX-License-Identifier: Apache-2.0
#
Initial commit.
2020-07-21 08:19:18 +00:00
# 0x00 - 0x0F
BDDISASM v2.1.0 release - please consult the CHANGELOG for details about the modifications.
2024-02-20 11:39:22 +00:00
VPERMQ ; Vuv{K}{z},Wuv|B64,Ib ; ; evex m:3 p:1 l:x w:1 0x00 /r ib ; s:AVX512F, t:AVX512, a:NOL0, l:fv, e:E4NF, w:W|R|R|R
VPERMPD ; Vuv{K}{z},Wuv|B64,Ib ; ; evex m:3 p:1 l:x w:1 0x01 /r ib ; s:AVX512F, t:AVX512, a:NOL0, l:fv, e:E4NF, w:W|R|R|R
VALIGND ; Vfv{K}{z},Hfv,Wfv|B32,Ib ; ; evex m:3 p:1 l:x w:0 0x03 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R|R
VALIGNQ ; Vfv{K}{z},Hfv,Wfv|B64,Ib ; ; evex m:3 p:1 l:x w:1 0x03 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R|R
VPERMILPS ; Vfv{K}{z},Wfv|B32,Ib ; ; evex m:3 p:1 l:x w:0 0x04 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R
VPERMILPD ; Vfv{K}{z},Wfv|B64,Ib ; ; evex m:3 p:1 l:x w:1 0x05 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R
VRNDSCALEPH ; Vfv{K}{z},Wfv|B16{sae},Ib ; ; evex m:3 p:0 l:x w:0 0x08 /r ib ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R
VRNDSCALEPS ; Vfv{K}{z},Wfv|B32{sae},Ib ; ; evex m:3 p:1 l:x w:0 0x08 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R
Added support for new Intel AVX 10.2 instructions. Added support for AMD RMPREAD instruction. Improved EVEX decoding, including the new U bit. Fixed ENTER & LEAVE operands.
2024-09-16 09:23:54 +00:00
VRNDSCALENEPBF16 ; Vfv{K}{z},Wfv|B16,Ib ; ; evex m:3 p:3 l:x w:0 0x08 /r ib ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:W|R|R|R
BDDISASM v2.1.0 release - please consult the CHANGELOG for details about the modifications.
2024-02-20 11:39:22 +00:00
VRNDSCALEPD ; Vfv{K}{z},Wfv|B64{sae},Ib ; ; evex m:3 p:1 l:x w:1 0x09 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R
VRNDSCALESH ; Vdq{K}{z},Hdq,Wsh{sae},Ib ; ; evex m:3 p:0 l:i w:0 0x0A /r ib ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R|R
VRNDSCALESS ; Vdq{K}{z},Hdq,Wss{sae},Ib ; ; evex m:3 p:1 l:i w:0 0x0A /r ib ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R
VRNDSCALESD ; Vdq{K}{z},Hdq,Wsd{sae},Ib ; ; evex m:3 p:1 l:i w:1 0x0B /r ib ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R
VPALIGNR ; Vfv{K}{z},Hfv,Wfv,Ib ; ; evex m:3 p:1 l:x w:i 0x0F /r ib ; s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:W|R|R|R|R
Initial commit.
2020-07-21 08:19:18 +00:00
# 0x10 - 0x1F
BDDISASM v2.1.0 release - please consult the CHANGELOG for details about the modifications.
2024-02-20 11:39:22 +00:00
VPEXTRB ; Mb,Vdq,Ib ; ; evex m:3 p:1 l:0 w:i 0x14 /r:mem ib ; s:AVX512BW, t:AVX512, l:t1s8, e:E9NF, w:W|R|R
VPEXTRB ; Ry,Vdq,Ib ; ; evex m:3 p:1 l:0 w:i 0x14 /r:reg ib ; s:AVX512BW, t:AVX512, l:t1s8, e:E9NF, w:W|R|R, a:D64
VPEXTRW ; Mw,Vdq,Ib ; ; evex m:3 p:1 l:0 w:i 0x15 /r:mem ib ; s:AVX512BW, t:AVX512, l:t1s16, e:E9NF, w:W|R|R
VPEXTRW ; Ry,Vdq,Ib ; ; evex m:3 p:1 l:0 w:i 0x15 /r:reg ib ; s:AVX512BW, t:AVX512, l:t1s16, e:E9NF, w:W|R|R, a:D64
VPEXTRD ; Md,Vdq,Ib ; ; evex m:3 p:1 l:0 w:0 0x16 /r:mem ib ; s:AVX512DQ, t:AVX512, l:t1s, e:E9NF, w:W|R|R, a:IWO64
VPEXTRD ; Ry,Vdq,Ib ; ; evex m:3 p:1 l:0 w:0 0x16 /r:reg ib ; s:AVX512DQ, t:AVX512, l:t1s, e:E9NF, w:W|R|R, a:IWO64|D64
VPEXTRQ ; Mq,Vdq,Ib ; ; evex m:3 p:1 l:0 w:1 0x16 /r:mem ib ; s:AVX512DQ, t:AVX512, l:t1s, e:E9NF, w:W|R|R, a:IWO64
VPEXTRQ ; Ry,Vdq,Ib ; ; evex m:3 p:1 l:0 w:1 0x16 /r:reg ib ; s:AVX512DQ, t:AVX512, l:t1s, e:E9NF, w:W|R|R, a:IWO64
VEXTRACTPS ; Md,Vdq,Ib ; ; evex m:3 p:1 l:0 w:i 0x17 /r:mem ib ; s:AVX512F, t:AVX512, l:t1s, e:E9NF, w:W|R|R
VEXTRACTPS ; Ry,Vdq,Ib ; ; evex m:3 p:1 l:0 w:i 0x17 /r:reg ib ; s:AVX512F, t:AVX512, l:t1s, e:E9NF, w:W|R|R
VINSERTF32X4 ; Vuv{K}{z},Huv,Wdq,Ib ; ; evex m:3 p:1 l:x w:0 0x18 /r ib ; s:AVX512F, t:AVX512, a:NOL0, l:t4, e:E6NF, w:W|R|R|R|R
VINSERTF64X2 ; Vuv{K}{z},Huv,Wdq,Ib ; ; evex m:3 p:1 l:x w:1 0x18 /r ib ; s:AVX512DQ, t:AVX512, a:NOL0, l:t2, e:E6NF, w:W|R|R|R|R
VEXTRACTF32X4 ; Wdq{K}{z},Vuv,Ib ; ; evex m:3 p:1 l:x w:0 0x19 /r ib ; s:AVX512F, t:AVX512, a:NOL0, l:t4, e:E6NF, w:W|R|R|R
VEXTRACTF64X2 ; Wdq{K}{z},Vuv,Ib ; ; evex m:3 p:1 l:x w:1 0x19 /r ib ; s:AVX512DQ, t:AVX512, a:NOL0, l:t2, e:E6NF, w:W|R|R|R
VINSERTF32X8 ; Voq{K}{z},Hoq,Wqq,Ib ; ; evex m:3 p:1 l:2 w:0 0x1A /r ib ; s:AVX512DQ, t:AVX512, l:t8, e:E6NF, w:W|R|R|R|R
VINSERTF64X4 ; Voq{K}{z},Hoq,Wqq,Ib ; ; evex m:3 p:1 l:2 w:1 0x1A /r ib ; s:AVX512F, t:AVX512, l:t4, e:E6NF, w:W|R|R|R|R
VEXTRACTF32X8 ; Wqq{K}{z},Voq,Ib ; ; evex m:3 p:1 l:2 w:0 0x1B /r ib ; s:AVX512DQ, t:AVX512, l:t8, e:E6NF, w:W|R|R|R
VEXTRACTF64X4 ; Wqq{K}{z},Voq,Ib ; ; evex m:3 p:1 l:2 w:1 0x1B /r ib ; s:AVX512F, t:AVX512, l:t4, e:E6NF, w:W|R|R|R
VCVTPS2PH ; Whv{K}{z},Vfv{sae},Ib ; ; evex m:3 p:1 l:x w:0 0x1D /r ib ; s:AVX512F, t:CONVERT, l:hvm, e:E11, w:W|R|R|R
VPCMPUD ; rKq{K},Hfv,Wfv|B32,Ib ; ; evex m:3 p:1 l:x w:0 0x1E /r ib ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R|R
VPCMPUQ ; rKq{K},Hfv,Wfv|B64,Ib ; ; evex m:3 p:1 l:x w:1 0x1E /r ib ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R|R
VPCMPD ; rKq{K},Hfv,Wfv|B32,Ib ; ; evex m:3 p:1 l:x w:0 0x1F /r ib ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R|R
VPCMPQ ; rKq{K},Hfv,Wfv|B64,Ib ; ; evex m:3 p:1 l:x w:1 0x1F /r ib ; s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R|R
Initial commit.
2020-07-21 08:19:18 +00:00
# 0x20 - 0x2F
BDDISASM v2.1.0 release - please consult the CHANGELOG for details about the modifications.
2024-02-20 11:39:22 +00:00
VPINSRB ; Vdq,Hdq,Mb,Ib ; ; evex m:3 p:1 l:0 w:i 0x20 /r:mem ib ; s:AVX512BW, t:AVX512, l:t1s8, e:E9NF, w:W|R|R|R
VPINSRB ; Vdq,Hdq,Rd,Ib ; ; evex m:3 p:1 l:0 w:i 0x20 /r:reg ib ; s:AVX512BW, t:AVX512, l:t1s8, e:E9NF, w:W|R|R|R
VINSERTPS ; Vdq,Hdq,Md,Ib ; ; evex m:3 p:1 l:0 w:i 0x21 /r:mem ib ; s:AVX512F, t:AVX512, l:t1s, e:E9NF, w:W|R|R|R
VINSERTPS ; Vdq,Hdq,Udq,Ib ; ; evex m:3 p:1 l:0 w:i 0x21 /r:reg ib ; s:AVX512F, t:AVX512, l:t1s, e:E9NF, w:W|R|R|R
VPINSRD ; Vdq,Hdq,Ed,Ib ; ; evex m:3 p:1 l:0 w:0 0x22 /r ib ; s:AVX512DQ, t:AVX512, l:t1s, e:E9NF, w:W|R|R|R, a:IWO64
VPINSRQ ; Vdq,Hdq,Eq,Ib ; ; evex m:3 p:1 l:0 w:1 0x22 /r ib ; s:AVX512DQ, t:AVX512, l:t1s, e:E9NF, w:W|R|R|R, a:IWO64
VSHUFF32X4 ; Vuv{K}{z},Huv,Wuv|B32,Ib ; ; evex m:3 p:1 l:x w:0 0x23 /r ib ; s:AVX512F, t:AVX512, a:NOL0, l:fv, e:E4NF, w:W|R|R|R|R
VSHUFF64X2 ; Vuv{K}{z},Huv,Wuv|B64,Ib ; ; evex m:3 p:1 l:x w:1 0x23 /r ib ; s:AVX512F, t:AVX512, a:NOL0, l:fv, e:E4NF, w:W|R|R|R|R
VPTERNLOGD ; Vfv{K}{z},Hfv,Wfv|B32,Ib ; ; evex m:3 p:1 l:x w:0 0x25 /r ib ; s:AVX512F, t:LOGICAL, l:fv, e:E4, w:RW|R|R|R|R
VPTERNLOGQ ; Vfv{K}{z},Hfv,Wfv|B64,Ib ; ; evex m:3 p:1 l:x w:1 0x25 /r ib ; s:AVX512F, t:LOGICAL, l:fv, e:E4, w:RW|R|R|R|R
VGETMANTPH ; Vfv{K}{z},Wfv|B16{sae},Ib ; ; evex m:3 p:0 l:x w:0 0x26 /r ib ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R
VGETMANTPS ; Vfv{K}{z},Wfv|B32{sae},Ib ; ; evex m:3 p:1 l:x w:0 0x26 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R
VGETMANTPD ; Vfv{K}{z},Wfv|B64{sae},Ib ; ; evex m:3 p:1 l:x w:1 0x26 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R
Added support for new Intel AVX 10.2 instructions. Added support for AMD RMPREAD instruction. Improved EVEX decoding, including the new U bit. Fixed ENTER & LEAVE operands.
2024-09-16 09:23:54 +00:00
VGETMANTPBF16 ; Vfv{K}{z},Wfv|B16,Ib ; ; evex m:3 p:3 l:x w:0 0x26 /r ib ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:W|R|R|R
BDDISASM v2.1.0 release - please consult the CHANGELOG for details about the modifications.
2024-02-20 11:39:22 +00:00
VGETMANTSH ; Vdq{K}{z},Hdq,Wsh{sae},Ib ; ; evex m:3 p:0 l:i w:0 0x27 /r ib ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R|R
VGETMANTSS ; Vdq{K}{z},Hdq,Wss{sae},Ib ; ; evex m:3 p:1 l:i w:0 0x27 /r ib ; s:AVX512F, t:AVX512, l:t1s, e:E2, w:W|R|R|R|R
VGETMANTSD ; Vdq{K}{z},Hdq,Wsd{sae},Ib ; ; evex m:3 p:1 l:i w:1 0x27 /r ib ; s:AVX512F, t:AVX512, l:t1s, e:E2, w:W|R|R|R|R
Initial commit.
2020-07-21 08:19:18 +00:00
# 0x30 - 0x3F
BDDISASM v2.1.0 release - please consult the CHANGELOG for details about the modifications.
2024-02-20 11:39:22 +00:00
VINSERTI32X4 ; Vuv{K}{z},Huv,Wdq,Ib ; ; evex m:3 p:1 l:x w:0 0x38 /r ib ; s:AVX512F, t:AVX512, a:NOL0, l:t4, e:E6NF, w:W|R|R|R|R
VINSERTI64X2 ; Vuv{K}{z},Huv,Wdq,Ib ; ; evex m:3 p:1 l:x w:1 0x38 /r ib ; s:AVX512DQ, t:AVX512, a:NOL0, l:t2, e:E6NF, w:W|R|R|R|R
VEXTRACTI32X4 ; Wdq{K}{z},Vuv,Ib ; ; evex m:3 p:1 l:x w:0 0x39 /r ib ; s:AVX512F, t:AVX512, a:NOL0, l:t4, e:E6NF, w:W|R|R|R
VEXTRACTI64X2 ; Wdq{K}{z},Vuv,Ib ; ; evex m:3 p:1 l:x w:1 0x39 /r ib ; s:AVX512DQ, t:AVX512, a:NOL0, l:t2, e:E6NF, w:W|R|R|R
VINSERTI32X8 ; Voq{K}{z},Hoq,Wqq,Ib ; ; evex m:3 p:1 l:2 w:0 0x3A /r ib ; s:AVX512DQ, t:AVX512, l:t8, e:E6NF, w:W|R|R|R|R
VINSERTI64X4 ; Voq{K}{z},Hoq,Wqq,Ib ; ; evex m:3 p:1 l:2 w:1 0x3A /r ib ; s:AVX512F, t:AVX512, l:t4, e:E6NF, w:W|R|R|R|R
VEXTRACTI32X8 ; Wqq{K}{z},Voq,Ib ; ; evex m:3 p:1 l:2 w:0 0x3B /r ib ; s:AVX512DQ, t:AVX512, l:t8, e:E6NF, w:W|R|R|R
VEXTRACTI64X4 ; Wqq{K}{z},Voq,Ib ; ; evex m:3 p:1 l:2 w:1 0x3B /r ib ; s:AVX512F, t:AVX512, l:t4, e:E6NF, w:W|R|R|R
VPCMPUB ; rKq{K},Hfv,Wfv,Ib ; ; evex m:3 p:1 l:x w:0 0x3E /r ib ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R|R
VPCMPUW ; rKq{K},Hfv,Wfv,Ib ; ; evex m:3 p:1 l:x w:1 0x3E /r ib ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R|R
VPCMPB ; rKq{K},Hfv,Wfv,Ib ; ; evex m:3 p:1 l:x w:0 0x3F /r ib ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R|R
VPCMPW ; rKq{K},Hfv,Wfv,Ib ; ; evex m:3 p:1 l:x w:1 0x3F /r ib ; s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R|R
Initial commit.
2020-07-21 08:19:18 +00:00
# 0x40 - 0x4F
BDDISASM v2.1.0 release - please consult the CHANGELOG for details about the modifications.
2024-02-20 11:39:22 +00:00
VDBPSADBW ; Vfv{K}{z},Hfv,Wfv,Ib ; ; evex m:3 p:1 l:x w:0 0x42 /r ib ; s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:W|R|R|R|R
Added support for new Intel AVX 10.2 instructions. Added support for AMD RMPREAD instruction. Improved EVEX decoding, including the new U bit. Fixed ENTER & LEAVE operands.
2024-09-16 09:23:54 +00:00
VMPSADBW ; Vfv{K}{z},Hfv,Wfv,Ib ; ; evex m:3 p:2 l:x w:0 0x42 /r ib ; s:AVX102, t:AVX10INT, l:fvm, e:E4NF, w:W|R|R|R|R
BDDISASM v2.1.0 release - please consult the CHANGELOG for details about the modifications.
2024-02-20 11:39:22 +00:00
VSHUFI32X4 ; Vuv{K}{z},Huv,Wuv|B32,Ib ; ; evex m:3 p:1 l:x w:0 0x43 /r ib ; s:AVX512F, t:AVX512, a:NOL0, l:fv, e:E4NF, w:W|R|R|R|R
VSHUFI64X2 ; Vuv{K}{z},Huv,Wuv|B64,Ib ; ; evex m:3 p:1 l:x w:1 0x43 /r ib ; s:AVX512F, t:AVX512, a:NOL0, l:fv, e:E4NF, w:W|R|R|R|R
VPCLMULQDQ ; Vfv,Hfv,Wfv,Ib ; ; evex m:3 p:1 l:x w:i 0x44 /r ib ; s:VPCLMULQDQ, t:VPCLMULQDQ, l:fvm, e:E4NF, w:W|R|R|R
Initial commit.
2020-07-21 08:19:18 +00:00
# 0x50 - 0x5F
BDDISASM v2.1.0 release - please consult the CHANGELOG for details about the modifications.
2024-02-20 11:39:22 +00:00
VRANGEPS ; Vfv{K}{z},Hfv,Wfv|B32{sae},Ib ; ; evex m:3 p:1 l:x w:0 0x50 /r ib ; s:AVX512DQ, t:AVX512, l:fv, e:E2, w:W|R|R|R|R
VRANGEPD ; Vfv{K}{z},Hfv,Wfv|B64{sae},Ib ; ; evex m:3 p:1 l:x w:1 0x50 /r ib ; s:AVX512DQ, t:AVX512, l:fv, e:E2, w:W|R|R|R|R
VRANGESS ; Vdq{K}{z},Hdq,Wss{sae},Ib ; ; evex m:3 p:1 l:i w:0 0x51 /r ib ; s:AVX512DQ, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R
VRANGESD ; Vdq{K}{z},Hdq,Wsd{sae},Ib ; ; evex m:3 p:1 l:i w:1 0x51 /r ib ; s:AVX512DQ, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R
Added support for new Intel AVX 10.2 instructions. Added support for AMD RMPREAD instruction. Improved EVEX decoding, including the new U bit. Fixed ENTER & LEAVE operands.
2024-09-16 09:23:54 +00:00
VMINMAXPH ; Vfv{K}{z},Hfv,Wfv|B16{sae},Ib ; ; evex m:3 p:0 l:x w:0 0x52 /r ib ; s:AVX102, t:AVX10MINMAX, l:fv, e:E2, w:W|R|R|R|R
VMINMAXPS ; Vfv{K}{z},Hfv,Wfv|B32{sae},Ib ; ; evex m:3 p:1 l:x w:0 0x52 /r ib ; s:AVX102, t:AVX10MINMAX, l:fv, e:E2, w:W|R|R|R|R
VMINMAXPD ; Vfv{K}{z},Hfv,Wfv|B64{sae},Ib ; ; evex m:3 p:1 l:x w:1 0x52 /r ib ; s:AVX102, t:AVX10MINMAX, l:fv, e:E2, w:W|R|R|R|R
VMINMAXNEPBF16 ; Vfv{K}{z},Hfv,Wfv|B16,Ib ; ; evex m:3 p:3 l:x w:0 0x52 /r ib ; s:AVX102, t:AVX10MINMAX, l:fv, e:E4, w:W|R|R|R|R
VMINMAXSH ; Vdq{K}{z},Hdq,Wsh{sae},Ib ; ; evex m:3 p:0 l:i w:0 0x53 /r ib ; s:AVX102, t:AVX10MINMAX, l:t1s, e:E3, w:W|R|R|R|R
VMINMAXSS ; Vdq{K}{z},Hdq,Wss{sae},Ib ; ; evex m:3 p:1 l:i w:0 0x53 /r ib ; s:AVX102, t:AVX10MINMAX, l:t1s, e:E3, w:W|R|R|R|R
VMINMAXSD ; Vdq{K}{z},Hdq,Wsd{sae},Ib ; ; evex m:3 p:1 l:i w:1 0x53 /r ib ; s:AVX102, t:AVX10MINMAX, l:t1s, e:E3, w:W|R|R|R|R
BDDISASM v2.1.0 release - please consult the CHANGELOG for details about the modifications.
2024-02-20 11:39:22 +00:00
VFIXUPIMMPS ; Vfv{K}{z},Hfv,Wfv|B32{sae},Ib ; ; evex m:3 p:1 l:x w:0 0x54 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E2, w:RW|R|R|R|R
VFIXUPIMMPD ; Vfv{K}{z},Hfv,Wfv|B64{sae},Ib ; ; evex m:3 p:1 l:x w:1 0x54 /r ib ; s:AVX512F, t:AVX512, l:fv, e:E2, w:RW|R|R|R|R
VFIXUPIMMSS ; Vdq{K}{z},Hdq,Wss{sae},Ib ; ; evex m:3 p:1 l:i w:0 0x55 /r ib ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:RW|R|R|R|R
VFIXUPIMMSD ; Vdq{K}{z},Hdq,Wsd{sae},Ib ; ; evex m:3 p:1 l:i w:1 0x55 /r ib ; s:AVX512F, t:AVX512, l:t1s, e:E3, w:RW|R|R|R|R
VREDUCEPH ; Vfv{K}{z},Wfv|B16{sae},Ib ; ; evex m:3 p:0 l:x w:0 0x56 /r ib ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R
VREDUCEPS ; Vfv{K}{z},Wfv|B32{sae},Ib ; ; evex m:3 p:1 l:x w:0 0x56 /r ib ; s:AVX512DQ, t:AVX512, l:fv, e:E2, w:W|R|R|R
VREDUCEPD ; Vfv{K}{z},Wfv|B64{sae},Ib ; ; evex m:3 p:1 l:x w:1 0x56 /r ib ; s:AVX512DQ, t:AVX512, l:fv, e:E2, w:W|R|R|R
Added support for new Intel AVX 10.2 instructions. Added support for AMD RMPREAD instruction. Improved EVEX decoding, including the new U bit. Fixed ENTER & LEAVE operands.
2024-09-16 09:23:54 +00:00
VREDUCENEPBF16 ; Vfv{K}{z},Wfv|B16,Ib ; ; evex m:3 p:3 l:x w:0 0x56 /r ib ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:W|R|R|R
BDDISASM v2.1.0 release - please consult the CHANGELOG for details about the modifications.
2024-02-20 11:39:22 +00:00
VREDUCESH ; Vdq{K}{z},Hdq,Wsh{sae},Ib ; ; evex m:3 p:0 l:i w:0 0x57 /r ib ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R|R
VREDUCESS ; Vdq{K}{z},Hdq,Wss{sae},Ib ; ; evex m:3 p:1 l:i w:0 0x57 /r ib ; s:AVX512DQ, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R
VREDUCESD ; Vdq{K}{z},Hdq,Wsd{sae},Ib ; ; evex m:3 p:1 l:i w:1 0x57 /r ib ; s:AVX512DQ, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R
Initial commit.
2020-07-21 08:19:18 +00:00
# 0x60 - 0x6F
BDDISASM v2.1.0 release - please consult the CHANGELOG for details about the modifications.
2024-02-20 11:39:22 +00:00
VFPCLASSPH ; rKq{K},Wfv|B16,Ib ; ; evex m:3 p:0 l:x w:0 0x66 /r ib ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E4, w:W|R|R|R
VFPCLASSPS ; rKq{K},Wfv|B32,Ib ; ; evex m:3 p:1 l:x w:0 0x66 /r ib ; s:AVX512DQ, t:AVX512, l:fv, e:E4, w:W|R|R|R
VFPCLASSPD ; rKq{K},Wfv|B64,Ib ; ; evex m:3 p:1 l:x w:1 0x66 /r ib ; s:AVX512DQ, t:AVX512, l:fv, e:E4, w:W|R|R|R
Added support for new Intel AVX 10.2 instructions. Added support for AMD RMPREAD instruction. Improved EVEX decoding, including the new U bit. Fixed ENTER & LEAVE operands.
2024-09-16 09:23:54 +00:00
VFPCLASSPBF16 ; rKq{K},Wfv|B16,Ib ; ; evex m:3 p:3 l:x w:0 0x66 /r ib ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:W|R|R|R
BDDISASM v2.1.0 release - please consult the CHANGELOG for details about the modifications.
2024-02-20 11:39:22 +00:00
VFPCLASSSH ; rKq{K},Wsh,Ib ; ; evex m:3 p:0 l:i w:0 0x67 /r ib ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E10, w:W|R|R|R
VFPCLASSSS ; rKq{K},Wss,Ib ; ; evex m:3 p:1 l:i w:0 0x67 /r ib ; s:AVX512DQ, t:AVX512, l:t1s, e:E6, w:W|R|R|R
VFPCLASSSD ; rKq{K},Wsd,Ib ; ; evex m:3 p:1 l:i w:1 0x67 /r ib ; s:AVX512DQ, t:AVX512, l:t1s, e:E6, w:W|R|R|R
Initial commit.
2020-07-21 08:19:18 +00:00
# 0x70 - 0x7F
BDDISASM v2.1.0 release - please consult the CHANGELOG for details about the modifications.
2024-02-20 11:39:22 +00:00
VPSHLDW ; Vfv{K}{z},Hfv,Wfv,Ib ; ; evex m:3 p:1 l:x w:1 0x70 /r ib ; s:AVX512VBMI2, t:AVX512VBMI, l:fvm, e:E4, w:RW|R|R|R|R
VPSHLDD ; Vfv{K}{z},Hfv,Wfv|B32,Ib ; ; evex m:3 p:1 l:x w:0 0x71 /r ib ; s:AVX512VBMI2, t:AVX512VBMI, l:fv, e:E4, w:RW|R|R|R|R
VPSHLDQ ; Vfv{K}{z},Hfv,Wfv|B64,Ib ; ; evex m:3 p:1 l:x w:1 0x71 /r ib ; s:AVX512VBMI2, t:AVX512VBMI, l:fv, e:E4, w:RW|R|R|R|R
VPSHRDW ; Vfv{K}{z},Hfv,Wfv,Ib ; ; evex m:3 p:1 l:x w:1 0x72 /r ib ; s:AVX512VBMI2, t:AVX512VBMI, l:fvm, e:E4, w:RW|R|R|R|R
VPSHRDD ; Vfv{K}{z},Hfv,Wfv|B32,Ib ; ; evex m:3 p:1 l:x w:0 0x73 /r ib ; s:AVX512VBMI2, t:AVX512VBMI, l:fv, e:E4, w:RW|R|R|R|R
VPSHRDQ ; Vfv{K}{z},Hfv,Wfv|B64,Ib ; ; evex m:3 p:1 l:x w:1 0x73 /r ib ; s:AVX512VBMI2, t:AVX512VBMI, l:fv, e:E4, w:RW|R|R|R|R
Initial commit.
2020-07-21 08:19:18 +00:00
# 0x80 - 0x8F
# 0x90 - 0x9F
# 0xA0 - 0xAF
# 0xB0 - 0xBF
# 0xC0 - 0xCF
BDDISASM v2.1.0 release - please consult the CHANGELOG for details about the modifications.
2024-02-20 11:39:22 +00:00
VCMPPH ; rK{K},Hfv,Wfv|B16{sae},Ib ; ; evex m:3 p:0 l:x w:0 0xC2 /r ib ; s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R|R
VCMPSH ; rK{K},Hfv,Wsh{sae},Ib ; ; evex m:3 p:2 l:i w:0 0xC2 /r ib ; s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R|R
Added support for new Intel AVX 10.2 instructions. Added support for AMD RMPREAD instruction. Improved EVEX decoding, including the new U bit. Fixed ENTER & LEAVE operands.
2024-09-16 09:23:54 +00:00
VCMPPBF16 ; rK{K},Hfv,Wfv|B16,Ib ; ; evex m:3 p:3 l:x w:0 0xC2 /r ib ; s:AVX102, t:AVX10BF16, l:fv, e:E4, w:W|R|R|R|R
Multiple changes - Add support for AVX512-FP16 instructions, as per https://software.intel.com/content/www/us/en/develop/download/intel-avx512-fp16-architecture-specification.html - Bug fix: zeroing with no masking is not supported, so return an error if we encounter such encodings - Bug fix: ignore VEX/EVEX.W field outside 64 bit mode for some instructions - Several other minor fixes and improvements
2021-07-08 09:40:39 +00:00
BDDISASM v2.1.0 release - please consult the CHANGELOG for details about the modifications.
2024-02-20 11:39:22 +00:00
VGF2P8AFFINEQB ; Vfv{K}{z},Hfv,Wfv|B64,Ib ; ; evex m:3 p:1 l:x w:1 0xCE /r ib ; s:GFNI, t:GFNI, l:fv, e:E4NF, w:W|R|R|R|R
VGF2P8AFFINEINVQB ; Vfv{K}{z},Hfv,Wfv|B64,Ib ; ; evex m:3 p:1 l:x w:1 0xCF /r ib ; s:GFNI, t:GFNI, l:fv, e:E4NF, w:W|R|R|R|R
Initial commit.
2020-07-21 08:19:18 +00:00
# 0xD0 - 0xDF
# 0xE0 - 0xEF
# 0xF0 - 0xFF
BDDISASM v2.1.0 release - please consult the CHANGELOG for details about the modifications.
2024-02-20 11:39:22 +00:00
# APX - RORX
RORX ; Gy,Ey,Ib ; ; evex m:3 p:3 l:0 nd:0 nf:0 0xF0 /r ib ; s:APX_F, t:BMI2, w:W|R|R, e:APX_EVEX_BMI, v:vex
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