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bddisasm/isagenerator/instructions/table_evex3.dat

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Typo fixes in the instruction tables. Added a reference to the git repo in the documentation.
2020-07-21 13:38:09 +00:00
# Mnemonic Explicit Operands Implicit Encoding Flags, Prefixes, Set, Category, Class, RW map, Additional ops
Initial commit.
2020-07-21 08:19:18 +00:00
#------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
# 0x00 - 0x0F
Improved comments & improved vector length specifiers.
2023-02-04 10:02:05 +00:00
VPERMQ Vuv{K}{z},Wuv|B64,Ib nil [evex m:3 p:1 l:x w:1 0x00 /r ib] s:AVX512F, t:AVX512, a:NOL0, l:fv, e:E4NF, w:W|R|R|R
VPERMPD Vuv{K}{z},Wuv|B64,Ib nil [evex m:3 p:1 l:x w:1 0x01 /r ib] s:AVX512F, t:AVX512, a:NOL0, l:fv, e:E4NF, w:W|R|R|R
VALIGND Vfv{K}{z},Hfv,Wfv|B32,Ib nil [evex m:3 p:1 l:x w:0 0x03 /r ib] s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R|R
VALIGNQ Vfv{K}{z},Hfv,Wfv|B64,Ib nil [evex m:3 p:1 l:x w:1 0x03 /r ib] s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R|R
VPERMILPS Vfv{K}{z},Wfv|B32,Ib nil [evex m:3 p:1 l:x w:0 0x04 /r ib] s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R
VPERMILPD Vfv{K}{z},Wfv|B64,Ib nil [evex m:3 p:1 l:x w:1 0x05 /r ib] s:AVX512F, t:AVX512, l:fv, e:E4NF, w:W|R|R|R
VRNDSCALEPH Vfv{K}{z},Wfv|B16{sae},Ib nil [evex m:3 p:0 l:x w:0 0x08 /r ib] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R
VRNDSCALEPS Vfv{K}{z},Wfv|B32{sae},Ib nil [evex m:3 p:1 l:x w:0 0x08 /r ib] s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R
VRNDSCALEPD Vfv{K}{z},Wfv|B64{sae},Ib nil [evex m:3 p:1 l:x w:1 0x09 /r ib] s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R
Multiple changes - Add support for AVX512-FP16 instructions, as per https://software.intel.com/content/www/us/en/develop/download/intel-avx512-fp16-architecture-specification.html - Bug fix: zeroing with no masking is not supported, so return an error if we encounter such encodings - Bug fix: ignore VEX/EVEX.W field outside 64 bit mode for some instructions - Several other minor fixes and improvements
2021-07-08 09:40:39 +00:00
VRNDSCALESH Vdq{K}{z},Hdq,Wsh{sae},Ib nil [evex m:3 p:0 l:i w:0 0x0A /r ib] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R|R
Initial commit.
2020-07-21 08:19:18 +00:00
VRNDSCALESS Vdq{K}{z},Hdq,Wss{sae},Ib nil [evex m:3 p:1 l:i w:0 0x0A /r ib] s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R
VRNDSCALESD Vdq{K}{z},Hdq,Wsd{sae},Ib nil [evex m:3 p:1 l:i w:1 0x0B /r ib] s:AVX512F, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R
Improved comments & improved vector length specifiers.
2023-02-04 10:02:05 +00:00
VPALIGNR Vfv{K}{z},Hfv,Wfv,Ib nil [evex m:3 p:1 l:x w:i 0x0F /r ib] s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:W|R|R|R|R
Initial commit.
2020-07-21 08:19:18 +00:00
# 0x10 - 0x1F
Fixed RET with immediate - the immediate is not sign-extended. Fixed VEX decoding in 32 bit mode - vex.vvvv bit 3 is simply ignored. Fixed several FMA instructions decoding (L/W flag should be ignored). Print the 64 bit immediate value in disassembly, instead of the raw immediate (note that the operand always contains the sign-extended, full immediate). XBEGIN always uses 32/64 bit RIP size (0x66 does not affect its size). Decode WBINVD even if it's preceded by 0x66/0xF2 prefixes. Several mnemonic fixes (FXSAVE64, FXRSTOR64, PUSHA/PUSHAD...). Properly decode VPERMIL2* instructions. Fixed SSE register decoding when it is encoded in immediate. Decode SCATTER instructions even though they use the VSIB index as source. Some disp8 fixes (t1s -> t1s8/t1s16). SYSCALL/SYSRET are decoded and executed in 32 bit compat modem, even though SDM states they are invalid. RDPID uses 32/64 bit reg size, never 16. Various other minor tweaks & fixes. Re-generated the test files, and added some more, new tests.
2020-07-23 11:08:01 +00:00
VPEXTRB Mb,Vdq,Ib nil [evex m:3 p:1 l:0 w:i 0x14 /r:mem ib] s:AVX512BW, t:AVX512, l:t1s8, e:E9NF, w:W|R|R
Added support for new Intel instructions, per Intel ISA extensions document #319433-046 (September 2022): PREFETCHITI, RAO-INT, CMPCCXADD, WRMSRNS, MSRLIST, AMX-FP16, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8. Multiple minor fixes to existing instructions. Moved x86 decoding tests in a separate directory & improved the test script.
2022-10-04 09:22:59 +00:00
VPEXTRB Ry,Vdq,Ib nil [evex m:3 p:1 l:0 w:i 0x14 /r:reg ib] s:AVX512BW, t:AVX512, l:t1s8, e:E9NF, w:W|R|R, a:D64
Fixed RET with immediate - the immediate is not sign-extended. Fixed VEX decoding in 32 bit mode - vex.vvvv bit 3 is simply ignored. Fixed several FMA instructions decoding (L/W flag should be ignored). Print the 64 bit immediate value in disassembly, instead of the raw immediate (note that the operand always contains the sign-extended, full immediate). XBEGIN always uses 32/64 bit RIP size (0x66 does not affect its size). Decode WBINVD even if it's preceded by 0x66/0xF2 prefixes. Several mnemonic fixes (FXSAVE64, FXRSTOR64, PUSHA/PUSHAD...). Properly decode VPERMIL2* instructions. Fixed SSE register decoding when it is encoded in immediate. Decode SCATTER instructions even though they use the VSIB index as source. Some disp8 fixes (t1s -> t1s8/t1s16). SYSCALL/SYSRET are decoded and executed in 32 bit compat modem, even though SDM states they are invalid. RDPID uses 32/64 bit reg size, never 16. Various other minor tweaks & fixes. Re-generated the test files, and added some more, new tests.
2020-07-23 11:08:01 +00:00
VPEXTRW Mw,Vdq,Ib nil [evex m:3 p:1 l:0 w:i 0x15 /r:mem ib] s:AVX512BW, t:AVX512, l:t1s16, e:E9NF, w:W|R|R
Added support for new Intel instructions, per Intel ISA extensions document #319433-046 (September 2022): PREFETCHITI, RAO-INT, CMPCCXADD, WRMSRNS, MSRLIST, AMX-FP16, AVX-IFMA, AVX-NE-CONVERT, AVX-VNNI-INT8. Multiple minor fixes to existing instructions. Moved x86 decoding tests in a separate directory & improved the test script.
2022-10-04 09:22:59 +00:00
VPEXTRW Ry,Vdq,Ib nil [evex m:3 p:1 l:0 w:i 0x15 /r:reg ib] s:AVX512BW, t:AVX512, l:t1s16, e:E9NF, w:W|R|R, a:D64
VPEXTRD Md,Vdq,Ib nil [evex m:3 p:1 l:0 w:0 0x16 /r:mem ib] s:AVX512DQ, t:AVX512, l:t1s, e:E9NF, w:W|R|R, a:IWO64
VPEXTRD Ry,Vdq,Ib nil [evex m:3 p:1 l:0 w:0 0x16 /r:reg ib] s:AVX512DQ, t:AVX512, l:t1s, e:E9NF, w:W|R|R, a:IWO64|D64
VPEXTRQ Mq,Vdq,Ib nil [evex m:3 p:1 l:0 w:1 0x16 /r:mem ib] s:AVX512DQ, t:AVX512, l:t1s, e:E9NF, w:W|R|R, a:IWO64
VPEXTRQ Ry,Vdq,Ib nil [evex m:3 p:1 l:0 w:1 0x16 /r:reg ib] s:AVX512DQ, t:AVX512, l:t1s, e:E9NF, w:W|R|R, a:IWO64
Initial commit.
2020-07-21 08:19:18 +00:00
VEXTRACTPS Md,Vdq,Ib nil [evex m:3 p:1 l:0 w:i 0x17 /r:mem ib] s:AVX512F, t:AVX512, l:t1s, e:E9NF, w:W|R|R
VEXTRACTPS Ry,Vdq,Ib nil [evex m:3 p:1 l:0 w:i 0x17 /r:reg ib] s:AVX512F, t:AVX512, l:t1s, e:E9NF, w:W|R|R
Improved comments & improved vector length specifiers.
2023-02-04 10:02:05 +00:00
VINSERTF32X4 Vuv{K}{z},Huv,Wdq,Ib nil [evex m:3 p:1 l:x w:0 0x18 /r ib] s:AVX512F, t:AVX512, a:NOL0, l:t4, e:E6NF, w:W|R|R|R|R
VINSERTF64X2 Vuv{K}{z},Huv,Wdq,Ib nil [evex m:3 p:1 l:x w:1 0x18 /r ib] s:AVX512DQ, t:AVX512, a:NOL0, l:t2, e:E6NF, w:W|R|R|R|R
VEXTRACTF32X4 Wdq{K}{z},Vuv,Ib nil [evex m:3 p:1 l:x w:0 0x19 /r ib] s:AVX512F, t:AVX512, a:NOL0, l:t4, e:E6NF, w:W|R|R|R
VEXTRACTF64X2 Wdq{K}{z},Vuv,Ib nil [evex m:3 p:1 l:x w:1 0x19 /r ib] s:AVX512DQ, t:AVX512, a:NOL0, l:t2, e:E6NF, w:W|R|R|R
Initial commit.
2020-07-21 08:19:18 +00:00
VINSERTF32X8 Voq{K}{z},Hoq,Wqq,Ib nil [evex m:3 p:1 l:2 w:0 0x1A /r ib] s:AVX512DQ, t:AVX512, l:t8, e:E6NF, w:W|R|R|R|R
VINSERTF64X4 Voq{K}{z},Hoq,Wqq,Ib nil [evex m:3 p:1 l:2 w:1 0x1A /r ib] s:AVX512F, t:AVX512, l:t4, e:E6NF, w:W|R|R|R|R
VEXTRACTF32X8 Wqq{K}{z},Voq,Ib nil [evex m:3 p:1 l:2 w:0 0x1B /r ib] s:AVX512DQ, t:AVX512, l:t8, e:E6NF, w:W|R|R|R
VEXTRACTF64X4 Wqq{K}{z},Voq,Ib nil [evex m:3 p:1 l:2 w:1 0x1B /r ib] s:AVX512F, t:AVX512, l:t4, e:E6NF, w:W|R|R|R
Improved comments & improved vector length specifiers.
2023-02-04 10:02:05 +00:00
VCVTPS2PH Whv{K}{z},Vfv{sae},Ib nil [evex m:3 p:1 l:x w:0 0x1D /r ib] s:AVX512F, t:CONVERT, l:hvm, e:E11, w:W|R|R|R
VPCMPUD rKq{K},Hfv,Wfv|B32,Ib nil [evex m:3 p:1 l:x w:0 0x1E /r ib] s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R|R
VPCMPUQ rKq{K},Hfv,Wfv|B64,Ib nil [evex m:3 p:1 l:x w:1 0x1E /r ib] s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R|R
VPCMPD rKq{K},Hfv,Wfv|B32,Ib nil [evex m:3 p:1 l:x w:0 0x1F /r ib] s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R|R
VPCMPQ rKq{K},Hfv,Wfv|B64,Ib nil [evex m:3 p:1 l:x w:1 0x1F /r ib] s:AVX512F, t:AVX512, l:fv, e:E4, w:W|R|R|R|R
Initial commit.
2020-07-21 08:19:18 +00:00
# 0x20 - 0x2F
Fixed RET with immediate - the immediate is not sign-extended. Fixed VEX decoding in 32 bit mode - vex.vvvv bit 3 is simply ignored. Fixed several FMA instructions decoding (L/W flag should be ignored). Print the 64 bit immediate value in disassembly, instead of the raw immediate (note that the operand always contains the sign-extended, full immediate). XBEGIN always uses 32/64 bit RIP size (0x66 does not affect its size). Decode WBINVD even if it's preceded by 0x66/0xF2 prefixes. Several mnemonic fixes (FXSAVE64, FXRSTOR64, PUSHA/PUSHAD...). Properly decode VPERMIL2* instructions. Fixed SSE register decoding when it is encoded in immediate. Decode SCATTER instructions even though they use the VSIB index as source. Some disp8 fixes (t1s -> t1s8/t1s16). SYSCALL/SYSRET are decoded and executed in 32 bit compat modem, even though SDM states they are invalid. RDPID uses 32/64 bit reg size, never 16. Various other minor tweaks & fixes. Re-generated the test files, and added some more, new tests.
2020-07-23 11:08:01 +00:00
VPINSRB Vdq,Hdq,Mb,Ib nil [evex m:3 p:1 l:0 w:i 0x20 /r:mem ib] s:AVX512BW, t:AVX512, l:t1s8, e:E9NF, w:W|R|R|R
VPINSRB Vdq,Hdq,Rd,Ib nil [evex m:3 p:1 l:0 w:i 0x20 /r:reg ib] s:AVX512BW, t:AVX512, l:t1s8, e:E9NF, w:W|R|R|R
Initial commit.
2020-07-21 08:19:18 +00:00
VINSERTPS Vdq,Hdq,Md,Ib nil [evex m:3 p:1 l:0 w:i 0x21 /r:mem ib] s:AVX512F, t:AVX512, l:t1s, e:E9NF, w:W|R|R|R
VINSERTPS Vdq,Hdq,Udq,Ib nil [evex m:3 p:1 l:0 w:i 0x21 /r:reg ib] s:AVX512F, t:AVX512, l:t1s, e:E9NF, w:W|R|R|R
Multiple changes - Add support for AVX512-FP16 instructions, as per https://software.intel.com/content/www/us/en/develop/download/intel-avx512-fp16-architecture-specification.html - Bug fix: zeroing with no masking is not supported, so return an error if we encounter such encodings - Bug fix: ignore VEX/EVEX.W field outside 64 bit mode for some instructions - Several other minor fixes and improvements
2021-07-08 09:40:39 +00:00
VPINSRD Vdq,Hdq,Ed,Ib nil [evex m:3 p:1 l:0 w:0 0x22 /r ib] s:AVX512DQ, t:AVX512, l:t1s, e:E9NF, w:W|R|R|R, a:IWO64
VPINSRQ Vdq,Hdq,Eq,Ib nil [evex m:3 p:1 l:0 w:1 0x22 /r ib] s:AVX512DQ, t:AVX512, l:t1s, e:E9NF, w:W|R|R|R, a:IWO64
Improved comments & improved vector length specifiers.
2023-02-04 10:02:05 +00:00
VSHUFF32X4 Vuv{K}{z},Huv,Wuv|B32,Ib nil [evex m:3 p:1 l:x w:0 0x23 /r ib] s:AVX512F, t:AVX512, a:NOL0, l:fv, e:E4NF, w:W|R|R|R|R
VSHUFF64X2 Vuv{K}{z},Huv,Wuv|B64,Ib nil [evex m:3 p:1 l:x w:1 0x23 /r ib] s:AVX512F, t:AVX512, a:NOL0, l:fv, e:E4NF, w:W|R|R|R|R
VPTERNLOGD Vfv{K}{z},Hfv,Wfv|B32,Ib nil [evex m:3 p:1 l:x w:0 0x25 /r ib] s:AVX512F, t:LOGICAL, l:fv, e:E4, w:RW|R|R|R|R
VPTERNLOGQ Vfv{K}{z},Hfv,Wfv|B64,Ib nil [evex m:3 p:1 l:x w:1 0x25 /r ib] s:AVX512F, t:LOGICAL, l:fv, e:E4, w:RW|R|R|R|R
VGETMANTPH Vfv{K}{z},Wfv|B16{sae},Ib nil [evex m:3 p:0 l:x w:0 0x26 /r ib] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R
VGETMANTPS Vfv{K}{z},Wfv|B32{sae},Ib nil [evex m:3 p:1 l:x w:0 0x26 /r ib] s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R
VGETMANTPD Vfv{K}{z},Wfv|B64{sae},Ib nil [evex m:3 p:1 l:x w:1 0x26 /r ib] s:AVX512F, t:AVX512, l:fv, e:E2, w:W|R|R|R
Multiple changes - Add support for AVX512-FP16 instructions, as per https://software.intel.com/content/www/us/en/develop/download/intel-avx512-fp16-architecture-specification.html - Bug fix: zeroing with no masking is not supported, so return an error if we encounter such encodings - Bug fix: ignore VEX/EVEX.W field outside 64 bit mode for some instructions - Several other minor fixes and improvements
2021-07-08 09:40:39 +00:00
VGETMANTSH Vdq{K}{z},Hdq,Wsh{sae},Ib nil [evex m:3 p:0 l:i w:0 0x27 /r ib] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R|R
Initial commit.
2020-07-21 08:19:18 +00:00
VGETMANTSS Vdq{K}{z},Hdq,Wss{sae},Ib nil [evex m:3 p:1 l:i w:0 0x27 /r ib] s:AVX512F, t:AVX512, l:t1s, e:E2, w:W|R|R|R|R
VGETMANTSD Vdq{K}{z},Hdq,Wsd{sae},Ib nil [evex m:3 p:1 l:i w:1 0x27 /r ib] s:AVX512F, t:AVX512, l:t1s, e:E2, w:W|R|R|R|R
# 0x30 - 0x3F
Improved comments & improved vector length specifiers.
2023-02-04 10:02:05 +00:00
VINSERTI32X4 Vuv{K}{z},Huv,Wdq,Ib nil [evex m:3 p:1 l:x w:0 0x38 /r ib] s:AVX512F, t:AVX512, a:NOL0, l:t4, e:E6NF, w:W|R|R|R|R
VINSERTI64X2 Vuv{K}{z},Huv,Wdq,Ib nil [evex m:3 p:1 l:x w:1 0x38 /r ib] s:AVX512DQ, t:AVX512, a:NOL0, l:t2, e:E6NF, w:W|R|R|R|R
VEXTRACTI32X4 Wdq{K}{z},Vuv,Ib nil [evex m:3 p:1 l:x w:0 0x39 /r ib] s:AVX512F, t:AVX512, a:NOL0, l:t4, e:E6NF, w:W|R|R|R
VEXTRACTI64X2 Wdq{K}{z},Vuv,Ib nil [evex m:3 p:1 l:x w:1 0x39 /r ib] s:AVX512DQ, t:AVX512, a:NOL0, l:t2, e:E6NF, w:W|R|R|R
Initial commit.
2020-07-21 08:19:18 +00:00
VINSERTI32X8 Voq{K}{z},Hoq,Wqq,Ib nil [evex m:3 p:1 l:2 w:0 0x3A /r ib] s:AVX512DQ, t:AVX512, l:t8, e:E6NF, w:W|R|R|R|R
VINSERTI64X4 Voq{K}{z},Hoq,Wqq,Ib nil [evex m:3 p:1 l:2 w:1 0x3A /r ib] s:AVX512F, t:AVX512, l:t4, e:E6NF, w:W|R|R|R|R
VEXTRACTI32X8 Wqq{K}{z},Voq,Ib nil [evex m:3 p:1 l:2 w:0 0x3B /r ib] s:AVX512DQ, t:AVX512, l:t8, e:E6NF, w:W|R|R|R
VEXTRACTI64X4 Wqq{K}{z},Voq,Ib nil [evex m:3 p:1 l:2 w:1 0x3B /r ib] s:AVX512F, t:AVX512, l:t4, e:E6NF, w:W|R|R|R
Improved comments & improved vector length specifiers.
2023-02-04 10:02:05 +00:00
VPCMPUB rKq{K},Hfv,Wfv,Ib nil [evex m:3 p:1 l:x w:0 0x3E /r ib] s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R|R
VPCMPUW rKq{K},Hfv,Wfv,Ib nil [evex m:3 p:1 l:x w:1 0x3E /r ib] s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R|R
VPCMPB rKq{K},Hfv,Wfv,Ib nil [evex m:3 p:1 l:x w:0 0x3F /r ib] s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R|R
VPCMPW rKq{K},Hfv,Wfv,Ib nil [evex m:3 p:1 l:x w:1 0x3F /r ib] s:AVX512BW, t:AVX512, l:fvm, e:E4nb, w:W|R|R|R|R
Initial commit.
2020-07-21 08:19:18 +00:00
# 0x40 - 0x4F
Improved comments & improved vector length specifiers.
2023-02-04 10:02:05 +00:00
VDBPSADBW Vfv{K}{z},Hfv,Wfv,Ib nil [evex m:3 p:1 l:x w:0 0x42 /r ib] s:AVX512BW, t:AVX512, l:fvm, e:E4NFnb, w:W|R|R|R|R
VSHUFI32X4 Vuv{K}{z},Huv,Wuv|B32,Ib nil [evex m:3 p:1 l:x w:0 0x43 /r ib] s:AVX512F, t:AVX512, a:NOL0, l:fv, e:E4NF, w:W|R|R|R|R
VSHUFI64X2 Vuv{K}{z},Huv,Wuv|B64,Ib nil [evex m:3 p:1 l:x w:1 0x43 /r ib] s:AVX512F, t:AVX512, a:NOL0, l:fv, e:E4NF, w:W|R|R|R|R
VPCLMULQDQ Vfv,Hfv,Wfv,Ib nil [evex m:3 p:1 l:x w:i 0x44 /r ib] s:VPCLMULQDQ, t:VPCLMULQDQ, l:fvm, e:E4NF, w:W|R|R|R
Initial commit.
2020-07-21 08:19:18 +00:00
# 0x50 - 0x5F
Improved comments & improved vector length specifiers.
2023-02-04 10:02:05 +00:00
VRANGEPS Vfv{K}{z},Hfv,Wfv|B32{sae},Ib nil [evex m:3 p:1 l:x w:0 0x50 /r ib] s:AVX512DQ, t:AVX512, l:fv, e:E2, w:W|R|R|R|R
VRANGEPD Vfv{K}{z},Hfv,Wfv|B64{sae},Ib nil [evex m:3 p:1 l:x w:1 0x50 /r ib] s:AVX512DQ, t:AVX512, l:fv, e:E2, w:W|R|R|R|R
Initial commit.
2020-07-21 08:19:18 +00:00
VRANGESS Vdq{K}{z},Hdq,Wss{sae},Ib nil [evex m:3 p:1 l:i w:0 0x51 /r ib] s:AVX512DQ, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R
VRANGESD Vdq{K}{z},Hdq,Wsd{sae},Ib nil [evex m:3 p:1 l:i w:1 0x51 /r ib] s:AVX512DQ, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R
Improved comments & improved vector length specifiers.
2023-02-04 10:02:05 +00:00
VFIXUPIMMPS Vfv{K}{z},Hfv,Wfv|B32{sae},Ib nil [evex m:3 p:1 l:x w:0 0x54 /r ib] s:AVX512F, t:AVX512, l:fv, e:E2, w:RW|R|R|R|R
VFIXUPIMMPD Vfv{K}{z},Hfv,Wfv|B64{sae},Ib nil [evex m:3 p:1 l:x w:1 0x54 /r ib] s:AVX512F, t:AVX512, l:fv, e:E2, w:RW|R|R|R|R
Initial commit.
2020-07-21 08:19:18 +00:00
VFIXUPIMMSS Vdq{K}{z},Hdq,Wss{sae},Ib nil [evex m:3 p:1 l:i w:0 0x55 /r ib] s:AVX512F, t:AVX512, l:t1s, e:E3, w:RW|R|R|R|R
VFIXUPIMMSD Vdq{K}{z},Hdq,Wsd{sae},Ib nil [evex m:3 p:1 l:i w:1 0x55 /r ib] s:AVX512F, t:AVX512, l:t1s, e:E3, w:RW|R|R|R|R
Improved comments & improved vector length specifiers.
2023-02-04 10:02:05 +00:00
VREDUCEPH Vfv{K}{z},Wfv|B16{sae},Ib nil [evex m:3 p:0 l:x w:0 0x56 /r ib] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R
VREDUCEPS Vfv{K}{z},Wfv|B32{sae},Ib nil [evex m:3 p:1 l:x w:0 0x56 /r ib] s:AVX512DQ, t:AVX512, l:fv, e:E2, w:W|R|R|R
VREDUCEPD Vfv{K}{z},Wfv|B64{sae},Ib nil [evex m:3 p:1 l:x w:1 0x56 /r ib] s:AVX512DQ, t:AVX512, l:fv, e:E2, w:W|R|R|R
Multiple changes - Add support for AVX512-FP16 instructions, as per https://software.intel.com/content/www/us/en/develop/download/intel-avx512-fp16-architecture-specification.html - Bug fix: zeroing with no masking is not supported, so return an error if we encounter such encodings - Bug fix: ignore VEX/EVEX.W field outside 64 bit mode for some instructions - Several other minor fixes and improvements
2021-07-08 09:40:39 +00:00
VREDUCESH Vdq{K}{z},Hdq,Wsh{sae},Ib nil [evex m:3 p:0 l:i w:0 0x57 /r ib] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R|R
Initial commit.
2020-07-21 08:19:18 +00:00
VREDUCESS Vdq{K}{z},Hdq,Wss{sae},Ib nil [evex m:3 p:1 l:i w:0 0x57 /r ib] s:AVX512DQ, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R
VREDUCESD Vdq{K}{z},Hdq,Wsd{sae},Ib nil [evex m:3 p:1 l:i w:1 0x57 /r ib] s:AVX512DQ, t:AVX512, l:t1s, e:E3, w:W|R|R|R|R
# 0x60 - 0x6F
Improved comments & improved vector length specifiers.
2023-02-04 10:02:05 +00:00
VFPCLASSPH rKq{K},Wfv|B16,Ib nil [evex m:3 p:0 l:x w:0 0x66 /r ib] s:AVX512FP16, t:AVX512FP16, l:fv, e:E4, w:W|R|R|R
VFPCLASSPS rKq{K},Wfv|B32,Ib nil [evex m:3 p:1 l:x w:0 0x66 /r ib] s:AVX512DQ, t:AVX512, l:fv, e:E4, w:W|R|R|R
VFPCLASSPD rKq{K},Wfv|B64,Ib nil [evex m:3 p:1 l:x w:1 0x66 /r ib] s:AVX512DQ, t:AVX512, l:fv, e:E4, w:W|R|R|R
Multiple changes - Add support for AVX512-FP16 instructions, as per https://software.intel.com/content/www/us/en/develop/download/intel-avx512-fp16-architecture-specification.html - Bug fix: zeroing with no masking is not supported, so return an error if we encounter such encodings - Bug fix: ignore VEX/EVEX.W field outside 64 bit mode for some instructions - Several other minor fixes and improvements
2021-07-08 09:40:39 +00:00
VFPCLASSSH rKq{K},Wsh,Ib nil [evex m:3 p:0 l:i w:0 0x67 /r ib] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E10, w:W|R|R|R
Initial commit.
2020-07-21 08:19:18 +00:00
VFPCLASSSS rKq{K},Wss,Ib nil [evex m:3 p:1 l:i w:0 0x67 /r ib] s:AVX512DQ, t:AVX512, l:t1s, e:E6, w:W|R|R|R
VFPCLASSSD rKq{K},Wsd,Ib nil [evex m:3 p:1 l:i w:1 0x67 /r ib] s:AVX512DQ, t:AVX512, l:t1s, e:E6, w:W|R|R|R
# 0x70 - 0x7F
Improved comments & improved vector length specifiers.
2023-02-04 10:02:05 +00:00
VPSHLDW Vfv{K}{z},Hfv,Wfv,Ib nil [evex m:3 p:1 l:x w:1 0x70 /r ib] s:AVX512VBMI2, t:AVX512VBMI, l:fvm, e:E4, w:RW|R|R|R|R
VPSHLDD Vfv{K}{z},Hfv,Wfv|B32,Ib nil [evex m:3 p:1 l:x w:0 0x71 /r ib] s:AVX512VBMI2, t:AVX512VBMI, l:fv, e:E4, w:RW|R|R|R|R
VPSHLDQ Vfv{K}{z},Hfv,Wfv|B64,Ib nil [evex m:3 p:1 l:x w:1 0x71 /r ib] s:AVX512VBMI2, t:AVX512VBMI, l:fv, e:E4, w:RW|R|R|R|R
VPSHRDW Vfv{K}{z},Hfv,Wfv,Ib nil [evex m:3 p:1 l:x w:1 0x72 /r ib] s:AVX512VBMI2, t:AVX512VBMI, l:fvm, e:E4, w:RW|R|R|R|R
VPSHRDD Vfv{K}{z},Hfv,Wfv|B32,Ib nil [evex m:3 p:1 l:x w:0 0x73 /r ib] s:AVX512VBMI2, t:AVX512VBMI, l:fv, e:E4, w:RW|R|R|R|R
VPSHRDQ Vfv{K}{z},Hfv,Wfv|B64,Ib nil [evex m:3 p:1 l:x w:1 0x73 /r ib] s:AVX512VBMI2, t:AVX512VBMI, l:fv, e:E4, w:RW|R|R|R|R
Initial commit.
2020-07-21 08:19:18 +00:00
# 0x80 - 0x8F
# 0x90 - 0x9F
# 0xA0 - 0xAF
# 0xB0 - 0xBF
# 0xC0 - 0xCF
Improved comments & improved vector length specifiers.
2023-02-04 10:02:05 +00:00
VCMPPH rK{K},Hfv,Wfv|B16{sae},Ib nil [evex m:3 p:0 l:x w:0 0xC2 /r ib] s:AVX512FP16, t:AVX512FP16, l:fv, e:E2, w:W|R|R|R|R
VCMPSH rK{K},Hfv,Wsh{sae},Ib nil [evex m:3 p:2 l:i w:0 0xC2 /r ib] s:AVX512FP16, t:AVX512FP16, l:t1s16, e:E3, w:W|R|R|R|R
Multiple changes - Add support for AVX512-FP16 instructions, as per https://software.intel.com/content/www/us/en/develop/download/intel-avx512-fp16-architecture-specification.html - Bug fix: zeroing with no masking is not supported, so return an error if we encounter such encodings - Bug fix: ignore VEX/EVEX.W field outside 64 bit mode for some instructions - Several other minor fixes and improvements
2021-07-08 09:40:39 +00:00
Improved comments & improved vector length specifiers.
2023-02-04 10:02:05 +00:00
VGF2P8AFFINEQB Vfv{K}{z},Hfv,Wfv|B64,Ib nil [evex m:3 p:1 l:x w:1 0xCE /r ib] s:GFNI, t:GFNI, l:fv, e:E4NF, w:W|R|R|R|R
VGF2P8AFFINEINVQB Vfv{K}{z},Hfv,Wfv|B64,Ib nil [evex m:3 p:1 l:x w:1 0xCF /r ib] s:GFNI, t:GFNI, l:fv, e:E4NF, w:W|R|R|R|R
Initial commit.
2020-07-21 08:19:18 +00:00
# 0xD0 - 0xDF
# 0xE0 - 0xEF
# 0xF0 - 0xFF
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