mirror of
https://github.com/trezor/trezor-firmware.git
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178 lines
4.6 KiB
C
178 lines
4.6 KiB
C
/**
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******************************************************************************
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* @file stm32f429i_discovery_sdram.h
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* @author MCD Application Team
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* @brief This file contains all the functions prototypes for the
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* stm32f429i_discovery_sdram.c driver.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2017 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __STM32F429I_DISCOVERY_SDRAM_H
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#define __STM32F429I_DISCOVERY_SDRAM_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include STM32_HAL_H
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/** @addtogroup BSP
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* @{
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*/
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/** @addtogroup STM32F429I_DISCOVERY
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* @{
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*/
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/** @addtogroup STM32F429I_DISCOVERY_SDRAM
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* @{
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*/
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/** @defgroup STM32F429I_DISCOVERY_SDRAM_Exported_Types STM32F429I DISCOVERY
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* SDRAM Exported Types
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* @{
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*/
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/**
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* @}
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*/
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/** @defgroup STM32F429I_DISCOVERY_SDRAM_Exported_Constants STM32F429I DISCOVERY
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* SDRAM Exported Constants
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* @{
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*/
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/**
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* @brief SDRAM status structure definition
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*/
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#define SDRAM_OK ((uint8_t)0x00)
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#define SDRAM_ERROR ((uint8_t)0x01)
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/**
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* @brief FMC SDRAM Bank address
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*/
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#define SDRAM_DEVICE_ADDR ((uint32_t)0xD0000000)
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#define SDRAM_DEVICE_SIZE \
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((uint32_t)0x800000) /* SDRAM device size in Bytes \
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*/
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/**
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* @brief FMC SDRAM Memory Width
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*/
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/* #define SDRAM_MEMORY_WIDTH FMC_SDRAM_MEM_BUS_WIDTH_8 */
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#define SDRAM_MEMORY_WIDTH FMC_SDRAM_MEM_BUS_WIDTH_16
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/**
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* @brief FMC SDRAM CAS Latency
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*/
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/* #define SDRAM_CAS_LATENCY FMC_SDRAM_CAS_LATENCY_2 */
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#define SDRAM_CAS_LATENCY FMC_SDRAM_CAS_LATENCY_3
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/**
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* @brief FMC SDRAM Memory clock period
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*/
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#define SDCLOCK_PERIOD \
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FMC_SDRAM_CLOCK_PERIOD_2 /* Default configuration used with LCD */
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/* #define SDCLOCK_PERIOD FMC_SDRAM_CLOCK_PERIOD_3 */
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/**
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* @brief FMC SDRAM Memory Read Burst feature
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*/
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#define SDRAM_READBURST \
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FMC_SDRAM_RBURST_DISABLE /* Default configuration used with LCD */
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/* #define SDRAM_READBURST FMC_SDRAM_RBURST_ENABLE */
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/**
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* @brief FMC SDRAM Bank Remap
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*/
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/* #define SDRAM_BANK_REMAP */
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/* Set the refresh rate counter */
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/* (15.62 us x Freq) - 20 */
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#define REFRESH_COUNT ((uint32_t)1386) /* SDRAM refresh counter */
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#define SDRAM_TIMEOUT ((uint32_t)0xFFFF)
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/* DMA definitions for SDRAM DMA transfer */
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#define __DMAx_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE
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#define SDRAM_DMAx_CHANNEL DMA_CHANNEL_0
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#define SDRAM_DMAx_STREAM DMA2_Stream0
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#define SDRAM_DMAx_IRQn DMA2_Stream0_IRQn
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#define SDRAM_DMAx_IRQHandler DMA2_Stream0_IRQHandler
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/**
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* @brief FMC SDRAM Mode definition register defines
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*/
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#define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000)
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#define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001)
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#define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002)
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#define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004)
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#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000)
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#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008)
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#define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020)
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#define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030)
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#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000)
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#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
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#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200)
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/**
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* @}
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*/
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/** @defgroup STM32F429I_DISCOVERY_SDRAM_Exported_Macro STM32F429I DISCOVERY
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* SDRAM Exported Macro
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* @{
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*/
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/**
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* @}
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*/
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/** @defgroup STM32F429I_DISCOVERY_SDRAM_Exported_Functions STM32F429I DISCOVERY
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* SDRAM Exported Functions
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* @{
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*/
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uint8_t BSP_SDRAM_Init(void);
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void BSP_SDRAM_Initialization_sequence(uint32_t RefreshCount);
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uint8_t BSP_SDRAM_ReadData(uint32_t uwStartAddress, uint32_t* pData,
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uint32_t uwDataSize);
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uint8_t BSP_SDRAM_ReadData_DMA(uint32_t uwStartAddress, uint32_t* pData,
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uint32_t uwDataSize);
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uint8_t BSP_SDRAM_WriteData(uint32_t uwStartAddress, uint32_t* pData,
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uint32_t uwDataSize);
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uint8_t BSP_SDRAM_WriteData_DMA(uint32_t uwStartAddress, uint32_t* pData,
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uint32_t uwDataSize);
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uint8_t BSP_SDRAM_Sendcmd(FMC_SDRAM_CommandTypeDef* SdramCmd);
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void BSP_SDRAM_DMA_IRQHandler(void);
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void sdram_init(void);
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* __STM32F429I_DISCOVERY_SDRAM_H */
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