12 Commits (ba741b81fd65ab61d870c98a1b16be0b1542c448)

Author	SHA1	Message	Date
tychovrahe	1909d1ebdb	feat(core): improve flexibility of combine script, add combine fw make targets ... [no changelog]	7 months ago
tychovrahe	c3f84e2949	perf(core): optimize boot speed on U5 by using has processor to calculate image hashes, switches to sha256 ... [no changelog]	7 months ago
tychovrahe	8150636a81	feat(core): add basic support for STM32U5	7 months ago
tychovrahe	8a4f376f20	refactor(core): prepare fw for differently sized fw chunks ... [no changelog]	11 months ago
Martin Milata	040f6c2c8e	Merge branch 'master' into release/23.09	1 year ago
matejcik	c892d4b0ba	refactor(core): inject full model name from build script ... so that we don't have to do awkward string operations when we need it [no changelog]	1 year ago
Martin Milata	07027a69e9	Merge branch 'master' into release/23.09	1 year ago
tychovrahe	bd0b0b2d15	refactor(core): move model specific norcow config to model header ... [no changelog]	1 year ago
tychovrahe	c9a657b074	feat(core): set final name for Safe 3 ... [no changelog]	1 year ago
tychovrahe	5a86add884	refactor(core): differentiate models by internal name in python ... [no changelog]	1 year ago
tychovrahe	238e3fd7c1	refactor(core): add abstraction over flash memory layout ... [no changelog]	1 year ago
tychovrahe	d3284baf21	feat(core): support STM32F429 discovery board	1 year ago