18 Commits

Author	SHA1	Message	Date
tychovrahe	c3f84e2949	perf(core): optimize boot speed on U5 by using has processor to calculate image hashes, switches to sha256 ... [no changelog]	2024-02-29 23:05:56 +01:00
tychovrahe	5e4e398f64	chore(core): optimize flash usage - SD card on U5 ... [no changelog]	2024-02-29 23:05:56 +01:00
tychovrahe	f83e33399f	chore(core): optimize flash usage - tamper on U5 ... [no changelog]	2024-02-29 23:05:56 +01:00
tychovrahe	ce82f53010	feat(core): support SD card on STM32U5 ... [no changelog]	2024-02-29 23:05:56 +01:00
tychovrahe	5106ac7aa3	feat(core): support optiga handling on U5 ... [no changelog]	2024-02-29 23:05:56 +01:00
tychovrahe	72dc8f57e8	feat(core): add haptic feedback ... [no changelog]	2024-02-29 23:05:56 +01:00
tychovrahe	a71a608ea7	feat(core): add basic support for T3T1	2024-02-29 23:05:56 +01:00
tychovrahe	7d7ccc9dde	chore(core): unify i2c instances numbering ... [no changelog]	2024-02-29 23:05:56 +01:00
tychovrahe	834693a115	fix(core): fix OTP programming on U5 ... [no changelog]	2024-02-29 23:05:56 +01:00
tychovrahe	cec0191360	fix(core): fix bootloader update on STM32U5 ... [no changelog]	2024-02-29 23:05:56 +01:00
tychovrahe	8815e764d2	feat(core): add support for STM32U585 ... [no changelog]	2024-02-29 23:05:56 +01:00
cepetr	4cf781abb2	chore(core, legacy, storage): refactor flash drivers ... [no changelog]	2024-02-29 23:05:56 +01:00
cepetr	271bed8bf6	chore(core): use cortex-m33 stack protection	2024-02-29 23:05:56 +01:00
cepetr	7e427432ea	chore(core): refactor trustzone initialization ... [no changelog]	2024-02-29 23:05:56 +01:00
cepetr	b504baceda	chore(core): refactor mpu initialization ... [no changelog]	2024-02-29 23:05:56 +01:00
cepetr	c4c571d837	chore(core): refactor boot_args ... [no changelog]	2024-02-29 23:05:56 +01:00
tychovrahe	353095ae95	feat(core): add support for STM32U5A9J-DK board ... [no changelog]	2024-02-29 23:05:56 +01:00
tychovrahe	8150636a81	feat(core): add basic support for STM32U5	2024-02-29 23:05:56 +01:00