52 Commits

Author	SHA1	Message	Date
tychovrahe	d71d9e9c34	feat(core): add T3W1 emulator build ... [no changelog]	2024-10-09 15:06:40 +02:00
tychovrahe	915d4fca94	feat(core): add support for T3W1, on F4 ... [no changelog]	2024-10-09 15:06:40 +02:00
tychovrahe	138fadbf7b	feat(core): add LHS200KB display panel ... [no changelog]	2024-10-09 15:06:40 +02:00
tychovrahe	d312944f1e	feat(core): embed bootloaders to DISC1,2 models in order to support testing related featurees ... [no changelog]	2024-09-27 09:49:20 +02:00
tychovrahe	d412ce987e	refactor(core): use common layout.c file ... [no changelog]	2024-09-27 09:49:20 +02:00
tychovrahe	21c1359ac6	refactor(core): streamline layout definitions ... [no changelog]	2024-09-27 09:49:20 +02:00
tychovrahe	e13d4a45a6	chore(core): remove residual support for T1B1 in core ... [no changelog]	2024-09-25 09:18:01 +02:00
tychovrahe	e9c025751c	fix(core): fix storage offsets ... [no changelog]	2024-09-24 12:21:53 +02:00
tychovrahe	28f420189a	refactor(core): combined build of coreapp + kernel, linker scripts refactoring ... [no changelog]	2024-09-24 12:21:53 +02:00
cepetr	1c991339ce	refactor(core/embed): split firmware into kernel & coreapp ... [no changelog]	2024-09-24 12:21:53 +02:00
cepetr	7f3cff04f1	refactor(core/embed): introduce new mpu driver ... [no changelog]	2024-09-24 12:21:53 +02:00
cepetr	91649dc7cb	feat(core/embed): introduce non-blocking i2c drivers ... [no changelog]	2024-09-24 12:21:53 +02:00
cepetr	33c2bcbe52	refactor(core/embed): simplify ensure_compatible_settings ... [no changelog]	2024-09-24 12:21:53 +02:00
Martin Milata	5d8461969a	chore(core): add hashes for 2.1.8 bootloader	2024-09-09 14:21:38 +02:00
Martin Milata	37006592db	chore(core): add signed bootloader 2.1.8 for T3B1 and T3T1	2024-09-09 12:12:39 +02:00
tychovrahe	708b0274f5	chore(core): bump monotonic versions ... [no changelog]	2024-09-03 13:07:34 +02:00
tychovrahe	395a4af9be	refactor(core): extract monotonic version to model specific headers ... [no changelog]	2024-09-03 13:07:34 +02:00
tychovrahe	c1864a2a91	refactor(core): enclose monotonic counter to platform specific module ... [no changelog]	2024-09-03 13:07:34 +02:00
tychovrahe	7275a5544e	refactor(core): move embedded bootloaders and their hashes to model folders ... [no changelog]	2024-08-29 12:47:24 +02:00
tychovrahe	4397978563	chore(core): add T3B1 binaries ... [no changelog]	2024-08-01 13:29:38 +02:00
tychovrahe	1212a7319a	fix(core): T3T1: adjust touch coordinates	2024-07-25 12:37:21 +03:00
tychovrahe	354dad617d	fix(core): fix vector table alignment on STM32U5 ... [no changelog]	2024-07-16 16:38:48 +02:00
tychovrahe	7c94080227	refactor(core): move vendor headers to model specific directories ... [no changelog]	2024-07-16 15:56:28 +02:00
tychovrahe	11b1d5ca41	chore(core): add T3B1 production keys ... [no changelog]	2024-07-16 15:56:28 +02:00
tychovrahe	78b4017859	feat(core): add support for T3B1	2024-07-16 15:56:28 +02:00
tychovrahe	e3b9548506	chore(core): add TS5 background image for emulator ... [no changelog]	2024-07-12 15:38:33 +02:00
tychovrahe	9166dc330e	refactor(core): reorganize model-specific files in embed/models ... [no changelog]	2024-05-21 19:01:31 +02:00
tychovrahe	6b31b8eec3	chore(core): change USB manufacturer and product strings for new models ... [no changelog]	2024-05-06 13:10:36 +02:00
matejcik	867300b8c6	chore(core): include T3T1 boardloader / bootloader production keys	2024-04-12 16:13:52 +02:00
tychovrahe	1600759457	refactor(core): simplify secret.h api, hide platform differences ... [no changelog]	2024-04-11 16:13:58 +02:00
tychovrahe	ffccf849eb	chore(core): fill T3T1 model full name ... [no changelog]	2024-04-04 12:46:44 +02:00
cepetr	1e3e7f808b	fix(core): fix build on disc2 model	2024-03-27 10:44:56 +01:00
tychovrahe	1909d1ebdb	feat(core): improve flexibility of combine script, add combine fw make targets ... [no changelog]	2024-03-13 22:12:57 +01:00
tychovrahe	b62dc27f06	feat(core): add translations support for U5 models ... [no changelog]	2024-02-29 23:05:56 +01:00
tychovrahe	c3f84e2949	perf(core): optimize boot speed on U5 by using has processor to calculate image hashes, switches to sha256 ... [no changelog]	2024-02-29 23:05:56 +01:00
tychovrahe	a71a608ea7	feat(core): add basic support for T3T1	2024-02-29 23:05:56 +01:00
tychovrahe	8815e764d2	feat(core): add support for STM32U585 ... [no changelog]	2024-02-29 23:05:56 +01:00
cepetr	4cf781abb2	chore(core, legacy, storage): refactor flash drivers ... [no changelog]	2024-02-29 23:05:56 +01:00
tychovrahe	353095ae95	feat(core): add support for STM32U5A9J-DK board ... [no changelog]	2024-02-29 23:05:56 +01:00
tychovrahe	8150636a81	feat(core): add basic support for STM32U5	2024-02-29 23:05:56 +01:00
grdddj	b8ea21d24a	feat(all): implement translations into Trezor ... Co-authored-by matejcik <ja@matejcik.cz>	2024-02-12 14:49:32 +01:00
tychovrahe	8a4f376f20	refactor(core): prepare fw for differently sized fw chunks ... [no changelog]	2023-10-20 16:33:53 +02:00
Martin Milata	040f6c2c8e	Merge branch 'master' into release/23.09	2023-09-29 16:42:23 +02:00
matejcik	c892d4b0ba	refactor(core): inject full model name from build script ... so that we don't have to do awkward string operations when we need it [no changelog]	2023-09-29 16:27:27 +02:00
Martin Milata	07027a69e9	Merge branch 'master' into release/23.09	2023-09-15 14:33:20 +02:00
tychovrahe	bd0b0b2d15	refactor(core): move model specific norcow config to model header ... [no changelog]	2023-08-29 11:17:19 +02:00
tychovrahe	c9a657b074	feat(core): set final name for Safe 3 ... [no changelog]	2023-08-18 16:14:47 +02:00
tychovrahe	5a86add884	refactor(core): differentiate models by internal name in python ... [no changelog]	2023-08-15 22:08:11 +02:00
tychovrahe	e8281385f6	feat(core): implement secret handling in bootloader	2023-08-15 09:37:38 +02:00
tychovrahe	238e3fd7c1	refactor(core): add abstraction over flash memory layout ... [no changelog]	2023-07-25 10:25:20 +02:00