6 Commits

Author	SHA1	Message	Date
tychovrahe	33bb7ef410	fix(core): increase framebuffer section size on U5G models ... [no changelog]	2025-01-06 11:42:40 +01:00
tychovrahe	04a1b3943f	chore(core): re-balance distribution in flash on F4 models ... [no changelog]	2025-01-02 11:41:48 +01:00
tychovrahe	0bc729a3da	refactor(core): streamline RAM layout ... [no changelog]	2024-12-11 21:41:52 +01:00
tychovrahe	b0dd521c5d	fix(core): separate bootargs from kernel/aux SRAM ... [no changelog]	2024-11-20 11:17:35 +01:00
tychovrahe	40c5426717	fix(core): fix MPU kernel sram setting for STM32U5G ... [no changelog]	2024-11-20 11:17:35 +01:00
cepetr	089db2cadf	refactor(core): restructure embed folder ... [no changelog]	2024-11-18 09:41:02 +01:00