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fix(core): increase framebuffer section size on U5G models

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This commit is contained in:
tychovrahe 2025-01-01 12:23:59 +01:00 committed by TychoVrahe
parent d235ed3d3d
commit 33bb7ef410
8 changed files with 44 additions and 44 deletions
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16
core/embed/models/D002/memory.ld
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@ -39,17 +39,17 @@ ASSETS_START = 0xc3e0000;
ASSETS_MAXSIZE = 0x20000;
ASSETS_SECTOR_START = 0x1f0;
ASSETS_SECTOR_END = 0x1ff;
FB1_RAM_START = 0x30000000;
FB1_RAM_SIZE = 0xbfe00;
BOOTARGS_START = 0x300bfe00;
BOOTARGS_START = 0x30000000;
BOOTARGS_SIZE = 0x200;
MAIN_RAM_START = 0x300c0000;
MAIN_RAM_SIZE = 0xfe00;
FB1_RAM_START = 0x30000200;
FB1_RAM_SIZE = 0xc1000;
MAIN_RAM_START = 0x300c1200;
MAIN_RAM_SIZE = 0xec00;
SAES_RAM_START = 0x300cfe00;
SAES_RAM_SIZE = 0x200;
FB2_RAM_START = 0x300d0000;
FB2_RAM_SIZE = 0xc0000;
AUX1_RAM_START = 0x30190000;
AUX1_RAM_SIZE = 0xe0000;
FB2_RAM_SIZE = 0xc1000;
AUX1_RAM_START = 0x30191000;
AUX1_RAM_SIZE = 0xdf000;
CODE_ALIGNMENT = 0x400;
COREAPP_ALIGNMENT = 0x2000;

18
core/embed/models/D002/model_D002.h
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@ -85,23 +85,23 @@
#define ASSETS_SECTOR_END 0x1FF
// RAM layout
#define FB1_RAM_START 0x30000000
#define FB1_RAM_SIZE (768 * 1024 - 512)
#define BOOTARGS_START 0x300BFE00
#define BOOTARGS_START 0x30000000
#define BOOTARGS_SIZE 0x200
#define MAIN_RAM_START 0x300C0000
#define MAIN_RAM_SIZE (64 * 1024 - 512)
#define FB1_RAM_START 0x30000200
#define FB1_RAM_SIZE (772 * 1024)
#define MAIN_RAM_START 0x300C1200
#define MAIN_RAM_SIZE (60 * 1024 - 512 - 512)
#define SAES_RAM_START 0x300CFE00
#define SAES_RAM_SIZE 512
#define FB2_RAM_START 0x300D0000
#define FB2_RAM_SIZE (768 * 1024)
#define FB2_RAM_SIZE (772 * 1024)
#define AUX1_RAM_START 0x30190000
#define AUX1_RAM_SIZE (896 * 1024)
#define AUX1_RAM_START 0x30191000
#define AUX1_RAM_SIZE (892 * 1024)
// misc
#define CODE_ALIGNMENT 0x400

16
core/embed/models/T3W1/memory.ld
View File

@ -39,17 +39,17 @@ ASSETS_START = 0xc3e0000;
ASSETS_MAXSIZE = 0x20000;
ASSETS_SECTOR_START = 0x1f0;
ASSETS_SECTOR_END = 0x1ff;
FB1_RAM_START = 0x30000000;
FB1_RAM_SIZE = 0xbfe00;
BOOTARGS_START = 0x300bfe00;
BOOTARGS_START = 0x30000000;
BOOTARGS_SIZE = 0x200;
MAIN_RAM_START = 0x300c0000;
MAIN_RAM_SIZE = 0xfe00;
FB1_RAM_START = 0x30000200;
FB1_RAM_SIZE = 0xc1000;
MAIN_RAM_START = 0x300c1200;
MAIN_RAM_SIZE = 0xec00;
SAES_RAM_START = 0x300cfe00;
SAES_RAM_SIZE = 0x200;
FB2_RAM_START = 0x300d0000;
FB2_RAM_SIZE = 0xc0000;
AUX1_RAM_START = 0x30190000;
AUX1_RAM_SIZE = 0xe0000;
FB2_RAM_SIZE = 0xc1000;
AUX1_RAM_START = 0x30191000;
AUX1_RAM_SIZE = 0xdf000;
CODE_ALIGNMENT = 0x400;
COREAPP_ALIGNMENT = 0x2000;

18
core/embed/models/T3W1/model_T3W1.h
View File

@ -91,23 +91,23 @@
#define ASSETS_SECTOR_END 0x1FF
// RAM layout
#define FB1_RAM_START 0x30000000
#define FB1_RAM_SIZE (768 * 1024 - 512)
#define BOOTARGS_START 0x300BFE00
#define BOOTARGS_START 0x30000000
#define BOOTARGS_SIZE 0x200
#define MAIN_RAM_START 0x300C0000
#define MAIN_RAM_SIZE (64 * 1024 - 512)
#define FB1_RAM_START 0x30000200
#define FB1_RAM_SIZE (772 * 1024)
#define MAIN_RAM_START 0x300C1200
#define MAIN_RAM_SIZE (60 * 1024 - 512 - 512)
#define SAES_RAM_START 0x300CFE00
#define SAES_RAM_SIZE 512
#define FB2_RAM_START 0x300D0000
#define FB2_RAM_SIZE (768 * 1024)
#define FB2_RAM_SIZE (772 * 1024)
#define AUX1_RAM_START 0x30190000
#define AUX1_RAM_SIZE (896 * 1024)
#define AUX1_RAM_START 0x30191000
#define AUX1_RAM_SIZE (892 * 1024)
// misc
#define CODE_ALIGNMENT 0x400

8
core/embed/sys/linker/stm32u5g/boardloader.ld
View File

@ -31,16 +31,16 @@ confidential_vma = ADDR(.confidential);
confidential_size = SIZEOF(.confidential);
/* used by the startup code to wipe memory */
_startup_clear_ram_0_start = MCU_SRAM1;
_startup_clear_ram_0_end = MCU_SRAM1 + MCU_SRAM1_SIZE - BOOTARGS_SIZE;
_startup_clear_ram_0_start = MCU_SRAM1 + BOOTARGS_SIZE;
_startup_clear_ram_0_end = MCU_SRAM1 + MCU_SRAM1_SIZE;
_startup_clear_ram_1_start = MCU_SRAM2;
_startup_clear_ram_1_end = MCU_SRAM6 + MCU_SRAM6_SIZE;
_startup_clear_ram_2_start = MCU_SRAM4;
_startup_clear_ram_2_end = MCU_SRAM4 + MCU_SRAM4_SIZE;
/* used by the jump code to wipe memory */
_handoff_clear_ram_0_start = MCU_SRAM1;
_handoff_clear_ram_0_end = MCU_SRAM1 + MCU_SRAM1_SIZE - BOOTARGS_SIZE;
_handoff_clear_ram_0_start = MCU_SRAM1 + BOOTARGS_SIZE;
_handoff_clear_ram_0_end = MCU_SRAM1 + MCU_SRAM1_SIZE;
_handoff_clear_ram_1_start = MCU_SRAM2;
_handoff_clear_ram_1_end = MCU_SRAM6 + MCU_SRAM6_SIZE;
_handoff_clear_ram_2_start = MCU_SRAM4;

4
core/embed/sys/linker/stm32u5g/bootloader.ld
View File

@ -30,8 +30,8 @@ confidential_vma = ADDR(.confidential);
confidential_size = SIZEOF(.confidential);
/* used by the startup code to wipe memory */
_startup_clear_ram_0_start = MCU_SRAM1;
_startup_clear_ram_0_end = MCU_SRAM1 + MCU_SRAM1_SIZE - BOOTARGS_SIZE;
_startup_clear_ram_0_start = MCU_SRAM1 + BOOTARGS_SIZE;
_startup_clear_ram_0_end = MCU_SRAM1 + MCU_SRAM1_SIZE;
_startup_clear_ram_1_start = MCU_SRAM2;
_startup_clear_ram_1_end = MCU_SRAM6 + MCU_SRAM6_SIZE;
_startup_clear_ram_2_start = MCU_SRAM4;

4
core/embed/sys/linker/stm32u5g/kernel.ld
View File

@ -41,8 +41,8 @@ _startup_clear_ram_2_start = MCU_SRAM4;
_startup_clear_ram_2_end = MCU_SRAM4 + MCU_SRAM4_SIZE;
/* used by the jump code to wipe memory */
_handoff_clear_ram_0_start = MCU_SRAM1;
_handoff_clear_ram_0_end = MCU_SRAM1 + MCU_SRAM1_SIZE - BOOTARGS_SIZE;
_handoff_clear_ram_0_start = MCU_SRAM1 + BOOTARGS_SIZE;
_handoff_clear_ram_0_end = MCU_SRAM1 + MCU_SRAM1_SIZE;
_handoff_clear_ram_1_start = MCU_SRAM2;
_handoff_clear_ram_1_end = MCU_SRAM6 + MCU_SRAM6_SIZE;
_handoff_clear_ram_2_start = MCU_SRAM4;

4
core/embed/sys/linker/stm32u5g/prodtest.ld
View File

@ -38,8 +38,8 @@ _startup_clear_ram_2_start = MCU_SRAM4;
_startup_clear_ram_2_end = MCU_SRAM4 + MCU_SRAM4_SIZE;
/* used by the jump code to wipe memory */
_handoff_clear_ram_0_start = MCU_SRAM1;
_handoff_clear_ram_0_end = MCU_SRAM1 + MCU_SRAM1_SIZE - BOOTARGS_SIZE;
_handoff_clear_ram_0_start = MCU_SRAM1 + BOOTARGS_SIZE;
_handoff_clear_ram_0_end = MCU_SRAM1 + MCU_SRAM1_SIZE;
_handoff_clear_ram_1_start = MCU_SRAM2;
_handoff_clear_ram_1_end = MCU_SRAM6 + MCU_SRAM6_SIZE;
_handoff_clear_ram_2_start = MCU_SRAM4;