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10,466 Commits 365 Branches 206 Tags 194 MiB
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Commit Graph

327 Commits

Author SHA1 Message Date
Martin Milata
81e66cb024 style(core/rust): enable clippy lints 
[no changelog]
 2021-09-23 14:22:40 +02:00
Martin Milata
bd005e33df refactor(core): decouple T1 button handling from touch 
[no changelog]
 2021-09-23 12:30:13 +02:00
Jan Pochyla
2c8dec93a6 feat(core): Split unix main, link core obj into Rust test target 2021-09-21 12:43:31 +02:00
matejcik
7a17124b43 refactor(core/rust): do not rely too much on new_exception helpers 2021-09-21 12:43:31 +02:00
matejcik
5e452dc57c refactor(core/rust): propagate unsafety of raise_exception 2021-09-21 12:43:31 +02:00
matejcik
806beb77d2 feat(core/rust): improve catch_exception, make use of Rust 1.55 2021-09-21 12:43:31 +02:00
matejcik
795ed2d339 fix(core/rust): fix "unnecessary unsafe" warning 
[no changelog]
 2021-09-21 12:43:31 +02:00
matejcik
31de21718f feat(core/rust): introduce Obj.is_null() 
[no changelog]
 2021-09-21 12:43:31 +02:00
matejcik
b666895303 feat(core/rust): catch, handle and propagate uPy exceptions 2021-09-21 12:43:31 +02:00
matejcik
8abcb6f8cc chore(core/rust): allow unused macros 
[no changelog]
 2021-09-21 12:43:31 +02:00
Jan Pochyla
7c65f0357a feat(core/rust): Implement exception catching in Rust 
chore(core): Add test for Rust exc catching

chore(core): Document exception catching in Rust

[no changelog]
 2021-09-21 12:43:31 +02:00
Martin Milata
aace875fef chore(vendor): bump micropython to 1.17 
Relevant micropython commits:
  d1bfb271d7686708fe8711a177629c8bf6e7f6a6 lib/uzlib: Move uzlib code from extmod to lib.
  4d546713ec8858cbf908de45de11cbfc46a20971 shared: Introduce new top-level dir and move 1st party lib code there.
  ca920f72184c50f61002aa9d5cd01555b1e28b7b py/mpstate: Make exceptions thread-local.
 2021-09-17 11:18:14 +02:00
Martin Milata
b062b95348 chore(vendor): bump micropython to 1.15 
Relevant micropython commits:
  ad4656b861f94277bed9647ca176e662ce5119e3 all: Rename BYTES_PER_WORD to MP_BYTES_PER_OBJ_WORD.
  9fef1c0bde2f9642d383bd56aa112447384a84ba py: Rename remaining object types to be of the form mp_type_xxx.
  5fdf351178df9a18df624ae0f5947d8a5a6bce40 py/gc: Don't include mpconfig.h and misc.h in gc.h.
 2021-09-17 11:18:14 +02:00
Martin Milata
d69b23e3c5 chore(core/emulator): ignore MICROPY_UNIX_COVERAGE 
Seems to be micropython internal flag that hasn't been working in our
emulator for some time.

Relevant micropython commits:
  b9a35bebf75be53a817bf6341af14b882093e345 py/qstr.h: Remove QSTR_FROM_STR_STATIC macro.

[no changelog]
 2021-09-17 11:18:14 +02:00
Pavol Rusnak
d153082c9c chore(vendor): bump micropython to 1.14 
Relevant micropython commits:
  4559bcb4679e04e0a5e24030675676ff6a9803f2 unix: Make mp_hal_delay_ms run MICROPY_EVENT_POLL_HOOK.
 2021-09-17 11:18:14 +02:00
Martin Milata
a007e062ab style(core): apply rustfmt 
[no changelog]
 2021-09-16 14:57:06 +02:00
Tomas Susanka
cec1f39a90 chore(core, legacy): bump versions 
[no changelog]
 2021-08-31 12:55:37 +02:00
Martin Milata
f37ca13f1a refactor(core): disable SD, SBU, fatfs for T1 build 2021-08-20 12:22:13 +02:00
Martin Milata
582e1318c4 feat(core/emulator): support protobuf messages in memory dumps 
[no changelog]
 2021-07-22 13:31:11 +02:00
Martin Milata
412d06fdfe docs(core+legacy): use towncrier for generating CHANGELOG.md 
core/embed/boardloader/CHANGELOG.md
core/embed/bootloader/CHANGELOG.md
core/embed/bootloader_ci/CHANGELOG.md
legacy/intermediate_fw/CHANGELOG.md
 2021-07-21 14:27:20 +02:00
Pavol Rusnak
d35071d732 docs(core+legacy): update changelogs to new format 2021-07-21 14:27:20 +02:00
Martin Milata
ceaf4da617 fix(core): explicitly refresh display on T1 
[no changelog]
 2021-07-20 22:00:42 +02:00
Pavol Rusnak
3d69ca1b1b chore(vendor): update nanopb to 0.4.5 2021-07-14 17:34:12 +02:00
matejcik
b41d4c71f0 feat(core/emulator): JSON memory map dump 
use `trezor.utils.mem_dump("somefile.json")` in a key place, then
`analyze.py src/somefile.json` to look at what is going on
 2021-07-14 13:50:24 +02:00
matejcik
fe6c131b14 feat(core/emulator): build emulator with -DSTATIC= 
This is perhaps a cleaner way to expose all relevant structures for
memory analysis.
 2021-07-14 13:50:24 +02:00
Martin Milata
81869fc4b0 chore(core): bump version to 2.4.2 
[skip_ci]
 2021-07-08 13:38:29 +02:00
Martin Milata
f06a57237b style(core): trezorhal/random_delays.c 2021-07-07 14:39:24 +02:00
Pavol Rusnak
8cfa5da1ce
docs: fix typos in comments 
[skip_ci]
 2021-06-30 15:41:55 +02:00
Ondřej Vejpustek
24200e7424 fixup! fix(legacy): make RDI work on T1 2021-06-24 17:34:24 +02:00
Ondrej Mikle
daa94ac941 fix(legacy): make RDI work on T1 2021-06-24 17:34:24 +02:00
Ondřej Vejpustek
b8b0ae09d9 fix(core): use unprivileged shutdown where needed 2021-06-23 16:40:45 +02:00
Ondřej Vejpustek
5984fd6ad7 feat(core): jump to unprivileged mode after shutdown 2021-06-23 16:40:45 +02:00
Ondřej Vejpustek
40b4f679f9 feat(core): implement wrapper for svc_shutdown 2021-06-23 16:40:45 +02:00
Ondřej Vejpustek
311288407e docs(core): document shutdown_privileged 2021-06-23 16:40:45 +02:00
Ondřej Vejpustek
4968d7da53 feat(core): implement svc shutdown 2021-06-23 16:40:45 +02:00
Ondřej Vejpustek
cca9d4b1c4 refactor(core): rename shutdown to shutdown_privileged 2021-06-23 16:40:45 +02:00
Ondřej Vejpustek
7686eb355a fix(core): fix import of random delays 2021-06-23 16:40:45 +02:00
Pavol Rusnak
69d1465e08
refactor(core): pass invert_colors to send_init_seq_ST7789V as argument 
to make the call more flexible
 2021-06-19 19:57:42 +02:00
Pavol Rusnak
18e103bb94
style(core): refactor style of display-stm32_T 2021-06-19 19:54:19 +02:00
matejcik
c06a93cba5 feat(core/rust): propagate bitcoin_only flag to Rust build 2021-06-08 09:55:19 +02:00
Jan Pochyla
8a21e3fc73 feat(core): Add Rust Protobuf codec 2021-06-08 09:55:19 +02:00
Pavol Rusnak
23aa69caea fix(core): unify Features.revision reporting with legacy 2021-06-04 12:50:49 +02:00
Martin Milata
ca836b2e45 chore(core): bump version to 2.4.1 2021-06-02 12:50:22 +02:00
Martin Milata
8c6b93e0bd build(core): account for ARM unwinding info in memory layout 
Currently the 8-byte section is inserted under semi-random name like
.ARM.exidx.text._ZN50_$LT$T$u20$as$u20$core..convert..Into$LT$U$GT$$GT$4into17h79ccbc4bdfe3f200E.
This makes it hard to include it in _codelen that is later baked into
firmware header. This change adds new section because including it in
.flash causes linker error due to mixing "ordered" and "unordered"
sections.

By renaming .exidx to /DISCARD/ we'd drop this info, there may also
exist compiler flag to do that.
 2021-05-21 13:49:42 +02:00
Martin Milata
20fe8552ca build(core/rust): use correct architecture for T1 
TT is Cortex-M4 is Armv7E-M while T1 is Cortex-M3 is Armv7-M:
https://community.arm.com/developer/ip-products/processors/b/processors-ip-blog/posts/armv6-m-vs-armv7-m---unpacking-the-microcontrollers
 2021-05-21 13:49:42 +02:00
Ondřej Vejpustek
6fd4739c5c feat(core): make random delays use chacha_drbg 2021-05-21 13:42:53 +02:00
Ondřej Vejpustek
e1a5f42c81 feat(core): make chacha_drbg more robust 2021-05-21 13:42:53 +02:00
Ondřej Vejpustek
8ee17f69b3 refactor(core): move wait_random and rdi into separate file 2021-05-21 13:42:53 +02:00
matejcik
e015bc0856 build(core/rust): disable nightly-only features 
When we need them, we will re-enable.
 2021-05-21 13:42:10 +02:00
matejcik
5f4240d93c feat(core): preallocate sys.modules to an appropriate size 2021-05-06 13:14:21 +02:00