Martin Milata 8c6b93e0bd build(core): account for ARM unwinding info in memory layout ... Currently the 8-byte section is inserted under semi-random name like .ARM.exidx.text._ZN50_$LT$T$u20$as$u20$core..convert..Into$LT$U$GT$$GT$4into17h79ccbc4bdfe3f200E. This makes it hard to include it in _codelen that is later baked into firmware header. This change adds new section because including it in .flash causes linker error due to mixing "ordered" and "unordered" sections. By renaming .exidx to /DISCARD/ we'd drop this info, there may also exist compiler flag to do that.		2021-05-21 13:49:42 +02:00
..
boardloader	fix(core): don't assert reset flags to allow "reboot to bootloader"	2021-03-10 18:31:51 +01:00
bootloader	feat(core): make random delays use chacha_drbg	2021-05-21 13:42:53 +02:00
bootloader_ci	feat(core): make random delays use chacha_drbg	2021-05-21 13:42:53 +02:00
extmod	refactor(core/usb): do not require serial number on instantiaton of USB	2021-05-06 13:14:21 +02:00
firmware	build(core): account for ARM unwinding info in memory layout	2021-05-21 13:49:42 +02:00
prodtest	feat(core): make random delays use chacha_drbg	2021-05-21 13:42:53 +02:00
reflash	all: rename TREZOR to Trezor where possible	2019-06-17 20:28:29 +02:00
rust	build(core/rust): use correct architecture for T1	2021-05-21 13:49:42 +02:00
segger	style(core): systemview editorconfig reformat	2021-01-26 20:53:38 +01:00
trezorhal	feat(core): make random delays use chacha_drbg	2021-05-21 13:42:53 +02:00
unix	feat(core): make random delays use chacha_drbg	2021-05-21 13:42:53 +02:00
vendorheader	core/headertool: support generating vendor headers with explicit size	2020-02-05 12:23:34 +01:00