arno/trezor-firmware
1
0
Fork 0
mirror of https://github.com/trezor/trezor-firmware.git synced 2024-11-16 04:29:08 +00:00
Code Issues Releases Wiki Activity
11,553 Commits 342 Branches 206 Tags 195 MiB
1a46c7dfdc
Commit Graph

116 Commits

Author SHA1 Message Date
tychovrahe
a89d139dc9 feat(core): increase clock frequency to 180 MHz 2022-11-04 15:10:55 +01:00
Martin Milata
bf7587574d chore(core): bump version to 2.5.4 
[skip_ci]
 2022-11-01 14:03:31 +01:00
tychovrahe
99eaaae28e build(core): redistribute content in flash 
[no changelog]
 2022-10-03 09:43:53 +02:00
tychovrahe
f7b9bb4ef8 feat(core/rust): use dma2d to improve rendering performance, implement text over image and icon over icon functions 2022-09-29 21:50:10 +02:00
tychovrahe
e3d5c178f1 feat(core): enable bus fault and usage fault handlers 
[no changelog]
 2022-09-13 15:04:40 +02:00
tychovrahe
6cf92fd748 feat(core): Introduce stack overflow detection by moving stack to the start of RAM 2022-08-16 17:03:06 +02:00
matejcik
ef47c26272 chore(core,legacy): bump versions 
[skip_ci]
[no changelog]
 2022-08-03 13:10:05 +02:00
TychoVrahe
a762e75fee
fix(core): reintroduce touch controller initialization without power down/up in firmware, fix model R firmware initialization 2022-07-26 15:09:43 +02:00
tychovrahe
c33f92bd72 feat(core): add RGB LED driver for Model R 2022-06-22 09:28:31 +02:00
Ondrej Mikle
7b7318c3aa feat(core/boardloader): add fixed-address boardloader capablities field 2022-06-13 18:18:25 +02:00
Martin Novak
2663801108 perf(firmware): do not initialize touch controller in firmware 2022-06-02 10:30:53 +02:00
Ondrej Mikle
c563c987e1 feat(core): jump back and stay in bootloader for TT via reverse SVC call trampoline 2022-06-01 14:50:59 +02:00
Ondřej Vejpustek
db0da196a8 chore(vendor): update secp256k1-zkp to latest 2022-05-16 16:23:18 +02:00
tychovrahe
f7a3aad9bd feat(core): initial Model R display implementation with framebuffer 2022-05-10 16:49:23 +02:00
grdddj
12da7f301d feat(core): allow for model R in firmware build 
As model R will run on the same computational hardware as model T,
memory_R.ld is just a symbolic link to memory_T.ld.

[no changelog]
 2022-05-06 11:44:52 +02:00
Martin Milata
692ea1415e chore(core): bump version to 2.5.2 
[skip_ci]
 2022-05-04 12:09:14 +02:00
TychoVrahe
7912a7d0d3
build(core,storage): fix conditional compilation for different Trezor models 
* build(core,storage) - Fix conditional compilation for different trezor models

* build(core) - Rename MODEL_* macro to TREZOR_MODEL_*, remove the original TREZOR_MODEL macro (replaced by conditional compilation for QSTR generation)

* build(core) - fixed missing TREZOR_MODEL to TREZOR_MODEL_x changes

[no changelog]
 2022-04-26 13:47:40 +02:00
Martin Milata
30ec1802f4 chore(core): bump version to 2.5.1 
[skip_ci]
 2022-03-30 21:57:54 +02:00
Pavol Rusnak
30a77a76bc
chore(legacy): rename MEMORY_PROTECT flag to PRODUCTION to match core naming (#2003) 2021-12-12 15:45:10 +01:00
Martin Milata
38c526719c chore(core): bump version to 2.4.4 
[skip_ci]
 2021-12-01 14:45:47 +01:00
Ondrej Mikle
219e08d81e build(core): keep bootloader image even for non-production builds 
[no changelog]
 2021-11-23 16:29:38 +01:00
Martin Milata
aa3784f726 build(core): place secp256k1-zkp in FLASH2 to make space for bootloader 
[no changelog]
 2021-11-23 14:51:11 +01:00
Ondřej Vejpustek
ad38d8e324 refactor(crypto,core): make zkp_context_init() return status 2021-11-18 19:05:40 +01:00
matejcik
1d72085b5c feat(core): implement conversion from timestamp to datetime 2021-10-29 11:00:30 +02:00
Ondřej Vejpustek
26463eb3ce feat(core): make core use ecdsa from secp256k1_zkp wherever possible 2021-10-25 14:41:28 +02:00
Pavol Rusnak
9e0cfa6783 fix(core): we don't need separate linker script for zkp 2021-10-25 14:41:28 +02:00
matejcik
32be2c09b9 feat(core): enable f-strings for micropython 
[no changelog]
 2021-10-13 11:53:17 +02:00
Jan Pochyla
2703d714c2 feat(core): add Rust UI components, layouts, text rendering 
[no changelog]
 2021-10-07 15:01:55 +02:00
Ondrej Mikle
6ea4b7b211 fix(core & legacy): better styled compiler checks 2021-09-27 15:42:29 +02:00
Ondrej Mikle
6b849b1d4d fix(core & legacy): avoid accidental build with broken stack protector 2021-09-27 15:42:29 +02:00
Martin Milata
bd005e33df refactor(core): decouple T1 button handling from touch 
[no changelog]
 2021-09-23 12:30:13 +02:00
Martin Milata
aace875fef chore(vendor): bump micropython to 1.17 
Relevant micropython commits:
  d1bfb271d7686708fe8711a177629c8bf6e7f6a6 lib/uzlib: Move uzlib code from extmod to lib.
  4d546713ec8858cbf908de45de11cbfc46a20971 shared: Introduce new top-level dir and move 1st party lib code there.
  ca920f72184c50f61002aa9d5cd01555b1e28b7b py/mpstate: Make exceptions thread-local.
 2021-09-17 11:18:14 +02:00
Pavol Rusnak
d153082c9c chore(vendor): bump micropython to 1.14 
Relevant micropython commits:
  4559bcb4679e04e0a5e24030675676ff6a9803f2 unix: Make mp_hal_delay_ms run MICROPY_EVENT_POLL_HOOK.
 2021-09-17 11:18:14 +02:00
Tomas Susanka
cec1f39a90 chore(core, legacy): bump versions 
[no changelog]
 2021-08-31 12:55:37 +02:00
Martin Milata
81869fc4b0 chore(core): bump version to 2.4.2 
[skip_ci]
 2021-07-08 13:38:29 +02:00
Ondřej Vejpustek
24200e7424 fixup! fix(legacy): make RDI work on T1 2021-06-24 17:34:24 +02:00
Ondrej Mikle
daa94ac941 fix(legacy): make RDI work on T1 2021-06-24 17:34:24 +02:00
Ondřej Vejpustek
4968d7da53 feat(core): implement svc shutdown 2021-06-23 16:40:45 +02:00
Ondřej Vejpustek
cca9d4b1c4 refactor(core): rename shutdown to shutdown_privileged 2021-06-23 16:40:45 +02:00
Ondřej Vejpustek
7686eb355a fix(core): fix import of random delays 2021-06-23 16:40:45 +02:00
Jan Pochyla
8a21e3fc73 feat(core): Add Rust Protobuf codec 2021-06-08 09:55:19 +02:00
Martin Milata
ca836b2e45 chore(core): bump version to 2.4.1 2021-06-02 12:50:22 +02:00
Martin Milata
8c6b93e0bd build(core): account for ARM unwinding info in memory layout 
Currently the 8-byte section is inserted under semi-random name like
.ARM.exidx.text._ZN50_$LT$T$u20$as$u20$core..convert..Into$LT$U$GT$$GT$4into17h79ccbc4bdfe3f200E.
This makes it hard to include it in _codelen that is later baked into
firmware header. This change adds new section because including it in
.flash causes linker error due to mixing "ordered" and "unordered"
sections.

By renaming .exidx to /DISCARD/ we'd drop this info, there may also
exist compiler flag to do that.
 2021-05-21 13:49:42 +02:00
Ondřej Vejpustek
6fd4739c5c feat(core): make random delays use chacha_drbg 2021-05-21 13:42:53 +02:00
Ondřej Vejpustek
8ee17f69b3 refactor(core): move wait_random and rdi into separate file 2021-05-21 13:42:53 +02:00
matejcik
5f4240d93c feat(core): preallocate sys.modules to an appropriate size 2021-05-06 13:14:21 +02:00
Jan Pochyla
6257584951 feat(core): Add Rust bindings to MicroPython and trezorhal 
core: Remove dangling module decls

core: Use new Cargo feature resolver, use external MacOS debug info

core: Rust docs improvements

core: Upgrade bindgen

core: Add test target to Rust

ci: build rust sources

build(core): .ARM.exidx.text.__aeabi_ui2f in t1 firmware size

It's an unwind table for softfloat function inserted by rustc, probably
can be removed to save 8 bytes:
599c58db70/link.x.in (L175-L182)

scons: Remove dead code

core: Move Rust target to build/rust

core: Replace extern with a FFI version

core: Add some explanatory Rust comments

core: Use correct path for the Rust lib

core: Remove Buffer::as_mut()

Mutable buffer access needs MP_BUFFER_WRITE flag. TBD in the Protobuf PR.

core: Improve docs for micropython::Buffer

core: Minor Rust docs changes

core: Rewrite trezor_obj_get_ll_checked

core: Fix incorrect doc comment

core: Remove cc from deps

fixup! core: Rewrite trezor_obj_get_ll_checked

core: update safety comments
 2021-05-05 16:00:21 +02:00
Andrew Kozlik
66823e2893 chore(core,legacy): Bump FIX_VERSIONs due to upgrade to storage version 3. 2021-03-25 14:24:41 +01:00
Pavol Rusnak
814db111b2
feat(core): add define to invert display colors on ST7789V 2021-03-10 16:06:18 +01:00
Pavol Rusnak
5395c542c1
chore(core): update changelog, bump version to 2.3.7 2021-02-13 11:16:11 +01:00